Organization

The organization of this thesis is overviewed as following: Chapter 2 presents the design methodology of Dual-mode LNA. In this chapter, a new topology for wider dynamic range is proposed. Chapter 3 presents the implemented circuit with UMC 0.13μm CMOS technology and measurement results. For shortening the system verification time, a behavior model of dual-gain mode LNA is constructed and demonstrated in Chapter 4. Chapter 5 concludes with a summary of contributions and the future works.

Table 1.5: Advantages / disadvantages of multi gain mode techniques

(2) Impacts on power consumption, NF and input matching are negligible

(1) Switch control voltage may higher than VDD (2) Gain variation is sensitive due to parasitic effects

Current splitting

[8-9] Gain step can be accurately created by setting the ratio of transistor sizes

(1) Power wasting problem (2) High NF in low gain mode

Bias control

[10] (1) S11 and S22 do not degrade during gain changes (2) Peak curves of gain versus frequency are almost at the same frequency

(1) Control range is smaller (2) Complex analogic

(2) Control signals are programmable

(1)P1dB improvement is not enough in low gain mode

(2)NF variation between different modes

Table 1.6: Gain, P1dB, current and NF comparison of multi gain mode techniques Technique Ref Gain

Chapter 2

Dual-gain Mode LNA Design

In this chapter, a CMOS LNA with dual-gain mode for WiMAX application is presented. Section 2.1 describes design concepts for high dynamic range of LNA for WiMAX applications. Section 2.2 introduces the dual-gain mode LNA topology.

Based on this topology, a circuit design by 0.13μm process is shown in section 2.3.

Section 2.4 provides simulation results of this circuit.

2.1 Design Concepts

From previous chapter, the specifications of dual-gain LNA are defined. The goal of this work is to design an LNA which can satisfy defined specifications. The LNA circuit has to be low noise figure, high gain and high linearity performance for wide dynamic range demand. Well matching networks can help to keep high power transfer efficiency between blocks. Moreover, for trend of minimizing size and power consumption in designing consumer electronic products nowadays, IC layout area and power consumption are more important issues than before.

It is a great challenge to balance effects of these issues, due to tradeoffs or conflicts between some of them. If LNA circuit has to be with high gain to reduce

noise, raise g_m is an effective way, but power consumption is raised, too. On the other hand, high gain LNA is suitable for small input signal, but when input signal is large, blocking problem will become seriously. The specifications in previous chapter declare that the requirement of gain and linearity is very severe. Even the dual-gain mode method will be used to release trade-off between gain and linearity specifications, design of proposed LNA is still not easy. There are some popular techniques which can solve gain, linearity and noise problems respectively, and they will be discussed below.

2.1.1 Gain Issue

Figure 2.1: A basic cascode CMOS LNA circuit

In the specification, the LNA power gain shall be more than 17dB in high gain mode. The common-source configuration is suitable for high gain, due to large effective load resistance as r_o of transistor [12]. The cascode configuration, with much larger load than common-source one, can enlarge gain more efficiently and easily.

Figure 2.1 depicts a basic cascode CMOS LNA circuit. The capacitor C_out is usually

very large as a DC block, and it can be ignored for load calculation. The effective load equals to parallel impedances Z2 and ZL. ZL is impedance of resonator which is formed by load inductor L_D and parasitic capacitance C_p. Z₂ is impedance seen from the drain of M2, and it can be derived by following formula:

(

2 2

)

1 2

2 r_o 1 g_m r_o r_o

Z = + + ⋅ ⋅ (6)

As mentioned before, the load is much larger than that of common-source only. But recently, for low power requirement in mobile devices, V_DD is getting smaller, and it gives restrict of using cascode structure. Folded structure or multiple stages can avoid the voltage room restrict, but they have to consume more power.

2.1.2 Linearity Issue

The LNA input IP3 specification in low gain mode is 5.5dBm. Such high linearity requirement is not easy to conquer, and so linearity enhancement technique shall be introduced to proposed LNA. The multiple gated transistor technique [13] is simple to use. The technique comes from the drain current i_DS versus v_gs equation of a common-source amplifier:

The v_gs³ term in (7) plays an important role in the third order intermodulation distortion [13][14]. Thus we can use two or more paralleled transistors with different bias voltage (as multiple gated transistors) to cancel g_m’’ term, and so the linearity of LNA can be enhanced. The concept of this technique is illustrated in Figure 2.2.

In this technique, V_bias2 is lower than V_bias1 with a constant offset. M₂ works in the sub-threshold region for positive gm’’ value by Vbias2, and so as to cancel gm’’ of M1.

Figure 2.2: Schematic and g_m’’ curve of multiple gated transistors technique

Because M₂ works in sub-threshold region, the current of M₂ is very small, and it gives no impact of power consumption. The gain will degrade in this technique, but it is not serious.

The linearity improvement is not quite obvious in the first paper of this technique (3dB OIP3 improvement in [13]). A formula of small signal circuit derived in [15]

gives a reason about the limit of original multiple gated transistors technique, where L is an inductor of source degeneration, and Z₁ is input impedance:

ε

In the last term of (9), the contribution of nonlinearity is not only comes from gm’’.

The original technique works only in low frequency operation, due to the last term is near to zero in low frequency. A modified technique which improves IIP3 near 20dB is presented in [16]. It uses a single tapped inductor for different source degeneration inductor values of two transistors. The circuit is depicted in Fig. 2.3.

Because the inductor value seen from the source of M₁ and M₃ are different, they can be adjusted to cancel the last term of (9) (as gm second-order distortion). M1

M₁

V_in M₃

V_bias3 V_bias1 C_B3

C_B1 L₂

L1

V_bias2

M₂ L₄

V_out C_B2

R3 R1

V_DD

Figure 2.3: Schematic of modified derivative superposition LNA (Bias circuit and input matching network are not shown)

works in active region, and M3 works in sub-threshold region. M2 forms the circuit as a cascode structure. The gain performance is good in this LNA, and gain degradation of using this techinique is smaller than 1dB. This technique is very useful for conquering requirements of proposed LNA.

2.1.3 Noise Issue

To be the first stage of receiver circuit, the noise problem is the most important issue in designing LNA circuit. Full integrated IC is popular for the system-on-chip design, but the low Q factor of on-chip inductor gives a challenge to it. The source degeneration technique is widely used for input matching (Figure 2.4). In this technique, the input signal is directly through the inductor Lin. If the Q factor of Lin is small, there will be a parasitic resistance on it, and it generates noise. Because the

inductor is just after the input port, it gives serious impact to LNA noise performance.

Thus the input inductor shall be carefully designed.

Figure 2.4: The source degeneration technique

The size selection of common-gate transistor is also an issue of noise performance.

The cascode stage has a smaller impact on the overall NF than input stage [17], but it plays an important role when the input stage is optimized. The [17] paper gives an reference of selecting the size of common-gate transistor.

The specification decided the same NF requirement for dual gain modes. Thus the degradation of NF performance in low gain mode has to be avoided. In the [9] circuit which is introduced in previous chapter, the noise variation between different gain modes is smaller. This technique can be an important design reference for the noise issue.

2.2 Dual-gain Mode Topology

2.2.1 Design Footprints

From the specifications in previous chapter, the LNA has to be designed with dual-gain mode. Two modes shall be integrated in one circuit to save chip area. To

realize this requirement, two circuits for different modes are designed first to see the common points. If the LNA can split into two circuits, one is designed for high gain mode and the other is for low gain mode, the design will be quite simple and no new techniques needed. Cascode configuration can be used for high gain requirement in high gain mode circuit. Low gain mode does not use cascode configuration for larger voltage room of common-source stage. Multiple gated transistor technique can be used for high linearity requirement in both gain mode circuits. The first designed structures of two mode circuits are illustrated in Figure 2.5. The high gain mode circuit structure is just the same as the circuit in [18].

(a) (b)

Figure 2.5: First designed LNA (a) for high gain mode; (b) for low gain mode.

Although the optimizations of these two circuits may lead to different sizes of components, the major difference between them is the existence of M₂ transistor. If M2 transistor can be “short” by giving different bias in high gain mode circuit, these two circuits can be merged into one.

The bias control and core switching techniques in [10][11] offered good references here. Adjusting Vbias2 may cause obviously gain variation, even the gain can lower than the circuit without cascode structure in Figure 2.5(b). But the linearity performance will be seriously degraded; even though the gain is already lower.

Complex bias control circuit is another drawback which is mentioned before. On the other hand, the core switching technique does not degrade linearity performance during gain control, but the gain range is quite small. The LNA, which combines core switching technique (2 bits only), is illustrated in Figure 2.6.

Figure 2.6: The LNA circuit with core switching technique

In Figure 2.6, if the transistor M2B can short vd1 and vd2 two points when it is on (and M₂ shall be off), the merged circuit can be realized. V_bias2B shall bias M_2B into triode region for the minimum voltage room consumption. M2B works in triode region when (V_bias2B—v_d2) is smaller than V_t3. But v_d2 is nearly to V_DD here, M_2B is impossible to operate in triode region except Vbias2B can be larger than VDD. The

over-V_DD bias circuit is major problem of this structure.

2.2.2 The Proposed Dual-gain Mode LNA Topology

The transistor M2B in Figure 2.6 can work as a real switch if PMOS is used. The schematic of proposed LNA is depicted in Figure 2.7. The input, output matching networks and source degeneration inductor is added in the circuit. The PMOS M2B

can easily bias in the triode region by setting V_bias2B to zero, since the V_sg of M_2B reaches almost as VDD voltage, and Vsg-|Vth| is still much larger than Vsd of M2B. The circuit operation and analyses are described in following subsections.

Figure 2.7: The proposed Dual-gain mode LNA circuit schematic

A. Circuit structure and operation

The proposed LNA circuit can be split into 4 stages: input matching stage, gm

(Multiple gated transistors, MGTR) stage, switching stage and output matching stage.

Capacitors CB1, CB2 and CB3 are with large size as DC blocks. Resistors R1, R3 are also with large size, and they are for supplying bias without degrading RF signal. The input matching stage is formed by input inductor Lin and source degeneration inductor L_S.

The gm stage is formed by M1 and M3 transistors. It uses the MGTR [13] (or Derivative Superposition named in [16]) technique to meet the IIP3 requirement. M₁ works in active region and off, and M3 works in sub-threshold region. The biases of M₁ and M₃ can be adjusted for the best IIP3 performance.

The switching stage is the major contribution of this new technique. In high gain mode, M₂ is on by setting V_bias2 to high, and V_bias2B is also set to high to turn off M_2B. Thus the circuit becomes to cascode configuration, and high gain can be realized. On the other hand, M₂ is off by setting V_bias2 to low, and V_bias2B is also set to low to turn on M2B in low gain mode. Because in the same mode, the voltage level of Vbias2 and V_bias2B are the same, two bias points can be combined into one, and the control signal can be given from baseband. The M2B works in triode region, which Ron is small, and it does not consume much voltage room. The voltage at v_d1 will be much higher than in the cascoded high gain mode, so the swing in the gm stage can be larger.

The output matching stage contains load inductor L_load, matching network L_out and Cout. The load inductor Lload and parasitic capacitances (from M2 and M2B) form a resonator, which shall resonate at the center frequency of operating band (2.5GHz).

B. Circuit analysis in input matching issue

The degeneration inductor LS can help to make real part of input impedance to 50Ω, as following equation describes:

⎥⎦ Inductor L_S locates between source of the transistor M₁ and ground. C_T represents capacitor with Cgs and Miller effect of Cgd. Because loading at the drains of M1 and M₃ is different between two gain modes (by whether the circuit is cascoded or not), CT will change their value. The variation of CT can be controlled by designing different g_m for different modes. g_m does not only effect C_T, but directly link to the real value of Z_in. The optimum g_m should keep Z_in to 50Ω and minimize the variation between two gain modes. It can be obtained by carefully designing sizes and biases of transistor M1, M3.

C. Linearity issue

The IIP3 equation derived in [16] can be modified for this new technique without taking the inductor between source of M3 and ground (as L1 in [16]) into account (only g_m stage):

The impact of not using the inductor L1 is that the second-order distortion may not be cancelled as well as before. The first and third terms of (13) are both raised their value. But since the first and third terms are with different signs, and the numerator of (12) is also raised when the denominator ε is raised, the impact of not using L1 is quite

small. By the way, the absence of L₁ gives a convenience of designing if the value of L1 is hard to implement.

D. Noise issue

The MGTR F_min derivation in [16], based on assumption of long channel device but without degeneration inductor, is given by:

)]

In this equation, the drain currents in both M₁ and M₃ transistors play important roles in noise performance. Because sizes of transistors are unchanged between high and low gain modes, the variation of NF between different gain modes will follow the value of drain currents. By the way, the switching stage structure is different in two modes. Even the currents condition will satisfy the minimum NF variation, the noise contribution of switching stage is still greater in low gain mode, due to saturation mode of M_2B and less gain of g_m stage. The problem can be reduced by giving a little more current to M3 which is working in sub-threshold region (Fmin will rapidly increases with v_gs falling below v_th [16].).

2.3 Circuit Design

This section introduces the size selection of each component. The UMC 0.13μm RF CMOS model is applied to this design, and the ADS RFDE simulation tool is used

for design supporting.

2.3.1 Input Matching Stage

The size of source degeneration inductor can be decided from three issues: First, the real part of Z_in equals to g_mL_S/C_T in (10). Second, large size of L_S will degrade gain performance. The last one is the adjustment of linearity performance optimization. The size is usually smaller than 1nH in many literatures, and it needs to realize by bondwire. But the circuit design here is fully-integrated, and such small inductor is also supported in the UMC 0.13μm model. The LS size is decided as 0.37nH.

To cancel the image part of input impedance in (10), the input inductor Lin shall be [1/(ω²C_gs)]-L_S, and it is near to 10nH. The quality factor affects the noise performance of LNA very much, since the parasitic resistance of Lin generates noise at the initial stage. It can be proved by Friis’ equation. In the circuit the Lin is designed as 5.8nH.

The sizes of DC blocks and resistors are designed for not disturbing RF signal transmission. DC block is better of larger size, but it occupies too large area on the chip. The 4.57pF size of DC blocks is decided for smaller area and less degradation of signal coupling. The resistors value is nearly 10kΩ.

2.3.2 gm (MGTR) Stage

Designing the size of transistors M1 and M3 shall consider following issues: Cgs

for input matching, g_m for gain, and g_m’’ for MGTR technique. To make 17dB gain in high gain mode, M1 size shall be large enough for large gm. But if M1 size is too large,

DC current as well as power consumption will be a problem. On the other hand, M₃ size has to be much larger than M1. Power issue here is not serious as M1, due to the current is very small. Small current makes small variation, so the positive g_m’’ value is smaller than negative gm’’ offered by the same size M1. Moreover, the optimum linearity performance points are different between two gain modes. It needs to be balanced in M3 size choosing. The final sizes (width) of M1 and M3 are decided as 96μm and 240μm, respectively.

2.3.3 Switching and Output Matching Stage

The parasitic capacitances of M2, M2B and the load inductor Lload form a load resonator. It shall resonate at the center frequency of the band. Because the size of M₂ and M2B gives a directly connection to parasitic capacitances, this is an issue for designing the size of M₂ and M_2B. Moreover, the M_2B size shall be larger for lower Ron, so that the consumption of voltage room by M2B will be smaller. The size of M2

and M2B are decided as 192μm and 240μm, respectively. Lload is designed as 5.34nH.

Besides the Lload and parasitic capacitances, capacitor Cout and inductor Lout are also a part of output matching. C_out as 409fF, and Lout as 2.96nH are designed. All the component sizes are listed in Table 2.1.

2.4 Simulation Results

The circuit simulation is accomplished with ADS RFDE simulation tools. The parasitic capacitances in layout are considered in simulations. Table 2.2 shows the DC simulation of this circuit. Table 2.3 presents S-parameter simulation results, with results at 2.5GHz and the worst case in the band. Table 2.6 describes harmonic

simulation results, under the conditions of that reference input power = -40dBm, 2.5GHz operating frequency and 10MHz offset of two tone test. Figure 2.8 to 2.11 show the curve of S-parameter and harmonic balance simulations results in 1-4 GHz.

Table 2.1: The component size list of proposed LNA Transistors μm / μm Inductors nH

M₁ 96 / 0.12 L_in 5.790

M3 240 / 0.12 LS 0.370

M2 192 / 0.12 Lload 5.344

M_2B 240 / 0.12 L_out 2.957

Capacitors pF Resistors kOhm

C_B1 4.568 R₁ 9.96

CB2 4.568 R2 9.96

CB3 4.568

Cout 0.409

Table 2.2: DC simulation results

Post-Sim I_D (mA) Power (mW) V_bias1 (mV) V_bias3 (mV)

HG mode 7.49 8.99 540 360

LG mode 6.15 7.38 500 280

Table 2.3: S-parameter simulation results

Post-Sim S21 (dB) NF (dB) S11 (dB) S22 (dB) S12 (dB) HG mode (2.5G) 17.69 1.95 -8.34 -4.97 -35.7

Worst case 17.22 2.08 -6.44 -4.17 -35.46

HGM Spec 17 2.5 -15 -15

LG mode (2.5G) 8.56 2.12 -21.98 -6.79 -20.55

Worst case 7.29 2.29 -16.92 -6.46 -20.15

LGM Spec 8 2.5 -15 -15

Table 2.4: Harmonic Balance simulation results Post-Sim IIP3 (dBm) IIP3 w/o

MGTR (dBm)

P1dB (dBm)

HG mode 1.443 -2.11 -15.48

HGM spec -4.5 -15

LG mode 5.376 1.076 -8.04

LGM Spec 5.5 -5

(a) S11 (b) S22

Figure 2.8: Smith charts of S11 and S22

(a) S11 (b) S22

Figure 2.9: S11 and S22 curves in dB

High gain mode Low gain mode

High gain mode Low gain mode

(a) S21 (b) S12

(c) NF (d) P1dB

Figure 2.10: S21, S12, NF, P1dB simulation results

(a) High gain mode (b) Low gain mode

Figure 2.11: HB IIP3 simulation results ^output

IM3

IM3 w/o MGTR High gain mode

Low gain mode

Chapter 3

Implementation and Experimental Results

In this chapter, the proposed circuit is implemented and measured. The circuit is implemented by the UMC 0.13μm process. Section 3.1 addresses layout consideration.

The proposed technique tapes out two times. Section 3.2 presents measurement results

The proposed technique tapes out two times. Section 3.2 presents measurement results

在文檔中 應用於WiMAX之雙增益模式互補金氧半低雜訊放大器設計 (頁 26-0)