Simulation Results - Noise issue - Dual-gain Mode LNA Design

Chapter 2 Dual-gain Mode LNA Design

D. Noise issue

2.4 Simulation Results

The circuit simulation is accomplished with ADS RFDE simulation tools. The parasitic capacitances in layout are considered in simulations. Table 2.2 shows the DC simulation of this circuit. Table 2.3 presents S-parameter simulation results, with results at 2.5GHz and the worst case in the band. Table 2.6 describes harmonic

simulation results, under the conditions of that reference input power = -40dBm, 2.5GHz operating frequency and 10MHz offset of two tone test. Figure 2.8 to 2.11 show the curve of S-parameter and harmonic balance simulations results in 1-4 GHz.

Table 2.1: The component size list of proposed LNA Transistors μm / μm Inductors nH

M₁ 96 / 0.12 L_in 5.790

M3 240 / 0.12 LS 0.370

M2 192 / 0.12 Lload 5.344

M_2B 240 / 0.12 L_out 2.957

Capacitors pF Resistors kOhm

C_B1 4.568 R₁ 9.96

CB2 4.568 R2 9.96

CB3 4.568

Cout 0.409

Table 2.2: DC simulation results

Post-Sim I_D (mA) Power (mW) V_bias1 (mV) V_bias3 (mV)

HG mode 7.49 8.99 540 360

LG mode 6.15 7.38 500 280

Table 2.3: S-parameter simulation results

Post-Sim S21 (dB) NF (dB) S11 (dB) S22 (dB) S12 (dB) HG mode (2.5G) 17.69 1.95 -8.34 -4.97 -35.7

Worst case 17.22 2.08 -6.44 -4.17 -35.46

HGM Spec 17 2.5 -15 -15

LG mode (2.5G) 8.56 2.12 -21.98 -6.79 -20.55

Worst case 7.29 2.29 -16.92 -6.46 -20.15

LGM Spec 8 2.5 -15 -15

Table 2.4: Harmonic Balance simulation results Post-Sim IIP3 (dBm) IIP3 w/o

MGTR (dBm)

P1dB (dBm)

HG mode 1.443 -2.11 -15.48

HGM spec -4.5 -15

LG mode 5.376 1.076 -8.04

LGM Spec 5.5 -5

(a) S11 (b) S22

Figure 2.8: Smith charts of S11 and S22

(a) S11 (b) S22

Figure 2.9: S11 and S22 curves in dB

High gain mode Low gain mode

(a) S21 (b) S12

Figure 2.10: S21, S12, NF, P1dB simulation results

(a) High gain mode (b) Low gain mode

Figure 2.11: HB IIP3 simulation results ^output

IM3

IM3 w/o MGTR High gain mode

Low gain mode

Chapter 3 Implementation and Experimental Results

In this chapter, the proposed circuit is implemented and measured. The circuit is implemented by the UMC 0.13μm process. Section 3.1 addresses layout consideration.

The proposed technique tapes out two times. Section 3.2 presents measurement results and analysis of DUT 1, and the new version DUT 2.

3.1 Layout Consideration

RF circuit is very sensitive to the parasitic effects. The signal path shall be carefully arranged by following considerations. First, the parasitic resistance shall be avoided. The narrow path or vias generate more parasitic resistance, and thus they may seriously degrade the noise performance. Second, the distance between two paths or components shall be larger to avoid mutual inductance or parasitic capacitance.

Third, to avoid the coupling noise from noisy substrate, the top metal layer is used for signal path. The last consideration is that the path shall be as short and straight as possible. If there is a branch on the path, the distance of two paths shall be designed to

the same to avoid phase variation.

In the component arrangement, it shall be arrange as symmetric as possible for same components, and thus the process variation between these components can be mitigated. Also, the usage of maximum finger number of transistor is suggested by [19]. Large finger number leads to lower process variation and better model fitting. In addition, the MOS capacitors are used at each DC port. They work as bypassing capacitors. The noise coming from biases can be filtered by them. Figure 3.1 illustrates the layout of the DUT 1. The layout is accomplished with Cadence Virtuoso editor. The die area is 0.85×1μm².

Figure 3.1: Layout of DUT 1

3.2 Measurement and Analysis

3.2.1 Measurement Setup

The measurement is on wafer testing with NDL support. The setup of the

measurement is described in Figure 3.2. ESG, Noise analyzer, Network analyzer and Power spectrum analyzer are used. The DC 6pin probe is used for 5 biases and 1 ground. Two RF GSG probes are used for input and output.

Figure 3.2: Measurement setup

3.2.2 Measurement Results

The measurement results are presented in following tables and figures. Table 3.1 describes the DC measurement results. Table 3.2 lists the S-parameter and NF results.

Table 3.3 presents harmonic balance results. The post-simulation results of DUT 1 are also listed in these tables for comparison. Figure 3.3 to 3.5 show the curves of measurement and post-simulation.

Table 3.1: DC measurement results Measured

ID (mA)

Post-Sim ID (mA)

Vbias1 (mV) Vbias3 (mV)

HG mode 7.375 2.28 540 360

LG mode 6.249 10.49 500 280

Table 3.2: S-parameter measurement results

S21 (dB) NF (dB) S11 (dB) S22 (dB) S12 (dB) HG mode (2.5G) 11.8 2.465 -5.193 -6.632 -34.43

Worst case 10.01 2.8 -3.876 -5.647 -33.56

Post-Sim (2.5G) 17.611 2.668 -12.757 -5.727 -37.627

HGM Spec 17 2.5 -15 -15

LG mode (2.5G) 8.452 2.185 -4.913 -7.808 -26.56

Worst case 6.62 2.44 -4.124 -7.391 -25.51

Post-Sim (2.5G) 8.625 2.774 -12.064 -6.494 -22.629

LGM Spec 8 2.5 -15 -15

Table 3.3: Harmonic balance measurement results Pre-Sim IIP3 (dBm) IIP3 w/o

MGTR (dBm)

P1dB (dBm)

HG mode -2.073 -1.331 -7.1

Post-Sim 4.895 -2.964 -16.12

HGM spec -4.5 -15

LG mode 2.761 1.414 -11.46

Post-Sim 5.973 1.3 -7.94

LGM Spec 5.5 -5

(a) HGM S11 (b) HGM S22

(e) LGM S11 (f) LGM S22

(g) LGM S21 (h) LGM S12

Figure 3.3: S-parameter measurement and post-simulation results

(a) High gain mode (b) Low gain mode Figure 3.4: NF measurement and post-simulation results

(a) HGM IIP3 (b) LGM IIP3

Figure 3.5: Harmonic balance measurement results

3.2.3 Analysis

In the measurement results, the DC current variation between post-simulation and measurement is the first problem. DC current is only one third of post-simulation in high gain mode, and 1.6 times of post-simulation in low gain mode. This variation affects gain and P1dB performances. Because the DC current is very low in high gain mode, gain is degraded, and P1dB performance is better. On the contrary, larger current in low gain mode results in higher gain and worse P1dB performance.

The MGTR technique is used in this circuit, but the function is failed. There is almost no IIP3 improvement (even degrading) when using MGTR technique. To find the best IIP3, the bias voltage cab be rearranged. But In the both modes, the current variations are all very small when transistor bias is varying from 0V to V_DD. It is impossible for such low variation, unless the transistor M1, M3, or both M1 and M3 are failed. The fail of transistors is the most likely reason of not fitting between measurement and post-simulation results. The reason of failure of transistors is that the bias voltage may not transfer to gate. Besides, the parasitic and EM effects may give some impact in measurement.

3.2.4 New considerations

From the previous experiences, a new device under test is designed for better performances. The noise and the gain performance are not fit to the specification in overall frequency bands. It is because the trade-off adjustment. For example, the input inductor shall be large for input matching, but the NF may serious degrade by low Q factor of large inductor. New DUT 2 gives more considerations of selecting these components. The layout of DUT 2 is illustrated in Figure 3.6. The comparisons of

component sizes are listed in Table 3.4, and the comparisons of gain and NF simulations are illustrated in Figure 3.7. In addition, the line width of signal and bias path are designed to be larger to prevent signal path (or transistor) fail.

Figure 3.6: Layout of DUT 2

Table 3.4: Component size comparisons of DUT1 and DUT2

Width (μm) DUT1 DUT2 Lin DUT1 DUT2

M₁ 100 96 size (nH) 8.756 5.790

M3 160 240 Q (2.5GHz) 10.15 10.55

M2 200 192 R (Ω) 13.546 8.622

M_2B 300 240

DUT1 DUT2 DUT1 DUT2

L_S (nH) 0.370 0.370 L_out (nH) 2.976 2.957 Lload (nH) 5.326 5.344 Cout (pF) 0.409 0.409

(a) HGM S21 (b) HGM NF

Figure 3.7: Gain and Noise comparisons between DUT1 and DUT2

DUT 2 DUT 1

Chapter 4 Behavior Model of Proposed LNA

Due to shorter time-to-market period nowadays, the behavior model of LNA circuit shall be constructed to reduce system verification time. In paper [20], a behavior model archives 0.79% error and 87% simulation time reduction. In this chapter, a behavior model of proposed LNA is constructed. Section 4.1 describes the issues of behavior model construction, and Section 4.2 is the simulation results.

4.1 Issues of Behavior Model Construction

The behavior model of LNA shall fit the following parameters: S-parameter, IIP3, P1dB and NF. The model can be constructed into three stages: input stage, gm stage and output stage. Input stage can be designed to fit S11 and noise performances. Gm stage can be constructed to fit S21 and linearity performances. Output stage can be arranged to fit S22.

The behavior model is constructed by verilog-a language. In proposed verilog-a file, there are three ports (in, out, gnd) and two parameters (mode control, MGTR control). The two parameters can be controlled by simulators for different gain mode or MGTR operations.

The model construction bases on the real components. For the passive components, there are some simple model can be used to substitute the complex model which offers by the foundry. The simple model is illustrated in Figure 4.1. In the figure, the shaded component is the most important one, and the size value is limited to equal to the revealed value.

Figure 4.1: Simple model of passive components

Figure 4.2: Input stage of LNA behavior model

The input stage model is presented in Figure 4.2. In the circuit, the bias resistor is

ignored. The bias resistor just effects lower frequency reaction. The part A in the input stage is constructed all by passive components. Thus when the mode is changed, values in part A do not need to change. The C_gs1, R₅ and C_gs3 form the model of transistors M1 and M3. The sizes of these components will change in different gain modes. The input noise sources, which dominate noise performance of LNA circuit, are placed at the gates of two transistors.

The construction of output stage is most likely the input stage. Figure 4.3 shows the output stage. Only Cd and Rout need to change value when gain mode changes.

Figure 4.3: Output stage of behavior model

The structure of gm stage will change in different gain modes. In high gain mode, the g_m stage will be formed by two small gm stages: common-source g_m stage and common-gate gm stage. In low gain mode, the gm stage will be formed by common-source g_m and a resistor R_on. The common-source g_m can split to two paths to simulate the MGTR technique. In the common-source gm, it can be written as a 3-order equation to simulate the P1dB and IIP3 performance.

4.2 Simulation Results

The comparisons of constructed behavior model versus the transistor level simulation results are illustrated in Figure 4.4 to 4.5. Table 4.1 lists the root mean square error values in the passband.

(a) HGM S11 and S22 (in dB) (b) LGM S11 and S22 (in dB)

(e) HGM S11 and S22 (Image part) (f) LGM S11 and S22 (Image part)

Figure 4.4: S11 and S22 Comparisons

S11 (behavior level) S11 (transistor model) S22 (behavior level) S22 (transistor model)

(a) HGM S21 (b) LGM S21

(e) HGM P1dB (f) LGM P1dB

Figure 4.5: S21, NF and P1dB Comparisons

After the behavior model constructed, it can be used in the system co-simulation.

The co-simulation platform shows in the Figure 4.6. We simulated with system block (which just lists some parameters), transistor level and behavior model in system co-simulation, and compared the performances of BER and simulation times. These

Behavior model Transistor level

simulations based on the condition of 1.5MHz channel bandwidth and QPSK 1/2 modulation. The simulation results are illustrated in Figure 4.7. The simulation time of behavior model is reduced to 84%.

Table 4.1: The RMSE values in the passband RMSE High gain mode Low gain mode

S11 (dB) 0.433 0.434

S11 real (dB) 0.016 0.016 S11 image (dB) 0.019 0.014

S22 (dB) 0.339 0.394

S22 real (dB) 0.013 0.028 S22 image (dB) 0.019 0.015

S21 (dB) 0.098 0.4

NF (dB) 0.287 0.34

Figure 4.6: WiMAX LNA co-simulation platform

BER performances Transistor Level:

Behavior model:

System block:

8.137x10^-4 2.181x10^-5 7.978x10^-4

Figure 4.7: System co-simulation results

Chapter 5 Conclusions

5.1 Summary

In this thesis, a 2.3-2.7GHz dual-gain mode CMOS LNA for WiMAX standard is implemented in a 0.13μm CMOS tech. The chip is fully integrated. A new technique of dual-gain mode LNA circuit is developed. The circuit needs only one common input matching network for different gain modes. The gain of LNA reaches 17dB in high gain mode, and IIP3 reaches 5.9dBm in low gain mode. A behavior model is constructed for facilitating design cycle.

5.2 Future Works

The WiMAX system supports many different channel bandwidths and modulations. The complete simulation of system verification takes a lot of time. In addition, the behavior model construction time is not short, more efficient way to generate model will be developed. Control and bias circuit will be co-designed with mixer, analog-baseband or baneband circuit design.

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Vita

姓名 : 梁書旗性別 : 男

出生地 : 台北縣

生日 : 民國六十七年十月三日

地址 : 台北縣蘆洲市重陽街 112 號七樓

學歷 : 國立交通大學電子工程研究所碩士班 2005/09~2007/06

國立清華大學電機工程學系 1997/09~2002/06 台北市立建國高級中學 1994/09~1997/06 論文題目 : Design of Dual-gain Mode CMOS LNA for WiMAX Applications

應用於 WiMAX 之雙增益互補金氧半低雜訊放大器設計

在文檔中應用於WiMAX之雙增益模式互補金氧半低雜訊放大器設計 (頁 41-0)