New considerations

From the previous experiences, a new device under test is designed for better performances. The noise and the gain performance are not fit to the specification in overall frequency bands. It is because the trade-off adjustment. For example, the input inductor shall be large for input matching, but the NF may serious degrade by low Q factor of large inductor. New DUT 2 gives more considerations of selecting these components. The layout of DUT 2 is illustrated in Figure 3.6. The comparisons of

component sizes are listed in Table 3.4, and the comparisons of gain and NF simulations are illustrated in Figure 3.7. In addition, the line width of signal and bias path are designed to be larger to prevent signal path (or transistor) fail.

Figure 3.6: Layout of DUT 2

Table 3.4: Component size comparisons of DUT1 and DUT2

Width (μm) DUT1 DUT2 Lin DUT1 DUT2

M₁ 100 96 size (nH) 8.756 5.790

M3 160 240 Q (2.5GHz) 10.15 10.55

M2 200 192 R (Ω) 13.546 8.622

M_2B 300 240

DUT1 DUT2 DUT1 DUT2

L_S (nH) 0.370 0.370 L_out (nH) 2.976 2.957 Lload (nH) 5.326 5.344 Cout (pF) 0.409 0.409

(a) HGM S21 (b) HGM NF

(c) LGM S21 (d) LGM NF

Figure 3.7: Gain and Noise comparisons between DUT1 and DUT2

DUT 2 DUT 1

Chapter 4

Behavior Model of Proposed LNA

Due to shorter time-to-market period nowadays, the behavior model of LNA circuit shall be constructed to reduce system verification time. In paper [20], a behavior model archives 0.79% error and 87% simulation time reduction. In this chapter, a behavior model of proposed LNA is constructed. Section 4.1 describes the issues of behavior model construction, and Section 4.2 is the simulation results.

4.1 Issues of Behavior Model Construction

The behavior model of LNA shall fit the following parameters: S-parameter, IIP3, P1dB and NF. The model can be constructed into three stages: input stage, gm stage and output stage. Input stage can be designed to fit S11 and noise performances. Gm stage can be constructed to fit S21 and linearity performances. Output stage can be arranged to fit S22.

The behavior model is constructed by verilog-a language. In proposed verilog-a file, there are three ports (in, out, gnd) and two parameters (mode control, MGTR control). The two parameters can be controlled by simulators for different gain mode or MGTR operations.

The model construction bases on the real components. For the passive components, there are some simple model can be used to substitute the complex model which offers by the foundry. The simple model is illustrated in Figure 4.1. In the figure, the shaded component is the most important one, and the size value is limited to equal to the revealed value.

Figure 4.1: Simple model of passive components

Figure 4.2: Input stage of LNA behavior model

The input stage model is presented in Figure 4.2. In the circuit, the bias resistor is

ignored. The bias resistor just effects lower frequency reaction. The part A in the input stage is constructed all by passive components. Thus when the mode is changed, values in part A do not need to change. The C_gs1, R₅ and C_gs3 form the model of transistors M1 and M3. The sizes of these components will change in different gain modes. The input noise sources, which dominate noise performance of LNA circuit, are placed at the gates of two transistors.

The construction of output stage is most likely the input stage. Figure 4.3 shows the output stage. Only Cd and Rout need to change value when gain mode changes.

Figure 4.3: Output stage of behavior model

The structure of gm stage will change in different gain modes. In high gain mode, the g_m stage will be formed by two small gm stages: common-source g_m stage and common-gate gm stage. In low gain mode, the gm stage will be formed by common-source g_m and a resistor R_on. The common-source g_m can split to two paths to simulate the MGTR technique. In the common-source gm, it can be written as a 3-order equation to simulate the P1dB and IIP3 performance.

4.2 Simulation Results

The comparisons of constructed behavior model versus the transistor level simulation results are illustrated in Figure 4.4 to 4.5. Table 4.1 lists the root mean square error values in the passband.

(a) HGM S11 and S22 (in dB) (b) LGM S11 and S22 (in dB)

(c) HGM S11 and S22 (Real part) (d) LGM S11 and S22 (Real part)

(e) HGM S11 and S22 (Image part) (f) LGM S11 and S22 (Image part)

Figure 4.4: S11 and S22 Comparisons

S11 (behavior level) S11 (transistor model) S22 (behavior level) S22 (transistor model)

(a) HGM S21 (b) LGM S21

(c) HGM NF (d) LGM NF

(e) HGM P1dB (f) LGM P1dB

Figure 4.5: S21, NF and P1dB Comparisons

After the behavior model constructed, it can be used in the system co-simulation.

The co-simulation platform shows in the Figure 4.6. We simulated with system block (which just lists some parameters), transistor level and behavior model in system co-simulation, and compared the performances of BER and simulation times. These

Behavior model Transistor level

simulations based on the condition of 1.5MHz channel bandwidth and QPSK 1/2 modulation. The simulation results are illustrated in Figure 4.7. The simulation time of behavior model is reduced to 84%.

Table 4.1: The RMSE values in the passband RMSE High gain mode Low gain mode

S11 (dB) 0.433 0.434

S11 real (dB) 0.016 0.016 S11 image (dB) 0.019 0.014

S22 (dB) 0.339 0.394

S22 real (dB) 0.013 0.028 S22 image (dB) 0.019 0.015

S21 (dB) 0.098 0.4

NF (dB) 0.287 0.34

Figure 4.6: WiMAX LNA co-simulation platform

BER performances Transistor Level:

Behavior model:

System block:

8.137x10^-4 2.181x10^-5 7.978x10^-4

Figure 4.7: System co-simulation results

Chapter 5

Conclusions

5.1 Summary

In this thesis, a 2.3-2.7GHz dual-gain mode CMOS LNA for WiMAX standard is implemented in a 0.13μm CMOS tech. The chip is fully integrated. A new technique of dual-gain mode LNA circuit is developed. The circuit needs only one common input matching network for different gain modes. The gain of LNA reaches 17dB in high gain mode, and IIP3 reaches 5.9dBm in low gain mode. A behavior model is constructed for facilitating design cycle.

5.2 Future Works

The WiMAX system supports many different channel bandwidths and modulations. The complete simulation of system verification takes a lot of time. In addition, the behavior model construction time is not short, more efficient way to generate model will be developed. Control and bias circuit will be co-designed with mixer, analog-baseband or baneband circuit design.

Bibliography

[1] WiMAX Forum, http://www.wimaxforum.org/technology/

[2] A. Amer, E. Hegazi, H. Ragai, “A Low-Power Wideband CMOS LNA for WiMAX”, IEEE TCS-II, Vol. 54, Issue 1, pp. 4-8, Jan 2007.

[3] IEEE, IEEE Standard 802.16-2004, Oct 2004.

[4] IEEE, IEEE Standard 802.16e-2005, Feb 2006.

[5] B. Razavi, RF Microelectronics, Prentice Hall, 1998.

[6] H. T. Friis, “Noise Figure of Radio Receivers”, Proc. IRE, Vol. 32, pp.419-422, July 1944.

[7] Z. Li, R. Quintal, Kenneth K. O, “A Dual-Band CMOS Front-End With Two Gain Modes for Wireless LAN Applications”, IEEE JSSC, Vol. 39, No. 11, pp.

2069- 2073, Nov 2004.

[8] C. D. Hull, J. L. Tham, R. R. Chu, “A Direct-Conversion Receiver for 900MHz (ISM Band) Spread-Spectrum Digital Cordless Telephone”, IEEE JSSC, Vol. 31, No. 12, pp. 1955-1963, Dec 1996.

[9] K. L. Fong, “Dual-Band High-Linearity Variable-Gain Low-Noise Amplifiers for Wireless Applications”, IEEE ISSCC Dig. Tech Papers, pp. 224-225, Feb 1999.

[10] Y. S. Wang, L. H. Lu, “5.7GHz low-power variable-gain LNA in 0.18μm CMOS”, IEE Electronic Letters, Vol. 41, No. 2, pp. 66-67, Jan 2005.

[11] K. H. Cheng, C. F. Jou, “A Novel Gain Control LNA for 2.4GHz Application using 0.18um CMOS”, 48th Midwest Symposium on Circuit and Systems, pp.

1330-1333, Aug 2005.

[12] A. S. Sedra, K. C. Smith, Microelectronic Circuits, 4th. Ed., Oxford University Press, 1998.

[13] B. Kim, J. S. Ko, K. Lee, “A New Linearization Technique for MOSFET RF Amplifier Using Multiple Gated Transistors”, IEEE Microwave and Guided Wave Letters, Vol. 10, No. 9, pp. 371-373, Sept 2000.

[14] S. Tanaka, F. Behbahani, A. A. Abidi, “A Linearization Technique for RF CMOS Power Amplifiers”, IEEE Symp. VLSI Circuits Dig. Technical Papers, pp. 93-94, June 1997.

[15] V. Aparin, G. Brown, L. E. Larson, “Linearization of CMOS LNA’s via Optimum Gate Biasing”, IEEE International Circuit System Symp., Vol. 4, pp.

748-751, May 2004.

[16] V. Aparin, L. E. Larson, “Modified Derivative Superposition Method for Linearizing FET Low-Noise Amplifier”, IEEE Transactions on Microwave theory and Techniques, Vol. 53, No. 2, pp. 571-581, Feb 2005.

[17] J. Goo, H. Ahn, D. J. Ladwig, Z. Yu, T. H. Lee, R.W. Dutton, “A Noise Optimization Technique for Integrated Low-Noise Amplifiers”, IEEE JSSC, Vol.

37, No. 8, pp. 994-1002, Aug 2002.

[18] T. W. Kim, B. Kim, K. Lee, “High Linearity Receiver Front-End Adopting MOSFET Transconductance Linearization by Multiple Gated Transistors”, IEEE JSSC, Vol. 39, No. 1, pp. 223-230, Jan 2004.

[19] UMC corporation, UMC 0.13um L130E RFCMOS Spice Model Document, UMC corporation, Nov. 2005.

[20] C. D. Hung, W. S. Wuen, M. F. Chou, K. A. Wen, “A Unified Behavior Model of Low Noise Amplifier for System-Level Simulation”, Digest of The 9th European Conference on Wireless Technology, pp.139-142, Oct 2006.

Vita

姓名 : 梁書旗 性別 : 男

出生地 : 台北縣

生日 : 民國六十七年十月三日

地址 : 台北縣蘆洲市重陽街 112 號七樓

學歷 : 國立交通大學電子工程研究所碩士班 2005/09~2007/06

國立清華大學電機工程學系 1997/09~2002/06 台北市立建國高級中學 1994/09~1997/06 論文題目 : Design of Dual-gain Mode CMOS LNA for WiMAX Applications

應用於 WiMAX 之雙增益互補金氧半低雜訊放大器設計