Dual-Band PLL

The function trend of modern communication transceivers moves from single-standard single-band [9] to multi-standard multi-band [10]. Developing a dual-band reconfigurable transceiver to cover multiple standards is not only helpful for the data-rate enhancement but also for the cost down significantly. In a dual-band reconfigurable transceiver, the dual-band PLL also plays an important role in the system. Figures 1.4 (a) and (b) show the block diagrams of dual-band PLLs using a dual-band VCO and a dual-mode frequency divider, respectively. In these PLLs, the most parts of the PLL blocks are re-usable to reduce the chip-area. In comparatively low-frequency (<10 GHz) dual-band PLLs, using dual-band VCO is a reasonable architecture, as shown in Figures 1.4 (a). In such frequency range, the dual-band VCO usually has good performance and its chip-area is much smaller than using two separate VCOs to the dual-band operation. And the first-stage divider implemented by a wideband digital divider which can easily cover the frequency range of dual-band VCO. When the operation frequency increases (>10 GHz), the dual-band VCO will suffer from many parasitic effects due to dual-band generation such that the design work becomes difficult. And the input locking range of first-stage ILFD is almost impossible to cover the whole dual-band frequencies. In this condition, the dual-band frequencies are generated by separately VCOs, and the first-stage divider can be implemented by dual-mode ILFD [11] to reduce the chip area in divider chain. These architectures for different operation frequencies can exactly reduce the chip area of PLL with high performance. However, keeping dual-band operation correctly is important in the dual-band PLL designs. So, the switch mechanism in VCO must be correctly controlled with robustness and the locking range in dual-mode ILFD needs to be enlarged significantly.

6

1.2 Dissertation Organization

In the dissertation, various component circuits for microwave and millimeter PLLs have been implemented including dual-band quadrature VCOs, high-division-ratio divide-by-three and divide-by-five ILFDs, and integrations of VCO and frequency tripler for wideband application and low-power application. All the component circuits are

LPF CP

PFD

Dual -Band

f

_ref1

,f

_ref2 VCO

f

01

,f

02

Digital Dividers (÷M) (CML and/or TSPC)

f

_div1

,f

_div2

Re-Usable Part

(a)

Dual-Mode ILFD (÷M,÷N) LPF

CP

PFD VCO

f

_ref

f

_div ^MUX

Mf

₀

Nf

₀

f

₀

Mf

₀

,Nf

₀

Digital Dividers (CML and/or TSPC)

Re-Usable Part

(b)

Figures 1.4 Block diagrams of dual-band PLLs by (a) using a dual-band VCO or (b) using a dual-mode frequency divider.

7

fabricated in CMOS 0.18µm technology.

In chapter 2, at first, the switchable inductor especially in parasitic effects in merged layout is introduced. And we proposed a new inner-diamond-structure (IDS) layout in a merged switchable inductor to ease parasitic effects. The design considerations in quadrature VCO circuit are also presented. Finally the measurement results are presented for verifying our design and discussions are made.

Chapter 3 introduces the designs of high-division-ratio divide-by-three and divide-by-five ILFDs. In order to accomplish the operation of frequency division and obtain better input locking range, the shunt-peaking with current-bleeding technique and a series LC band-pass filter are incorporated in the designs of divide-by-three and divide-by-five ILFDs, respectively. The design details for respective ILFDs will be revealed. Finally the experimental results will be shown and discussed.

In chapter 4, an integration of VCO and frequency tripler is designed for wideband operation and low-power consumption applications. For wideband application, the way how to increase the tuning range is discussed. For low-power application, besides the power consumption consideration using current-reused topology, we also focus on noise the optimization since the current-reused topology will induce additional noise issue.

Finally the measurement results will be given.

In chapter 5, we propose a dual-mode ILFD with new circuit topology to increase the input locking range. The wide input locking range must be obtained to increase the robustness in dual-mode operation. The input locking range is analyzed and design consideration for this ILFD is also described. Finally, the experimental results are shown.

In the final chapter, the conclusions of these works are made and future work is presented.

8

Chapter 2

Dual-Band Quadrature VCO Using IDS Switchable Inductor

2.1 Introduction

Recently, the function trend of modern communication transceivers moves from single-standard single-band [9] to multi-standard multi-band [10]. Developing a dual-band reconfigurable transceiver to cover multiple standards is not only helpful for the data-rate enhancement but also for the cost down significantly. But the circuit design difficulty of reconfigurable dual-band transceivers is usually higher than that of single-band ones.

Though transformer-based dual-band oscillator designs, like differential VCO in [12] and QVCOs in [13]-[14], have achieved wide tuning range and low phase noise, the band switching highly depend on magnetic coupling coefficient of the transformers. The precise device characterization of on-chip transformers become a critical need for the band switching design in the transformer-based oscillators.

The way using a switched LC-resonator to provide a dual-band operation, which are switched by MOS transistors, can be implemented with switched capacitor [15] and/or

9

switched inductor [16-18]. In such switched LC-resonators, switched inductor exhibits the benefits in the capability of making a trade-off between the gain and the power consumption by an optimal composition of inductance and capacitance [17]. But dual-band VCOs using switched inductors usually occupy relatively large chip area [16],[18] than those ones using switched capacitors; such condition will become critical in QVCOs since the QVCOs usually need a double number of inductors than differential or single-end VCOs. For chip area consideration, switchable inductors using merged layout structure [17]

are proposed for saving the area significantly, but the quality factor degradation will worsen the phase noise of an oscillator when the switch is turned on.

Switched-inductor-based dual-band QVCOs like that reported in [18] would have low circuit complexity, but the design trade-off between the chip area and quality factor degradation makes the overall circuit optimization be limited.

In this work, a differential inner-diamond-structure (IDS) switchable inductor, first introduced in [19], is embedded to a dual-band QVCO design. The proposed IDS switchable inductor can mitigate the quality factor degradation caused by the merged layout. Therefore, the QVCO can be optimized in phase noise and chip area simultaneously to achieve better FOM with low circuit complexity.

2.2 Switchable Inductor Design Consideration

Figure 2.1 shows the schematic of a switchable inductor. Generally, the oscillation frequency of an LC-tuned oscillator can be expressed as

TOTAL TOTAL

OSC 2À L C

f = 1 (Eq. 2-1)

10

where C_TOTAL is the sum of variable capacitance (C_VAR) and parasitic capacitance (CPARA); LTOTAL is the inductance of switchable inductor determined by LOUT and LIN. When the switch is turned off (at the OFF state), the total inductance (L_TOTAL) is equal to LIN+LOUT. When the switch is turned on (at the ON state), the inductor LIN will be excluded and the total inductance (L_TOTAL) becomes L_OUT only. The traditional differential switchable inductor is implemented by four individual inductors (LIN1, LIN2, LOUT1 and L_OUT2) [16] or two differential inductors (L_IN and L_OUT) [18]. In such a way, the switchable inductor will consume a large chip area. In order to shrink the chip area of a switchable inductor like that reported in [17], the L_IN can be folded into the hollow region of L_OUT to merge the individual inductors together.

The traditional differential switchable inductor using merged layout and its diagram with dimension parameters are shown in Figure 2.2. Although the merged layout structure can save the chip area significantly, it is reported that the traditional merged switchable inductor suffers from several parasitic effects [17] since the metal lines of inner and outer coils are layouted in parallel. Besides the skin effect which results in an increase of total

Port1 Port2

L

_IN

L

OUT

V

_sw

L

OUT1

L

OUT2

L

IN2

L

_IN1

Figure 2.1 Schematic of differential switchable inductor.

11

resistance, there are some other parasitic effects which also increase the inductor’s effective resistance. At the ON state, the eddy current induced in the inner inductor coil will cancel a part of the magnetic flux generated by the outer inductor. At the OFF state, proximity effect will be the main reason of metal loss in this structure. On the other hand, the substrate loss has to be considered at both the OFF and ON states [19]. These parasitic effects all will induce additional losses to degrade the quality factor of switchable inductors.

Hence, how to reduce these parasitic effects and minimize the losses under the same chip area is an important issue for switchable inductor design.

2.3 Parasitic Effects in Merged Layout

In order to characterize and analyze the parasitic effects in the merged layout, a differential switchable inductor shown in Figure 2.2 has been fabricated in a 0.18-µm CMOS process. Figure 2.3 presents the equivalent lumped-circuit model for fitting the

Port1 Port2

V

SW

I.D.O

MOS Switch

L

_IN

L

OUT

I.D.I

Metal Width

Metal Width, Wm =15 µm I.D.O=330 µm

I.D.I=170 µm

W/L of MOS

=512/0.18 µm V_SW

S1=a-b b a

I.D.O I.D.I

Wm

Figure 2.2 Photograph and its diagram with device dimensions of the differential switchable inductor in traditional merged layout.

12

measured quality factor and inductance of the merged differential switchable inductor. In this model, COX, CSUB and RSUB together account for the substrate loss effect; ROUT and RIN

are the resistances of the outer and inner inductors, respectively. R_OUT and R_IN are composed of the resistance of coil and the parasitic resistance caused by the skin effect.

(L₁+L_OUT) and L_IN are the inductances of the outer and inner inductors respectively. C_P is the parasitic capacitance between the inner and outer inductors; K is the coupling coefficient between the inner and outer inductors. C_PIN is the parasitic capacitance in the inner inductor; KIN is the self-coupling coefficient in the inner inductor. Besides, KPR, LPR

and R_PR together account for the proximity effect which cause the metal loss at the OFF state. The fitting parameters are given at the bottom of Figure 2.3. The comparisons of inductance and quality factor between the measured and modeling results are shown in Figure 2.4.

For the OFF state only RSUB

L₁ L_OUT L_IN K KIN R_OUT RIN CSUB C_OX C_PIN C_P 0.42 0.32 0.56 0.52 0.19 3 0.5 166 33 200 280 20 Inductor in nH, Resistance in ohm, Capacitance in fF.

K_PR L_PR R_PR 0.52 1.48 11.3

Figure 2.3 Equivalent lumped-circuit model with fitting parameters of traditional merged differential switchable inductor shown in Figure 2.2.

13

2.3.1 Substrate Loss

Figures 2.5 (a) and (b) show the modeling inductance and quality factor for K=0.52 with ±50% variations. It is clear that both the inductance and quality factor are varied with different K. The simplified single-ended parallel model cited from [20], as shown in Figure 2.6, is adopted for characterizing our switchable inductor by fitting varied inductance and quality factor. RP,eff and CP mainly represent the parasitic resistance and capacitance of the substrate. C_S is the overlap capacitance caused by the metal-line underpasses. L_S,eff and RS,eff represent the series inductance and resistance of the switchable inductor after the transformer action. To simplify our analysis, the R_S,eff only takes into account the resistance of coils and the parasitic resistance caused by the skin effect and proximity effect. However,

-4 -2 0 2 4 6

Inductance(nH)

Measured Model

0 2 4 6 8 10

0 2 4 6 8

Measured Model

Quality Factor

Frequency (GHz) ON-state OFF-state

OFF-state

ON-state

Figure 2.4 Measured and modeling results for the inductances and quality factors of the traditional merged switchable inductor shown in Figure 2.2.

14

RS,eff is dominated by the resistance of the primary coils. Therefore, CS and RS,eff are taken to be independent of K in our analysis.

From such a simplified model, the quality factor can be expressed as



Figures 2.5 Evaluated (a) inductance and (b) quality factor as K = 0.52 varied with

±50%.

Figure 2.6 Simplified single-ended parallel model.

15

Among the parameters shown in the second term, R_P,eff directly dominates the quality factor performance if RP,eff > (Q²．R_S,eff). Increasing the RP,eff will improve the quality factor directly [20] since R_P,eff represents the loss caused by the substrate. Therefore, the extracted RP,eff from the fitting results of inductance and quality factor can interprets well the concrete characteristic of substrate losses with relation to different K. Let the constant parameters CS, CP and RS,eff be denoted as a set of {CS, CP, RS,eff}. They are {20 fF, 131 fF, 9.2 ©} at the OFF state and {0 fF, 5 fF, 9.6 ©} at the ON state for our study case in Figure 5(a) and (b). The fitting parameters of LS,eff and RP,eff values related with K are shown in Table 1. It is noted that the quality factor is evaluated at 2.5 GHz for the OFF state and at 7 GHz for the ON state because of the consideration of dual-band oscillator operation. A higher value of K leads to a lower R_P,eff in the single-ended parallel model at both the OFF and ON states. From Table 2.1, it is observed that the dependences of LS,eff on the coupling coefficient K at the OFF and ON states are different. At the OFF state, single-ended inductance LS,eff is derived from the original differential structure, so higher K will lead to higher inductance L_S,eff (e.g., from 3.07 nH to 4.06 nH as K raised from 0.26 to 0.78). On the other hand, at the ON state, the close-looped opposite-directional eddy current will

Table 2.1 Fitting parameters of the equivalent circuit model shown in Figure 2.6.

OFF-state

@2.5 GHz

Fitting Parameters Q Factor (∆Q%) L_S,eff(nH) R_S,eff(©) R_P,eff(©)

K=0.78 4.06 9.2 1407 4.44 (+3%)

K=0.52 3.56 9.2 1580 4.31 (0%)

K=0.26 3.07 9.2 2007 4.09 (-5%)

ON-state

@7GHz

Fitting Parameters Quality Factor(Q) LS,eff(nH) RS,eff(©) RP,eff(©)

K=0.78 1.14 9.6 3600 4.8 (-15%)

K=0.52 1.32 9.6 5800 5.63 (0%)

K=0.26 1.43 9.6 12600 6.22 (+10%)

16

cancel a part of the magnetic flux resulted from the outer inductor. Therefore, a higher value of K will leads to the decrease of LS,eff (e.g., from 1.43 nH to 1.14 nH as K raised from 0.26 to 0.78)

From equation (Eq. 2-2), it is clear that the quality factor also depends on LS,eff as well as the self-resonance factor, besides the substrate loss factor. The self-resonance factor itself is also a function of LS,eff. At the OFF state, the value of inductance LS,eff is inherently greater than that at the ON state below the self-resonance frequency. Therefore, the quality factor at the OFF state is greater than that at the ON state when the operation frequency is of the same. From Table 2.1, it is noted that the quality factor at the OFF state is much insensitive to value of K because the variation of RP,eff is smaller than thatat the ON state.

2.3.2 Metal Loss

Resistance of the coil and parasitic resistance due to the skin effect and proximity effect are the main reasons for the metal loss of an inductor. The losses due to the coil resistance involving the skin effect in the merged and non-merged differential switchable

Inductor Coil

X B Field

Eddy Loops

Excitation Current

Z Y W

Figure 2.7 Proximity effect in a multi-turn inductor [21].

17

inductors are common. But the proximity effects on the merged and non-merged inductors are quite different from each other. In merged layout, the proximity effect between the inner and outer inductors is an important issue at the OFF state. At the ON state, only eddy current is existed the inner part of coil, hence the proximity effect will be concerned at the OFF state only.

In general multi-turn inductor, the proximity effect, as shown in Figure 2.7, is caused by magnetic flux (B field) induced from adjacent coil. Such B field will produce eddy current within coil to subtract the excitation current in the outside of coil; then the current density is gathered in the inside of coil to increase the current crowding effect. In Figure 2.7, according to [21], the induced electric field (E field) for eddy current within coil in point form for the segment of the loop can be expressed as

z Integration of equation 2-3 with respect to the x-axis can produce eddy current density (J_eddy) extracted from E field. The simplified expressions of E field and eddy current density (|Jeddy|) at the edge of coil with width of W are where à is the conductivity of the coil. From equations (Eq. 2-3)-(Eq. 2-5), the mechanism of proximity effect is dominated by coupling and interaction between E field and magnetic flux density (B field) from adjacent coil. It is complexity in merged switchable inductor since it depends on layout structure and the distance between coils of inner and outer inductor.

In order to analyze the proximity effect conveniently in merged switchable inductor, the equivalent model shown in Figure 2.3 includes three parameters KPR, LPR and RPR to

18

account for the increase of resistance due to the proximity effect at the OFF state. Such model is based on a coupled transformer loop [22]. The RL-ladder expression in [22] is simplified to single resistor and inductor in series for reducing the model complexity. The mutual inductance is also transformed by KPR which is the coupling coefficient between inner and outer coils.

Figure 2.8 shows the measured and modeling inductances and quality factors when considering the proximity effect (as K_PR varied with ±50%) at the OFF state. When the value of KPR is increased from 0.52 to 0.78(+50%) at 2.5 GHz, the inductance (or quality factor) is decreased from 4 nH (or 4.34) to 3.4 nH (or 3.3); When the value of K_PR is decreased from 0.52 to 0.26(-50%) at 2.5 GHz, the inductance (or quality factor) is

Modeling (KPR=0.26) Modeling (KPR=0.52) Modeling (KPR=0.78) Measurement in Fig. 2.2

-4 -2 0 2 4 6 8

Inductance(nH)

-2 0 2 4 6

Quality Factor

0 2 4 6 8 10

Frequency (GHz)

Figure 2.8 Measured and modeling results of inductance and quality factor at the OFF state when consider the proximity effect. As KPR = 0.52 varied with ±50%.

19

increased from 4 nH (or 4.34) to 4.4 nH (or 5.2). Therefore, at the OFF state, reducing K_PR to mitigate the proximity effect can reduce the effect resistance and prevent from quality factor and inductance degradations.

2.3.3 Overall Losses at the ON and OFF States

Through the above analysis of substrate and metal losses, the quality factor at the ON state is dominated by coupling coefficient K, and that at OFF state is dominated by the proximity effect coupling coefficient KPR as well as K. At the ON state, the quality factor can be improved by reducing the value of K because of the reduced substrate loss. At the OFF state, the quality factor can be improved by decreasing the metal effective resistance caused by the proximity effect occurred between the inner and outer inductors.

Comprehensively considerations of the overall losses in a switchable inductor design, K and K_PR must be decreased in switchable inductor designs.

2.4 Proposed Inner-Diamond-Structure (IDS) Switchable Inductor

To reduce K and K_PR in a merged switchable inductor, we rotate the inner inductor with 45 degrees to let the layout be in a diamond shape. This is so-called inner-diamond-structure (IDS) switchable inductor. Figure 2.9 shows the photo and its diagram with dimension parameters of the IDS switchable inductor. The testkey is also fabricated in a 0.18-µm CMOS process. As compared with the switchable inductor shown in Figure 2.2, only the inner dimension of inner inductor (I.D.I) is slightly changed from 170µm to 165µm. In an approximate manner, the inductor geometry dimensions for these two structures, including inner dimension of inner inductor (I.D.I), outer dimension of outer inductor (I.D.O) and the width of coil (w), are all assumed to be of the same to each other.

20

The coupling effects in both traditional and IDS switchable inductors will be checked for understanding the advantages of this novel layout structure. The coupling coefficient K in the switchable inductors can be expressed as

OUT IN L L K M

= ⋅ (Eq. 2-6) where LIN and LOUT are the inductances of inner and outer inductors, respectively, and M is

the mutual inductance between L_IN and L_OUT. Since the geometry dimensions of traditional and IDS inductors are of the same, the LIN and LOUT in two structures are of the same, too.

The mutual inductance can be modified from [23] as

( )

¸

Figure 2.9 Photograph and its diagram with device dimensions and of the switchable inductor in IDS layout.

21

and P need to be discussed in the analysis. The factor cos(¸ ) is usually ignored since ¸ =0°

in a normal layout case, but it is an important factor due to the rotated inner inductor. As

in a normal layout case, but it is an important factor due to the rotated inner inductor. As

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