Chapter 3 High-Division-Ratio Injection-Locked Frequency Divider
3.4 M EASUREMENT R ESULTS
3.4.2 Measurement Results of Divide-by-Five ILFD
Our proposed divide-by-five ILFD is fabricated in a 0.18 µm CMOS process. Figure 3.13 presents the microphotograph of this work. The total chip area is 0.87 mm × 0.69 mm, and the core area excluding the pads and buffers is 0.26 mm × 0.52 mm. The measured tuning range of the VCO core ranged from 7.78 to 8.23 GHz as the tuning voltage was varied from 0 V to 1.8 V. The power consumption was 18 mW with 1-V supply voltage in the core circuit. Figure 3.14 shows the measured output spectrums locating at 8 GHz under
Table 3.1 Performance comparisons of our proposed ILFD with other dividers reported in CMOS 0.18-µm technology.
Ref. [32] [4] [28]
This work with bleeding
off on
Operation Range (fL to fH) (GHz)
1.9 (3.3~5.2)
3.1 (15.5~18.6)
1.44 (14.04~15.48)
4.06 (23.31~27.37)
4.32 (23.17~27.49) Max. Locking
Range (GHz) 1.7 1 0.51 0.77 1
Pin(dBm) +4 +3.4 0 +4
Pdiss(mW) 12.96 4.6 9.02 4.28
Chip Area(mm2) 0.23 0.81+ 0.406 0.43
+with an on-chip balun
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locked when the input frequencies are equal to 40 GHz. Figure 3.15 shows the measured wideband output spectrum. The measured second- and fifth- harmonic suppressions are approximately 20 and 37 dBc, respectively, with reference to the fundamental output signal.
The single-ended input signal through an external 180° hybrid coupler generates differential signals for the measurement. Figure 3.16 shows the measured input sensitivity at several control voltages. With -3 dBm of input power, the total operation frequency range was from 39.36 to 42.1 GHz, and the maximum locking range was 735 MHz at a tuning voltage of 0.8 V. Figure 3.17 shows the phase noise performance comparison of the input reference at 40 GHz and the output locked signal at 8 GHz. At a frequency offset of 200 kHz, the phase noises are -109.2 dBc/Hz for the input reference signal and -122.4
Figure 3.13 Chip microphotograph of the proposed divide-by-five ILFD.
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dBc/Hz for the output locked signal. The phase noise difference of 13.3 dB is close to the theoretical value of 14 dB. The measurement results of this work and some other silicon-based high-division-ratio frequency dividers [33]-[35] are summarized in Table 3.2.
Figure 3.14 Measured output spectrum of the locked frequency at input frequency=40 GHz.
Figure 3.15 Measured wideband output spectrum.
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Figure 3.16 Measured input sensitivities for Vtune = 0, 0.4, 0.8, 1.2, 1.4, and 1.8 V.
Input @40 GHz
Ouput @ 8 GHz
-109.1 dBc/Hz
@ 200 kHz offset
-122.4 dBc/Hz
@ 200 kHz offset
Figure 3.17 Measured phase noises of input reference signal (at 40 GHz) and output locked signal (at 8 GHz).
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3.5 Summary
In this chapter, a low-power, wide-locking-range, K-band divide-by-three ILFD and a 40-GHz divide-by-five ILFD have been presented. They are both implemented and fabricated by using a 0.18-µm CMOS process. The divide-by-three ILFD combines the shunt-peaking and current-bleeding topologies to enhance both the locking range and operation range. The measured operation range is 4.32 GHz (from 23.17 to 27.49 GHz) with 4.28 mW DC power consumption. The bleeding source effect on the enhancement of locking range has also been verified experimentally. From the experimental data shown, it is found that a locking range extension of about 260 MHz has been achieved with the bleeding source turning on. In divide-by-five ILFD, by mixing the input signals with the fourth-order harmonic and bypassing the unwanted second harmonic at the common-mode node A of the injection pair, the divide-by-five function could be obtained correctly.
Table 3.2 Performance comparison of silicon-based microwave and millimeter-wave high-division-ratio dividers.
Performance Comparison of Silicon-Based Microwave and Millimeter-Wave High-Division-Ratio Dividers
Ref. Process Division Ratio
Pdc
(mW)
Operation Range (GHz)
Maximum Locking Range
(MHz) [33] 0.18 µm
CMOS 4 7.56 45.9~50.9 450
[34] 0.18 µm
CMOS 4 1.8 41.9~44 200
[35] 0.18 µm
SiGe 4 50 59.8~60.1 350
This work
0.18 µm
CMOS 5 18 39.36~42.1 735
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These works with high-division-ratio, acceptable locking range, small core area, and low injection power requirement exhibit the great potential in the use for the first-stage divider in microwave and millimeter-wave PLLs.
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Chapter 4
Integration of VCO and Frequency Tripler
4.1 Introduction
The demand for wideband or low-power transceivers operated at microwave and millimeter-wave frequencies has increased rapidly with the development of the 60 GHz wireless personal area network (WPAN) [2] and radar systems [3]. The phase-locked loop (PLL) is an important building block in such transceivers due to its power-hungry and bandwidth limitation. Among all building blocks in the PLL, the voltage-controlled oscillator (VCO) and the first-stage frequency divider operated at highest frequency suffer from serious high frequency loss. Therefore, design of VCO and the first-stage frequency divider becomes challengeable especially for low-power and wideband PLL at microwave and millimeter-wave regime.
For wideband PLL application, designing a wideband varactor-tuned VCO will suffer from poor phase noise performance, since the quality factor of the LC-tank directly dominates the phase noise. And the MOS varactors at the microwave and millimeter-wave
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regime usually have poor quality factors in a lossy CMOS process. The phase noise degradation will also become more serious when the bandwidth of VCO increases since VCOs need larger varactors to widen the tuning range. On the other hand, a high-speed first-stage divider having a wider operation range than a VCO ensures that the PLL locks successfully. ILFDs [5] have been widely proposed for the first-stage divider design in microwave and millimeter-wave PLLs. However, in comparison with the digital divider, the relatively narrower locking range of ILFD is not suitable to cover the wide bandwidth of VCO.
For low-power PLL application, reducing the power consumption of power-hungry components of PLL is an efficient way to reduce the overall power consumption of PLL.
As the operation frequency of the PLL increases, the VCO and the first-stage divider consume the greatest part (> 80%) of power dissipation [36]-[37]. So optimally designing the VCO and the first-stage divider can directly lower the overall power consumption of PLL. However, the VCO operated in microwave and millimeter wave usually consumes a lot of DC power to compensate the serious high frequency loss. And the input locking range of ILFD usually depends on the output power of VCO. The wider the locking range, the higher is the injection power required. Therefore, the VCO will require more power consumption to deliver greater output power to the ILFD. In addition, the power consumption of ILFD is naturally higher than low-frequency digital divider.
Thus, the traditional PLL with a direct high-frequency VCO may not be the most realizable architecture to achieve the features of wideband and low-power consumption. It can be replaced by one with a low-frequency VCO and a frequency multiplier [8]. A lower-frequency VCO can be optimally designed with better phase noise, wider bandwidth and lower power consumption because of the availability of high-quality-factor varactors.
The integration of a low-frequency VCO and a frequency multiplier to achieve the desired
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mm-wave source had been widely adopted for PLL applications [38]-[41]. A non-linear differential amplifier has been used as a frequency tripler in [38]; however, it suffers from high power consumption and poor sub-harmonic rejection. Quadrature VCO (QVCO) with frequency doubler using pinchoff clipping has been proposed in [39], but QVCO usually consumes more chip area and DC power. A Gilbert cell mixer has been used as frequency doubler [40], but it has many input ports directly connected to the VCO output nodes. The mixer will cause overloading of capacitive parasitics that degrades the frequency tuning range directly. In this chapter, we present two integrations of VCO and frequency tripler for wideband and low-power PLL applications.
4.2 Consideration of PLL Architecture
Figures 4.1(a) and (b) illustrate the architectures of a traditional PLL and a PLL using a frequency tripler at 24 GHz, respectively. In Figures 4.1(a), the VCO and the first-stage divider both operate at 24 GHz. The VCOs operated at K-band [42]-[43] can achieve good performance when the FTR of VCO is less than 10 %. Unfortunately, when a VCO has a wider tuning range by using large-value varactors, the phase noise performance will be limited by low quality factor of the varactors. On the other hand, the K-band first-stage divider is usually implemented by a current-mode logic (CML) frequency divider [36]-[37]
or an injection-locked frequency divider (ILFD) [44]-[45]. A high-speed CML divider has a wide bandwidth while it needs a higher power dissipation. In contrast, ILFD usually has a lower power dissipation but its operation locking range is relatively narrower. In order to achieve a wider locking range of ILFD, higher injection power from the VCO to the ILFD must be required. Therefore, enlarging the VCO output amplitude or inserting an extra buffer amplifier between the VCO and the ILFD is necessary. The total power consumption
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is difficult to be reduced in microwave and millimeter-wave PLLs [46].
An integration of VCO and ILFD has been implemented for observing its performance limitation. Figure 4.2 shows the microphotograph of the integration of the design VCO and frequency divider. The measured tuning range of the VCO is shown in Figure 4.3. Such integration operating at 14.78 GHz is optimally designed for low-power consumption. And its measurement results are summarized in the Table 4.1. According measurement results, the power consumption of 7.3mW is acceptable due to well design to lower the power consumption. But when the operation increases to higher frequency such as 24 GHz, 60 GHz, and 70 GHz, the power consumption must be increased to more than 10mW. Therefore, the power consumption in VCO and the first-stage divider is exactly limited in traditional architecture. Besides, the locking range of ILFD cannot cover the tuning range of VCO completely. For PLL application, the ILFD also need to be controlled to meet the VCO frequency. It also indicates that narrower input locking range of ILFD
ILFD or CML
Figures 4.1 Possible architectures of a 24 GHz PLL. (a) a traditional PLL and (b) a PLL using a frequency tripler.
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will significantly limit the flexibility of PLL.
Figure 4.2 Microphotograph of the integrated VCO and ILFD.
-0.2 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 13.8
14.0 14.2 14.4 14.6 14.8
F req. (G H z)
Vtune1(V)
Mea.
Figure 4.3 Measured tuning range of the VCO.
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The architecture replacement shown in Figures 4.1(b) is very attractive for microwave and millimeter-wave PLL applications. It is clear that the VCO and the first-stage divider operate at just one-third of the target 24 GHz as compared with that shown in Figures 4.1 (a). In general, MOS varactors can have a wider tuning capability and a better quality factor when they are operating at comparatively low frequencies. The trade-off between the tuning range and phase noise of a VCO at low mm-wave frequency range will become easier than that are operated at high mm-wave frequency range. Besides, the first-stage divider can be implemented by the CML topology with low power consumption and wide bandwidth. In addition, the adoption of a mixer-based frequency tripler is suitable for the mm-wave PLL design, since the close-in phase noise of the tripler output will follow that of the VCO by an increase of 9.5 dB. Such architecture naturally has capabilities of wideband and low-power. Extending the tuning range of VCO, the wideband operation frequency can be directly obtained in output of frequency tripler. For wideband application of PLL, such integration evidently makes the PLL design flexible. For low-power consumption of PLL, the current-reused topology can be adopted for further saving the total power consumption of PLL.
Table 4.1 Summary of the measured performances of the integration of VCO and ILFD.
Items Measurement Data
Operation Frequency 14.78 GHz Total Power Consumption 7.3 mW Power Consumption of VCO 3.1 mW Tuning Range of VCO 900 MHz Phase Noise@ 1 MHz -110(dBc/Hz) Power Consumption of ILFD 4.2 mW Input Locking Range of ILFD
(at Vtune2 = 0.7 V) 400 MHz
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4.3 Fundamental Theory of Integration of VCO and Frequency Tripler
Figure 4.4 shows the block diagram of the integration of VCO and frequency tripler.
In general, the second harmonic of the VCO output frequency can be easily obtained at the common node of the cross-coupled pair. By mixing the differential fundamental signals (f0+ and f0-) with the second harmonic (2f0), two frequency terms (2f0 ± f0) can be produced at the output nodes of an inductive-loaded differential mixer. The inductor load as well as the parasitic capacitance of the mixer acts as a band-pass filter (BPF) that peaks the frequency of 3fo and filters out the fundamental frequency (f0). By doing so, it accomplishes the desired frequency trebling. In the next session, we will explain this mechanism in detail.
The large voltage swings VVCO+ and VVCO− at the VCO differential outputs. These voltage swings at the common node can be modeled by
]
Figure 4.4 Block diagram of integration of VCO and frequency tripler.
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where Vn is the voltage coefficient of n-th order harmonic, É is the output frequency in o radius, and let us take into account the harmonic terms up to the fourth order.
At the common node of the VCO cross-coupled pair, the common-mode AC current iCM can be modeled as
where gCM is the common-mode transconductance of the VCO cross-coupled pair. The AC voltage VCM(= iCM⋅ZCM) at the common node then can be further expressed as
where ZCM is the node impedance at the common node, gCM,2 is the transconductance for the second-order harmonic, and gCM,4 is the transconductance for the fourth-order harmonic, by taking into account the frequency response of ZCM and the non-linear behavior of the VCO cross-coupled pair.
As shown in Figure 4.2, the inductor LSP as well as the capacitors in the node VCM
will form an LC resonator. Let the resonator be resonated at 2É , the node impedance Zo CM
will be peaked at ω=2É and be much greater than that at ω=4o É . Therefore, it can be o
deduced from (Eq. 4-3) that the first term at the right hand side will be dominated.
It is noted that the large voltage swings VVCO+ and VVCO− are also fed into the mixer core. Due to the switching operation of the mixer core, the resulted non-linear voltage swings VMIX+ and VMIX− can be also modeled by the following expressions similar to (Eq.
where Vmix,n is the voltage coefficient of n-th order harmonic.
Taking into account the frequency mixing of the dominate terms from (Eq. 4-3) and (Eq. 4-4), the resulted differential output voltages V and tri+ V of the mixer in Figure 4.2 tri− can be expressed as
t)
where Av,mix is the voltage conversion gain of the mixer and the parameter Vmix can be expressed as The voltage conversion gain Av,mix can be modeled as
L output load. The output load of the mixer is a band-pass filter (BPF). From (Eq. 4-3) - (Eq.
4-7), it is clear that the output voltage swings are proportional to the parameters gm,mix, gCM, ZL and ZCM. Besides, it is worth noting that each voltage coefficient in (Eq. 4-6) contributes to the final voltage swings. The inductor LSP helps to peaking ZCM and enhances the voltage swings of V2 and V4. Designing the VCO in a deep voltage-limited region with strong nonlinearity could enhance the amplitude of Vmix, but the phase noise degradation and power consumption are the concerns for the overall circuit optimization.
Therefore, there should be a trade-off among the output power and phase noise.
4.4 Design Consideration for Wideband Application
The circuit schematic of the integration of VCO and frequency tripler for wideband application is shown in Figure 4.3. To widen the operation frequency range and improve the phase noise performance after frequency trebling, the VCO itself needs a wide tuning
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range as well as good phase noise. The capacitance tuning ratio of a VCO can be expressed
where Cvar,max and Cvar,min are the maximum and minimum varactor capacitances, respectively, and Cfix is the fixed parasitic capacitance. It follows from (Eq. 4-8) that the frequency tuning range can be maximized by either increasing the varactor capacitance or decreasing the parasitic capacitance. Nevertheless, a higher varactor capacitance generally results in degradation of the quality factor of the LC-tank. Therefore, in our VCO design, the NMOS-only cross-coupled pair (M1–M2) is adopted for negative resistance generation.
Such an NMOS-only structure introduces less parasitic capacitance as compared to the CMOS structure or the PMOS-only structure. Accumulation-type MOS varactors (Cvar1-Cvar2) are used to provide the appropriate Cvar,max/Cvar,min ratio (401 fF/144 fF) with a good quality factor (e 21) at 8 GHz. The inductor L1 with a value of 1.62 nH and a quality factor of 13.6 at 8 GHz is realized by a three-turn center-tapped octagonal structure. This particular topology requires a lower operation frequency (i.e., 7.3–9 GHz) for achieving an output signal ranging from 22–27 GHz. Therefore, it has a greater possibility of attaining the tuning range specification of the VCO as compared to that of a VCO directly operated around the 24 GHz band. The phase noise can be optimized according to the operation frequency range at around 8 GHz instead of 24 GHz, which provides higher quality factors to the passive components. The common node in this VCO core provides the output voltage V2f, which is peaked by a resonator composed of L2 and the parasitic capacitance connected to the source ends of the cross-coupled pair (M1–M2). A common source buffer is also integrated to drive the 50 Ω instrument load when taking measurements.
A single-balanced mixer is employed as the frequency tripler. As shown in Figure 4.3,
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this mixer includes an RF transconductance stage (M3), an LO switch pair (M4–M5), an output inductor (L3), and a positive feedback load (M6–M7). The positive feedback load is designed for IF switching enhancement. The bias voltages (Vbias1 and Vbias2) for the RF and LO ports, respectively, are carefully selected to determinate the M3 bias current and to ensure proper switching behavior. Instead of using large currents to maximize the trans- conductance of M3, the output power is enhanced by incorporating the positive feedback load (M6–M7). The inductor L3, which has a value of 0.49 nH at 24 GHz, resonates with the total parasitic capacitance (CT) contributed by the switching stage, positive feedback load, and output buffer. This L3-CT resonator acts as a band-pass filter that provides a high load impedance of three times the VCO frequency and filters out other unwanted signals.
Finally, to facilitate measurement, a tapper buffer is also integrated in a two-stage configuration to drive the instrument load.
V
tuneFigure 4.5 Circuit schematic of the integration of VCO and frequency tripler for wideband application.
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4.5 Design Consideration for Low-Power Application
4.5.1 VCO Design
The VCO is shown in the upper part of Figure 4.6. An NMOS-only cross-coupled pair (M1–M2) is used for negative resistance generation to compensate for the loss of the LC tank which is composed of Cvar1-Cvar2, C4-C5, and L1. At the common node (VCM) of the cross-coupled pair, an inductor (LSP) resonates with the AC coupled capacitor (C1) and all the node parasitic capacitance to peak the node impedance at 2ωo. This is the so-called shunt-peaking technique [47].
Due to more current budget in current-reused topology, we can increase the voltage
Vtune
Figure 4.6 Circuit schematic of the current-reused integration of VCO and frequency tripler for low-power application.
65
amplitude of VCO to make it operates more close to the verge of current-limited region. A VCO operates in such region can achieve better phase noise and higher output amplitude, and it also can enhance the output power in frequency tripler.
Figure 4.7 shows the simulated phase noises of the VCO with and without inductive peaking at Vtune =1.6 V. An improvement of phase noise at 1 MHz offset frequency is achieved by 4 dB, and the improvements over the whole FTR are also greater than 2.5 dB.
According to the simulated results, the shunt-peaking technique indeed improves the VCO phase noise performance. Since such technique can help to prevent the LC tank from the loaded quality factor degradation and especially provide a high impedance at 2ωo. And the Lsp and CAC can ease the unwanted noise from the tripler which will affect the VCO performance seriously.
The capacitor CAC can provide an AC-ground path at the node N1. The higher
The capacitor CAC can provide an AC-ground path at the node N1. The higher