S UMMARY

Compared with the transformer-based quadrature VCOs which are operated in dual-band applications, a quadrature VCO using switchable inductors has relatively low circuit complexity. A non-merged switchable inductor will consume larger chip area while a traditional switchable inductor with merged layout will suffer from substrate loss and proximity effect. In this chapter, a merged switchable inductor with the IDS layout has been proposed and analyzed to understand the parasitic effects on the quality factor degradation. In contrast, two switchable inductors with the traditional layout and IDS layout have been fabricated in a 0.18-µm CMOS process and compared with each other.

According to measurement results, the proposed IDS switchable inductor indeed improve the quality factor at both the OFF and ON states.

Two dual-band quadrature VCOs using traditional and IDS switchable inductors, respectively, have also been fabricated and verified in a 0.18-µm CMOS process. All their device components but the switchable inductors are of the same. The dual-band quadrature VCO using the IDS switchable inductor exhibits lower phase noise and consequently better FOM due to the better quality factor of the IDS inductor at either the OFF state or the ON state. Therefore, the features of low complexity, small chip area and better FOM can be achieved simultaneously in the quadrature VCOs using the proposed IDS switchable inductors.

33

Chapter 3

High-Division-Ratio

Injection-Locked Frequency Divider

3.1 Introduction

Frequency dividers play an important role in phase-locked loops (PLLs). As the operation frequency of PLLs increases to the microwave and millimeter-wave levels, frequency dividers especially in early-stage contribute to major part of power dissipation and occupy a large chip area in the overall PLL circuits, and keeping the locking range overlapped at every division stage becomes more and more of a challenge [25]. In such PLLs, for early-stage dividers that operate at a high frequency, injection-locked frequency divider is the most suitable structure due to its capability of high frequency operation.

However, compared to digital frequency dividers, its relatively narrow locking range makes it difficult to guarantee an overlapping locking range between the early-stage dividers. This daunting problem can be solved by using a high-division-ratio divider in the

34

first stage. The direct high-division-ratio division of input signals into a considerably low frequency can improve the robustness and enables the connection to the wideband digital divider in the subsequent stage. The efforts to guarantee an overlapping locking range can then be further reduced and the stages of dividers can be reduced simultaneously. Reducing the stages of early-stage using ILFD divider will lead to significant reduction of power dissipation and chip area.

However, the narrower input locking range of high-division ILFD is still a challengeable issue since an enough wide input-locking range is require to withstand the signal frequency shift caused by process, voltage, and temperature variations. When the operation frequency increases, the input locking range of high-division-ratio ILFD is usually narrower than that of divide-by-two ILFD. In high-division-ratio ILFD, the power level of high-order harmonics is naturally lower due to the serious high-frequency substrate loss in a lossy CMOS process. The input locking range will be reduced when the division-ratio increases. In this chapter, divide-by-three and divide-by-five ILFDs will be designed and implemented. Divide-by-five ILFD usually suffers from serious locking range degradation but the advantage of high-division-ratio is very attractive. In contrast, divide-by-three ILFD suffers from less locking range degradation, but the advantage of high-division-ratio is less obvious. According to PLL system requirement, we can choose either divide-by-three or divide-by-five for the use of first-stage divider, and the narrow locking ranges all can be compensated by design technique or adding varactors to tune free-running frequency of ILFD.

Various kinds of frequency dividers that use the harmonic injection technique to achieve division-by-three operation have been reported for different topologies at K-band or Ku-band regime [4], [26]-[29]. The differential-output divide-by-three ILFD reported in [4] uses a cascode differential input pair, which utilizes a shunt-peaking inductor to

35

enhance the locking range. The ILFDs reported in [26]-[27] have wide input locking range, but they all require a greater chip size due to the use of more than two transformers or inductors. Multi-modulus ILFD [28] inherently suffers from a narrower locking range limited by the weaker injection capability of high-order harmonics. The transformer-feedback ILFD [29] can achieve low power consumption, but on-chip transformer needs more effort to get accuracy device model. On the other hand, the divide-by-five is rare in lossy CMOS process.

In this chapter, we propose a K-band, low power, divide-by-three ILFD that combines the techniques of shunt peaking [4] and current bleeding [30] to achieve wide locking range and a divide-by-five ILFD using LC band-pass filter to bypass the unwanted second harmonic and enhance fourth harmonic. In divide-by-three ILFD, the shunt-peaking technique widens the locking range by greater internal injection power [4]. Due to the implementation of current-bleeding topology in our divide-by-three ILFD, additional transconductance given by the PMOS helps to provide extra injection power which further widens the input locking range. In addition, the cross-coupled pair in the divider mixing core is designed with an optimal size to reduce the parasitic capacitance, and then the tuning range of the mixing core can be enlarged such that the operation range can be improved. In divide-by-five ILFD, by mixing the input signals with the peaked fourth-order harmonic and using LC band-pass filter to bypass the unwanted second harmonic, the divide-by-five function could be obtained correctly.

3.2 Divide-by-Three ILFD Using Shunt-Peaking and Current-Bleeding Techniques

A cascode differential divide-by-three ILFD core was reported in [4] (as shown in

36

Figure 3.1 but excluding the bleeding current sources). The shunt-peaking inductor L2 is introduced not only to resonate with the parasitic capacitances at the third harmonic but also to provide a short-circuit path for the fundamental output component fo. Transistors M3

and M4 convert the differential-injection signal into a differential current (at 3fo) which will mix with the second-order harmonic (at 2fo) produced by the nonlinearity of transistors M1

and M2 to satisfy the condition imposed by fundamental component generation (i.e., 3fo – 2fo = fo). All the other unwanted harmonic terms are filtered out by the tunable band-pass filter, which is composed of L1, CV1, CV2, and the total drain parasitic capacitance of the mixing core.

The current-bleeding technique has been reported in the previous mixer design [30]

and the divide-by-two frequency divider design [31]. In this work, it is the first time that

V

_DD

-Figure 3.1 Schematic of our proposed divide-by-three ILFD.

37

the current-bleeding technique is employed in the design of divide-by-three circuit. The current-bleeding technique allows the DC operation current of the switching stage (i.e., M1

and M2) to be different from that of the transconductance stage (M3 and M4). Therefore, the ILFD design will become more flexible. The optimal design of the transconductance stage will focus on the tradeoff between input-signal gain and noise, whereas that of the switching stage will focus on the enhancement of second harmonic power produced by the nonlinear operation of the switching pair.

The schematic of our proposed circuit is shown in Figure 3.1. This proposed circuit is implemented by adding PMOS transistors M5 (M6) between the supply VDD and node X (Y) to a reported cascode differential divide-by-three ILFD. The input differential signals are injected not only into the transconductance transistors (M3 and M4) but also into the current-bleeding transistors (M5 and M6) so that the injection efficiency can be increased.

By using the current-bleeding technique, the oscillator core (i.e., the divider mixing core) can be operated at a lower current level, which is optimized to sustain free-running oscillation over a wider tuning range. The LC-tank of the oscillator core is composed of L1

(= 2.5 nH with Q = 13.5 at 8.2 GHz) and the varactors CV1 and CV2 (each equals to 81.2 pF at zero bias). The cross-coupled pair M1 and M2 provides negative conductance to compensate the tank loss.

Figure 3.2 shows the simulated results of input sensitivity for three different topologies (with shunt-peaking-only, with current-bleeding-only, and with the combination of shunt- peaking and current-bleeding) at Vtune=1V. From the simulation results, employing both of shunt-peaking and current-bleeding topology exhibits a widest input locking range. Current-bleeding-only topology can save chip area by removing the shunt-peaking inductor, but the high-order harmonics will suffer from serious loss due to the node parasitic capacitances at nodes X and Y. Compared to shunt-peaking-only and

38

current-bleeding-only topologies, our proposed shunt-peaking and current-bleeding topology can provide a higher injection efficiency to extend input locking range evidently.

3.3 Divide-by-Five ILFD

Figure 3.3 shows a block diagram of the proposed divide-by-five circuit. The differential input signals were mixed with the fourth-order harmonic to obtain the two terms 5f0 ± 4f0. A band-pass filter used as a load of free running VCO filters out the higher frequency at 5f0 + 4f0 (9f0), leaving a lower frequency at 5f0 - 4f0 (f0), which equals exactly one-fifth of the input signals under a locked condition. The common mode node A (was shown in Figure 3.4) mainly exists second harmonic and fourth-order harmonic. (The other

Figure 3.2 Simulated input sensitivity for three different topologies at Vtune=1V.

39

and high-even harmonics are weak enough to be neglected.) The second harmonic was an unwanted frequency, and only the fourth-order harmonic was required for the above-mentioned mixing mechanism. Hence, we need to insert a component to bypass second harmonic and peak the fourth-order harmonic. Figure 3.5 shows two approaches to accomplish such requirement. One is the open stub one-fourth wavelength transmission line at second harmonic frequency (2f0); the other is a series-LC band-pass filter resonated at second harmonic frequency (2f0). Open stub one-fourth wavelength transmission line will produce a short circuit to ground at second harmonic frequency for bypassing second harmonic signal and an open circuit at fourth-order harmonic to peak its signal. Band-pass filter resonated at second harmonic can bypass the second harmonic to ground and peak fourth-order harmonics due to the frequency response of filter. Figure 3.6 shows the simulated magnitudes of impedance in these two approaches. According to simulated results, band-pass filter indeed has better characteristic of bypass and peaking. On the other hand, the chip-area consumption of transmission line is too large for on-chip implementation. Hence, we insert a series-LC band-pass filter that resonates at the second harmonic in our proposed divide-by-five ILFD. It can provide high impedance for the fourth-order harmonic, and the unwanted second harmonic can be bypassed to the ground.

Then the function of divide-by-five can be achieved correctly.

Figure 3.4 shows a schematic of the circuit of the proposed divide-by-five frequency divider. The NMOS cross-coupled pair (M1-M2) cancels out the loss of the LC tank (L1, Cvar1-Cvar2) and the parasitic capacitance to make VCO be free running at the target frequency (f0). The differential inputs are injected into the gates of M3-M4. This direct injection-locked topology was incorporated in order to prevent signal loss in the injection path. The middle of the injection pair is the natural common mode node A that can efficiently provide the fourth-order harmonic. Figure 3.7 shows the simulated second- and

40

fourth-order harmonic power levels at the common node A with and without the insertion of a band-pass filter as the tuning voltage (Vtune) was varied from 0 V to 1.8 V. According to the simulation results, this node exists initially a stronger second harmonic than a fourth-order harmonic. By inserting a band-pass filter composed of C1 and L2 that can attenuate the second-order harmonics 20 dB and increase the fourth-order 7.6 dB, respectively. Indeed, the band-pass filter not only bypasses the second harmonic to the ground but also peaks the desired fourth-order harmonic that enhances our proposed mixing mechanism. Finally, two-stage common source buffers were designed to drive a 50-© load.

V _in+

(5f

_o

)

A

M

₄

M

₃

4f _o

f _o -,9f _o

-f _o +,9f _o + V _out+

(f

_o

)

BPF@f

_o

BPF@f

_o

2f0

Trans. Function

4f0

V

in-(5f

_o

)

BPF@2f

_o

V

out-(f

_o

)

Figure 3.3 Block diagram of proposed divide-by-five ILFD.

41

V _dd V _in+ V

in-M ₁

M ₃ M ₄ L ₁

L ₂ C ₁

M ₂

•

V _tune

C

var1

C

_var2

V out-V _out+

CS Buffers CS Buffers

A

Differential Injection

pair

VCO Core

Figure 3.4 Schematic of proposed divide-by-five ILFD.

• •

OPEN

• /4 @ 2f

₀

A A

Figure 3.5 Two approaches to bypass second harmonic and peak the fourth-order harmonic.

42

Figure 3.6 Simulated magnitudes of impedance in these two approaches.

-20 dB

+7.6 dB

0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8

0.00 0.03 0.06 0.09 0.12 0.15 0.18

Magnitude of Node A

V

_tune

2^nd harmonic, w/o BPF 4^th harmonic, w/o BPF 2^nd harmonic, w/ BPF 4^th harmonic, w/ BPF

Figure 3.7 Simulated second- and fourth-order harmonic power levels at the common mode node A.

43

3.4 Measurement Results

3.4.1 Measurement Results of Divide-by-Three ILFD

The proposed divide-by-three ILFD was fabricated using a 0.18-µm RF CMOS process and the chip photograph is shown in the inset of Figure 3.8. The overall chip area, including the dummy metal area and bonding pads, is 0.43 mm². Open-drain NMOS buffers are integrated onto this chip for driving the 50© output loads when performing the measurements. At a supply voltage of 1.2 V, the measured power consumptions (Pdiss) of the core and buffer stages are 4.28 and 8.16 mW, respectively. The measured tuning range under free running is 880 MHz (from 7.78 GHz to 8.66 GHz), while the tuning voltage changes from 0.4 to 2 V.

Figure 3.8 Chip photography of divide-by-three ILFD.

44

The differential injection signals were provided by a signal generator (Agilent E8257D) with an external 180 degree hybrid coupler. The output performances were characterized by a spectrum analyzer (Agilent E4440A). From the wideband spectrum measurement shown in Figure 3.9, the measured second- and third- harmonic suppressions are approximately 38.05 and 37.89 dBc, respectively, with reference to the fundamental output signal.

Figure 3.10 shows the measured sensitivity curves for various tuning voltages Vtune

between 0.4 and 2 V. The total locking range is 4.32 GHz with respect to an injection-power level of +4 dBm. The measured phase-noise performances under free-running and injection-locked conditions are -85 and -139 dBc/Hz, respectively, at an offset of 1 MHz from the center frequency, as shown in Figure 3.11. It is clear that the close-in phase-noise difference between the original and locked signals approaches to the theoretical value of 9.5 dB. Figure 3.12 shows the measured locking range for various

Figure 3.9 Measured wideband output spectrum.

45

tuning voltages when the bleeding current sources are turned on and off. It is obvious that the locking range is extended when the bleeding sources are turned on.

Table 3.1 summarizes the performance comparisons of our proposed ILFD with other dividers [4][28][32] reported in CMOS 0.18-µm technology. In general, when the operation frequency increases, the input locking range is usually degraded because the high-order harmonics become weaker in lossy CMOS technology. Consequently, the design of wider operation range for compensating the degradation of locking range becomes more important when the operation frequency is above 10 GHz. Compared to the circuits reported in [4] and [28], our proposed circuit not only operates in higher frequency without suffering from locking range degradation but also has an extension of operation range. Low power consumption and small chip area can be also achieved in our proposal circuit.

Figure 3.10 Measured input sensitivity for various tuning voltages Vtune between 0.4 to 2 V.

46

Figure 3.11 Measured phase noise performance under free-running and injection-locked conditions. The phase noise of the original input signal is also plotted for comparison.

Figure 3.12 Measured locking range for various tuning voltages when the bleeding sources are turned on and off.

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3.4.2 Measurement Results of Divide-by-Five ILFD

Our proposed divide-by-five ILFD is fabricated in a 0.18 µm CMOS process. Figure 3.13 presents the microphotograph of this work. The total chip area is 0.87 mm × 0.69 mm, and the core area excluding the pads and buffers is 0.26 mm × 0.52 mm. The measured tuning range of the VCO core ranged from 7.78 to 8.23 GHz as the tuning voltage was varied from 0 V to 1.8 V. The power consumption was 18 mW with 1-V supply voltage in the core circuit. Figure 3.14 shows the measured output spectrums locating at 8 GHz under

Table 3.1 Performance comparisons of our proposed ILFD with other dividers reported in CMOS 0.18-µm technology.

Ref. [32] [4] [28]

This work with bleeding

off on

Operation Range (fL to fH) (GHz)

1.9 (3.3~5.2)

3.1 (15.5~18.6)

1.44 (14.04~15.48)

4.06 (23.31~27.37)

4.32 (23.17~27.49) Max. Locking

Range (GHz) 1.7 1 0.51 0.77 1

P_in(dBm) +4 +3.4 0 +4

Pdiss(mW) 12.96 4.6 9.02 4.28

Chip Area(mm²) 0.23 0.81⁺ 0.406 0.43

+with an on-chip balun

48

locked when the input frequencies are equal to 40 GHz. Figure 3.15 shows the measured wideband output spectrum. The measured second- and fifth- harmonic suppressions are approximately 20 and 37 dBc, respectively, with reference to the fundamental output signal.

The single-ended input signal through an external 180° hybrid coupler generates differential signals for the measurement. Figure 3.16 shows the measured input sensitivity at several control voltages. With -3 dBm of input power, the total operation frequency range was from 39.36 to 42.1 GHz, and the maximum locking range was 735 MHz at a tuning voltage of 0.8 V. Figure 3.17 shows the phase noise performance comparison of the input reference at 40 GHz and the output locked signal at 8 GHz. At a frequency offset of 200 kHz, the phase noises are -109.2 dBc/Hz for the input reference signal and -122.4

Figure 3.13 Chip microphotograph of the proposed divide-by-five ILFD.

49

dBc/Hz for the output locked signal. The phase noise difference of 13.3 dB is close to the theoretical value of 14 dB. The measurement results of this work and some other silicon-based high-division-ratio frequency dividers [33]-[35] are summarized in Table 3.2.

Figure 3.14 Measured output spectrum of the locked frequency at input frequency=40 GHz.

Figure 3.15 Measured wideband output spectrum.

50

Figure 3.16 Measured input sensitivities for Vtune = 0, 0.4, 0.8, 1.2, 1.4, and 1.8 V.

Input @40 GHz

Ouput @ 8 GHz

-109.1 dBc/Hz

@ 200 kHz offset

-122.4 dBc/Hz

@ 200 kHz offset

Figure 3.17 Measured phase noises of input reference signal (at 40 GHz) and output locked signal (at 8 GHz).

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3.5 Summary

In this chapter, a low-power, wide-locking-range, K-band divide-by-three ILFD and a 40-GHz divide-by-five ILFD have been presented. They are both implemented and fabricated by using a 0.18-µm CMOS process. The divide-by-three ILFD combines the shunt-peaking and current-bleeding topologies to enhance both the locking range and operation range. The measured operation range is 4.32 GHz (from 23.17 to 27.49 GHz) with 4.28 mW DC power consumption. The bleeding source effect on the enhancement of locking range has also been verified experimentally. From the experimental data shown, it is found that a locking range extension of about 260 MHz has been achieved with the bleeding source turning on. In divide-by-five ILFD, by mixing the input signals with the fourth-order harmonic and bypassing the unwanted second harmonic at the common-mode node A of the injection pair, the divide-by-five function could be obtained correctly.

Table 3.2 Performance comparison of silicon-based microwave and millimeter-wave high-division-ratio dividers.

Performance Comparison of Silicon-Based Microwave and Millimeter-Wave High-Division-Ratio Dividers

Ref. Process Division Ratio

Pdc

(mW)

Operation Range (GHz)

Maximum Locking Range

(MHz) [33] 0.18 µm

CMOS 4 7.56 45.9~50.9 450

[34] 0.18 µm

CMOS 4 1.8 41.9~44 200

[35] 0.18 µm

SiGe 4 50 59.8~60.1 350

This work

0.18 µm

CMOS 5 18 39.36~42.1 735

52

These works with high-division-ratio, acceptable locking range, small core area, and low injection power requirement exhibit the great potential in the use for the first-stage divider in microwave and millimeter-wave PLLs.

53

Chapter 4

Integration of VCO and Frequency Tripler

4.1 Introduction

The demand for wideband or low-power transceivers operated at microwave and millimeter-wave frequencies has increased rapidly with the development of the 60 GHz

The demand for wideband or low-power transceivers operated at microwave and millimeter-wave frequencies has increased rapidly with the development of the 60 GHz

在文檔中 應用於微波與毫米波鎖相迴路之關鍵電路設計 (頁 49-0)