Chapter 4 Integration of VCO and Frequency Tripler
4.6 E XPERIMENTAL R ESULTS
4.6.2 Experimental Results of Integration for Low-Power Application
The chip photograph is shown in Figure 4.13. The total chip area is 0.7 mm × 0.8 mm, including the buffer stage and the probe pads. The core circuit, excluding the buffer stage, consumes 9 mW at a supply voltage of 1.8 V. When conducting the measurement, the VCO and frequency tripler are tested from one of the differential ends and the other end is connected to 50-Ω terminator. Figure 4.14 indicates the measured tuning range of the VCO increases from 7.06 to 8.33 GHz, as the tuning voltage Vtune is raised from 0 V to 2 V. The resulted output frequency range of the frequency tripler is from 21.18 to 24.98 GHz. The tripler output power and sub-harmonic power levels over the whole FTR is shown in Figure 4.15. After calibrating for the cable loss of about 2 dB, the measured output power of the tripler ranges from –3.6 to –16.7 dBm over the whole FTR. The power of the sub-harmonic É0 measured in the whole range is less than 30 dBm. The power of the sub-harmonic 2É0 ranges from -16 to -26 dbm.
The phase noises of both the VCO and frequency tripler are measured by a signal source analyzer (Agilent E5052B+ E5053A). Figure 4.16 shows the measured phase
105 106 107
Frequency Offset from Carrier (Hz) Tripler
Figure 4.12 Measured phase noises of the VCO and the frequency tripler at Vtune=0V.
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noises at Vtune=0 V and Vtune=2 V. At a frequency offset of 1 MHz from the center frequency, the phase noises of the VCO at Vtune=0 V and Vtune=2 V are –113.8 and –109.2 dBc/Hz, respectively; whereas those of the frequency tripler are –105.1 and –98.4 dBc/Hz.
The measured phase noises at 1 MHz offset in VCO and frequency tripler versus tuning voltages are shown in Figure 4.17. The worst phase noise measured is –92 dBc/Hz at 1MHz offset at Vtune=1.2V. Over the whole tuning range, the average phase noise degradation from the VCO to the frequency tripler is around 10 dB close to the theoretical value of 9.5 dB. The worst degradation of 10.8 dB is occurred at Vtune=2V.
Figure 4.13 Die photo of this work. Total chip size is 0.7 mm × 0.8 mm.
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 6
7 8 9 10
21 22 23 24 25
VCO Frequency (GHz)
V
tune(V)
VCO Tripler
Tripler Frequency (GHz)
Figure 4.14 Measured tuning range of the VCO and the frequency tripler.
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0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 -60
-50 -40 -30 -20 -10 0
3•
0-•
03•
0(Tripler Output)
Output Power (dBm )
V
tune(V) 3•
0-2•
0Figure 4.15 Measured output power in the frequency tripler at whole frequency range after the cable loss calibration.
-140 -130 -120 -110 -100 -90 -80 -70 -60
Tripler(Vtune=2V) VCO(Vtune=2V) Tripler(Vtune=0V) VCO(Vtune=0V)
100K 1M 10M
Frequency Offset from Carrier (Hz)
Phase Noise (dBc /Hz )
Figure 4.16 Measured phase noises of the VCO and the frequency tripler at Vtune=0V and Vtune=2V.
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4.6.3 Performance Comparisons with Previous Works
Table 4.2 compares the performance of this work with some previously reported works. Standalone VCOs in [42]–[43] have low power consumption, but the tuning ranges are usually limited. The transconductor-tuned VCO [49] has the widest tuning range but its power consumption is relatively high. In the case of using the integration of a low frequency VCO and a frequency multiplier like in [48] and our work that for wideband application, the tuning range and phase noise can be optimized individually. Since frequency tripler owns higher multiplication ratio than frequency doubler, wider tuning range and better FOMT can be achieved in our work that for wideband application. But the power consumptions in such case are still high since they draw separate operation currents for the VCO and frequency multiplier, individually.
10.8 dB
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 -115
-110 -105 -100 -95 -90
Phase Noise (dBc/Hz) @ 1 MHz offset
Vtune (V)
VCO Tripler
Figure 4.17 Measured phase noises versus tuning voltage Vtune for the VCO and the frequency tripler.
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The performance of our work for low-power application can be optimized in tuning range, phase noise, and power consumption simultaneously. The best FOMT calculated is -187.2 dBc/Hz, as referred to the minimum phase noise performance over the whole frequency tuning range. But our work that for low power application tuning range is narrower than our work that for wideband application because of their different design targets. In overall, wide frequency tuning range is achieved with remarkable FOMT in our works for wideband applications. The low-power consumption with excellent FOMT can be achieved in our work for low-power applications.
Table 4.2 Performance comparisons with the reported works.
Ref. Main
* evaluated by the average PN over the FTR.
** evaluated by the minimum PN over the FTR.
{ }
4.7 Summary
Using a 0.18 µm CMOS process, we have successfully presented two cases of VCO and frequency tripler integrations for wideband and low-power PLL applications. For the wideband application, the tuning range is enlarged by optimally design in low-frequency VCO. For the low-power application, the power consumption is reduced by using the current reuse topology. Both these works exhibit a high potential for the use in wideband and low-power LO signal generation design of 24 GHz PLLs, respectively.
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Chapter 5
Wideband Dual-Mode ILFD Using Regenerative Second-Harmonic
Feedback Technique
5.1 Introduction
In recent years, many standards such as 24/77-GHz short/long range automotive radar systems [3] and 60 GHz wireless personal area network (WPAN) [2] have been developed rapidly at microwave and millimeter-wave frequencies. For higher integration to reduce the cost of transceiver system, the demand of multi-mode multi-band millimeter-wave transceivers [3] has also been increased. In multi-mode multi-band transceiver, the design of dual-band multi-band phase-locked loops (PLLs) [50]-[51] will become challengeable when the operation frequency is increased to millimeter-wave regime. The first-stage divider (i.e., the prescaler) plays an important role to keep the PLL closed-loop function correctly. The LC-based injection-locked frequency divider (ILFD) is the most suitable
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topology for first-stage divider design due to its capability of high operation frequency with low power dissipation. However, compared to digital divider topology, the relatively narrower input locking range and larger chip-area of an ILFD are critical issues in PLL design. Hence, dual-mode [11],[53],[55] or multi-mode ILFDs [51] are usually used in dual-band and multi-band PLLs as shown in Figure 5.1 to reduce the chip-area of the first-stage divider. Besides, in order to compensate the narrower locking range of ILFD, the varactors are usually used in LC-tank of ILFD to extend the operation bandwidth.
In dual-mode and multi-mode ILFDs, the highest division-ratio mode in ILFD also means the highest operation frequency. When the operation frequency increases, the input locking range of high-division-ratio ILFDs is usually narrower than that of divide-by-2 ILFDs since the power level of high-order harmonics is naturally lower due to the serious high-frequency substrate loss in a lossy CMOS process[7]. Therefore, this mode will suffer from serious input locking range degradation. Adding additional varactors in ILFD can compensate the degradation, but it will decrease the maximum operation frequency of ILFD and increase the complexity of dual-PLL. Hence how to design a dual-mode ILFD
Dual-Mode ILFD (÷3,÷1) LPF
CP
PFD VCO
f
reff
divDigital Dividers (÷M)
This work
MUX
f
03f
0f
0f
0,3f
0Divider Chain
Figure 5.1 Block diagram of dual-band PLL using dual-mode ILFD at millimeter-wave.
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with wideband input locking range especially in the highest division-ratio mode is an important issue in dual-band PLL design.
Divide-by-three ILFD is the highest division-ratio mode in our work, so the input locking range in this mode must extended significantly for dual-band PLL applications.
Many divide-by-three ILFDs, which are fabricated in CMOS processes and operated at K-band and Ku-band regime, have been reported [7], [26]-[27], [54]. The cascode differential injection divide-by-three ILFD incorporating with the shunt-peaking technique to enlarge the locking range has been proposed in [7]. But, when the frequency increases, the peaking level will be limited due to serious substrate loss. The divide-by-3 ILFDs using transformer and linear mixer techniques as reported in [26]-[27] can extend the input locking range. But the bonding wires adopted in [26]-[27] are difficult to be integrated and result in extra packaging cost. The direct injection by a floating source injector [54] also can be applied to the divde-by-3 ILFDs to widen the locking range. However, increasing the source impedance of the injector becomes difficult due to the substrate loss when the higher operation frequency increases.
In this chapter, the dual-mode ILFD using regenerative second-harmonic feedback technique is proposed to compensate the input locking range degradation due to high frequency substrate loss and further extend the input locking range in lossy CMOS process.
Hence, this work has high potential to be incorporated in dual-band PLL at millimeter wave frequency.
5.2 Dual-Mode ILFD
5.2.1. ILFD with ILO and Divide-by-Three Modes
Figures 5.2 (a) and (b) illustrate the block diagram of our proposed dual-mode ILFD.
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In divide-by-3 ILFD mode, the second-harmonic (2f0) of the output signal can be obtained from a signal combiner (e.g., the common-mode node of a differential transistor pair) and fed into an amplifier for the amplification of the second-harmonic signal. Then, the regenerated and amplified second-harmonic is fed back to a mixer to mix with differential input signals (3f0) for producing the two frequency terms at 3f0 ± 2f0. By this proposed technique, this mixing methodology can be accomplished with higher conversion gain. By filtering out all the unwanted signals with the band-pass filter, the desired fundamental differential signals at f0 can be obtained at the output nodes.
It is worth to note that the enlarged output signals will again enhance the second harmonics (2f0) in sequence for feedback. When this loop is locked, the output frequency
f
o+
Figures 5.2 Block diagrams of the proposed dual-mode injection-locked circuit at (a) divide-by-three ILFD mode and (b) ILO mode.
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will exactly be equal to one-third of input frequency. In ILO mode, the second harmonic enhancement using proposed technique is the same to divide-by-three ILFD mode. Then, differential input signals at fundamental are injected into input for producing the two frequency terms at f0 ± 2f0. Such two terms are filtered by the same band-pass filter, and the outputs also enhance the second harmonics (2f0) in sequence for feedback again.
Finally, the inputs are equal to output and ILO mode can be accomplished successfully.
5.2.2. ILFD with Divide-by-Three and Divide-by-Five Modes
In addition to ILFD with ILO and divide-by-three modes, the dual-mode ILFD with divide-by-three and divide-by-five modes also can be achieved by a switchable band-pass filter [56]. The block diagrams of dual-mode ILFD operations are shown in Figures 5.3 (a) and (b), respectively. It is clear that the dominant harmonic remained at the common-source node is determined by controlling the resonant frequency of the band-pass filter with the switchable inductor. The input frequency mixes with the dominant harmonic to generate the desired output frequency. Then the functions of divide-by-three and divide-by-five can be accomplished successfully.
Although this dual-mode ILFD owns very high-division ratio in both mode, but the input locking range is still too narrow to be incorporated in dual-band PLL without additional tuning mechanism like adding MOS varactor in ILFD core. By adding MOS varactor indeed can improve the total bandwidth of ILFD, but the complexity of PLL will also increased. It is not suitable with the dual-mode PLL since the dual-mode PLL is a system circuit with high complexity originally. Hence, in this chapter, only the wideband dual-mode ILFD with ILO and divide-by-three modes is discussed and analyzed since its high potential for PLL applications.
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5.3 Input Locking Range of ILFD
The input locking range of a general direct ILFD can be described as [55]
max frequency and output amplitude. And Iq(ϕ)represents the injection current of ILFD. In brief, increasing the inductance (L) and injection current can increase the input locking range in fixed operation frequency(ω ). Such guideline also suits to our ILFD, but the 0 injection current in this work will depend on the conversion gain and second harmonic amplitude in this work. This is because that the injection signal is mixed with enhanced second harmonic to produce injection signal at fundamental frequency to lock the free-running oscillator around fundamental frequency. Hence, the regenerative second
4fo
Mode 1 : Divide-by-3 Mode 2 : Divide-by-5
Switchable
Figures 5.3 Block diagrams of the proposed dual-mode injection-locked circuit at (a)divide-by-three ILFD mode and (b) divide-by-five mode.
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harmonic feedback technique is proposed for wide input locking range.
The circuit schematic of the proposed circuit is shown in Figure 5.4. The large voltage swings VOSC+ ,free and VOSC− ,free at the free-running oscillator differential outputs can be
where Vn is the voltage coefficient of n-th order harmonic, ω is the output frequency in 0 radius, and let us take into account the harmonic terms up to the fourth order.
At the common node of the free-running oscillator cross-coupled pair, the common-mode AC current iCM can be modeled as
)
where gCM is the common-mode transconductance of the free-running oscillator cross-coupled pair. The AC voltage VCM(= iCM⋅ZCM) at the common node then can be
where ZCM is the node impedance at the common node, by taking into account the frequency response of ZCM and the non-linear behavior of the oscillator cross-coupled pair.
As shown in Figure 5.4, the inductor L3 as well as the AC coupled capacitor and parasitic capacitors in the node VCM will form an LC resonator. Let the resonator be resonated at 2ωo, the node impedance ZCM will be peaked at ω=2ωo and be much greater than that at ω=4ωo. Therefore, it can be deduced from (Eq. 5-4) that the first term at the right hand side will be dominated.
It is noted that the large voltage swings VIN+ and VIN−are also fed into the mixer core
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transistors M4 and M5, respectively. Due to the switching operation of the mixer core, the resulted non-linear voltage swings VIN,mix+ and VIN,mix− can be also modeled as
2]
where Vmix,n is the voltage coefficient of n-th order harmonic.
Taking into account the frequency mixing of the dominate terms from (Eq. 5-4) and (Eq. 5-5), the resulted differential injection voltages VINJ+ and VINJ− with high input signal power (around 0 dBm) can be expressed as
)
Figure 5.4 Circuit schematic of the proposed dual-mode ILFD.
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where Av,CG is the voltage conversion gain of the mixer and the parameter VM can be
Assuming that the VIN± signals are approximately square waves, the voltage conversion gain Av,CG can be expressed as
0 impedance of the output load and impedance caused by parasitic capacitance in node A.
The output load of the mixer is a band-pass filter composed of two inductors (L1 and L2) and a capacitor CT, as indicated in Figure 5.4. From (Eq. 5-8), under the condition (gm4+gm5)Zpar>> 1, the voltage conversion gain is simply determined by the product of gm3ZL. From (Eq. 5-2)-(Eq. 5-6), the free-running oscillator differential outputs are firstly combined to generate even-order harmonic signals. By using resonator composed of inductor L3 as well as the AC coupled capacitor and parasitic capacitors, only second harmonic is extracted for frequency mixing. Then the second harmonic is converted to fundamental again in mixing mechanism. Finally, the current gain from free-running oscillator to injection signal can be expressed as
0 According to (Eq. 5-1), increasing the current gain means increasing the injection current, then the input locking range can be enlarged sequentially. However, since the large-signal device model is high complexity, the current gain only can be obtained by circuit simulations when the injection power is equal to 0 dBm. Figure 5.5 shows simulated
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current gain and corresponding locking range at divide-by-three mode with and without the regenerative second-harmonic feedback technique. In the case of the ILFD at divide-by-three mode without the regenerative second-harmonic feedback, we just remove the AC coupled capacitor (C1) to break the second-harmonic feedback loop so that the transconductance stage is out of function consequently. From the simulation results, high current gain and wider locking range can be achieved in ILFD with the regenerative second-harmonic feedback technique. It verifies that the regenerative second-harmonic feedback technique successfully improves the current gain. And the resulting wider input also can be obtained.
The above-mentioned analysis mainly focuses on the input locking range of divide-by-three ILFD. But such analysis also can be applicable for ILO mode. Since the differences in ILO mode are only input signal frequency and unwanted signal at
30 35 40 45
-25 -20 -15 -10 -5 0 5 10
Gain (dB )
Frequency (GHz)
With Without L.R
L.R
L.R=Locking Range 1.1dB
Figure 5.5 Simulated current gain and corresponding locking range at divide-by-three mode with and without the regenerative second-harmonic feedback technique.
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third-harmonic(3f0), and they almost do not change the mixing mechanism in the circuit.
The simulation results in ILO mode are also indicated in Figure 5.6. The results is similar to divide-by-three mode and also can verify the analysis of input locking range.
5.4 Input Locking Range under High Frequency Loss
Since the operation frequency of PLL grows up rapidly, we will observe the condition when our proposed technique is under high frequency loss in this part. But in dual-mode operation, we only focus on the higher division-ratio mode since its high operation frequency and high sensitivity to high frequency loss. In order to model the high frequency loss, the capacitor Cs is connected at node A in Figure 5.4. Figure 5.7 shows the simulated maximum input locking ranges versus different capacitance values of CS with and without the regenerative second-harmonic feedback technique. The input power is equal to 0 dBm.
The higher capacitance value of CS will stand for the more substrate losses. According to
9 12 15 18
-25 -20 -15 -10 -5 0 5 10 15
Gain (dB )
Frequency (GHz)
With Without
L.R=Locking Range L.R
L.R
Figure 5.6 Simulated current gain and corresponding locking range at ILO mode with and without the regenerative second-harmonic feedback technique.
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the simulation results, our proposed divide-by-three ILFD with the regenerative second-harmonic feedback technique indeed have a wider input locking range. The improvement of input locking range is 0.7 GHz in a normal condition (without added CS).
Under a serious loss condition (e.g., CS=20 fF), the improvement is obviously increased to 1.1 GHz. If the ILFD in divide-by-three mode is operating without a regenerative second-harmonic feedback, it will be lack of conversion gain enhancement for the second harmonic at node A. The amplitude of the second harmonic is thus lower than that with regenerative second-harmonic feedback. As the value of CS increases, the amplitude of second harmonic will be degraded more and more. Hence, the input locking range will also be degraded and such degradation will get worse.
This simulation results also can be supported by (Eq. 5-8). In (Eq. 5-8), the parameter of Zpar is almost dominated by the added capacitor CS. Larger value of capacitance will lower the value of Zpar since impedance of capacitor is equal to 1/jÉCS. Hence under serious loss leads to higher modeling capacitance of CS. Then the conversion gain in (Eq.
1 . 1 GHz 0. 7 GHz
0 5 10 15 20
2.7 3.0 3.3 3.6 3.9 4.2 4.5
( With Second Harmonic Feedback
Without Second Harmonic Feedback
0. 6 GHz
0. 2 GHz
Capacitance value of C s fF) Maximum Input Locking Range(GHz)
Figure 5.7 Simulated maximum input locking ranges versus different capacitance values of CS , with and without second-harmonic feedback.
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5-8) will be reduced simultaneously. Fortunately, the conversion gain is not totally dominated on Zpar, enhancing the value of gm3ZL can compensated the degraded Zpar to ease the conversion gain reduction. However, in the ILFD without regenerative second harmonic feedback, the injection signal highly depends on the magnitude of second
5-8) will be reduced simultaneously. Fortunately, the conversion gain is not totally dominated on Zpar, enhancing the value of gm3ZL can compensated the degraded Zpar to ease the conversion gain reduction. However, in the ILFD without regenerative second harmonic feedback, the injection signal highly depends on the magnitude of second