Chapter 5 Wideband Dual-Mode Injection-Locked Frequency Divider
5.5 ILFD C IRCUIT D ESIGN
The circuit schematic of the proposed circuit is shown in Figure 5.4. The free-running oscillator core of the ILFD is composed of the NMOS-only cross-coupled pair (M1–M2), the switching pair (M4–M5), and the LC tank that includes L1, L2, and total parasitic capacitance CT. The cross-coupled pair (M1–M2) produces negative resistance for compensating the loss of the LC tank. The second-harmonic (2f0) can be obtained at the common node of M1 and M2. The inductor L3 is employed to resonate with the AC coupled capacitor C1 and the stray parasitic capacitance at the node B. Then, the second-harmonic can be peaked. The mixing circuit in this work is realized by a single-balanced mixer which includes the RF transconductance stage (M3) and the input switching pair (M4–M5).
The peaked second-harmonic (2f0) is fed into the transconductance stage to accomplish the regeneration of the second-harmonic; the differential input signals at 3f0 are directly
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injected into the switching stage and then the frequency terms of 3f0 ± 2f0 can be generated at the output ports. By utilizing the band-pass filter (i.e., the LC tank of free-running oscillator core), only the signal at f0 can be preserved. The design consideration for ILO mode is similar to that for divide-by-three mode. Finally, for the measurement consideration, two buffers in a self-biased inverter topology are also integrated on chip for driving the 50© output loads.
Since the input signals (VIN±) had been assumed to approximately square waves, the magnitudes of Vmix,1 and Vmix,3 are fixed. If the free-running oscillator designed to operate in a deep voltage-limited region with strong nonlinearity could enhance the amplitudes of V2 and V4, but it will also increase the power consumption. The parameter of gm3 can be enhanced for higher gain with higher power consumption, since such parameter usually depends on DC bias current. Hence, increasing the parameters of ZL and ZCM will effectively increase the gain without additional performance degradation. The inductor L3
helps to peaking ZCM and enhances the voltage swings of V2 and V4. And the LC-tank of free-running oscillator needs to be optimized with high quality factor to increase the input locking range and lower the power consumption [55].
5.6 Measurement Results
The wideband dual-mode ILFD using the regenerative second-harmonic feedback technique was fabricated in a 0.18-µm CMOS process and the chip photograph is shown in Figure 5.9. The chip size of core area is 0.52 mm × 0.43 mm (= 0.22 mm2). The measured DC power consumption (PDC) of the core is 11.9 mW at a supply voltage of 0.9V. The differential injection signals are generated by a signal generator with an external 180°
hybrid coupler. The output performances are measured by a spectrum analyzer (Agilent
91
E4440A). At the ILO mode, the measured output spectrums locating at 10 and 12.8 GHz under locked are shown in Figures 10 (a) and (b), respectively, when the input frequencies are equal to 10 and 12.8 GHz. At the divide-by-three mode, the measured output spectrums locating at 11.3 and 12.56 GHz under locked are shown in Figures 11 (a) and (b), respectively, when the input frequencies are equal to 33.9 and 37.7 GHz. The output power over the whole operation range is around -17 dBm after the cable loss calibration at the input power of 0 dBm.
(a)
Figure 5.9 Chip photography of this work. Total chip size of core is 0.52 mm × 0.43 mm.
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(b)
Figures 5.10 Measured output spectrum of the locked frequency at (a) input frequency=10 GHz and (b) input frequency= 12.8 GHz.
(a)
(b)
Figures 5.11 Measured output spectrum of the locked frequency at (a) input frequency= 33.9 GHz and (b) input frequency= 37.7 GHz.
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Figures 5.12 (a) and (b) show the measured curves of input sensitivity at ILO and divide-by-three modes. This work without any tuning mechanism operates from 10 to 12.8 GHz at ILO mode and from 33.9 to 37.7 GHz at divide-by-three mode. The measured input locking ranges are shown in Figure 5.13 (a) and (b) when the input power varies from minimum to maximum. The maximum input locking ranges are 2.8 and 3.8 GHz at ILO mode and divide-by-three mode, respectively. Figure 5.14 (a) shows that input and output phase noises are all -119 dBc/Hz at ILO mode at an offset frequency of 200 KHz. Figure 5.14 (b) shows that input and output phase noises are -121 and -111.5 dBc/Hz at
(a)
33.5 34.0 34.5 35.0 35.5 36.0 36.5 37.0 37.5 38.0 -30
-27 -24 -21 -18 -15 -12 -9 -6 -3 0 3
Input Power(dBm)
Frequency(GHz)
(b)
Figures 5.12 Measured curves of input sensitivity at (a) ILO mode (b) divide-by-three mode.
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divide-by-three mode, respectively at an offset frequency of 200 KHz. The difference of phase noise is about 0 and 9.5dB for ILO mode and divide-by-three mode, which are close to the theoretical value.
-20 -15 -10 -5 0 5
0.0 0.5 1.0 1.5 2.0 2.5 3.0
Input Locking Range (GHz)
Input Power (dBm)
(a)
-25 -20 -15 -10 -5 0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
Input Locking Range (GHz)
Input Power (dBm)
(b)
Figures 5.13 Measured input locking ranges at (a) ILO mode and (b) divide-by-three mode when the input power varies from minimum to maximum.
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Table 5.1 summarizes the performance comparisons of our proposed dual-mode ILFD with other reported dividers using CMOS 0.18-µm or 0.13-µm processes. Generally, when the operation frequency increases, the input locking range of divide-by-3 ILFD becomes narrower since the high-order harmonic levels inherently become weaker in lossy CMOS
10k 100k 1M
-140 -130 -120 -110
Phase Noise (dBc/Hz)
Offset Frequency (Hz)
Output Phase Noise Input Phase Noise
0 dB
(a)
9.5 dB
10k 100k 1M
-150 -140 -130 -120 -110 -100 -90
Phase Noise (dBc/Hz)
Offset Frequency (Hz)
Output Phase Noise Input Phase Noise
(b)
Figures 5.14 Measured phase noises of input and output at (a) ILO mode and (b) divide-by-three mode.
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process. However, among the previous works listed in Table 5.1, this work in the divide-by-three mode (i.e. high-division-ratio mode) can own the widest input locking range (of 3.8 GHz) at high operation frequency (from 33.9 GHz to 37.7 GHz) by utilizing the regenerative second-harmonic feedback technique, even just being fabricated by a CMOS 0.18 µm process.
Table 5.1 Performance comparisons of our proposed dual-mode ILFD with other reported dividers in CMOS 0.18-µm and 0.13-µm processes.
Ref. CMOS
Tech.
Division Ratio
Operation Range GHz @ Input Pinj
5.7 Summary
A wide input locking range dual-mode ILFD has been successfully presented by using a 0.18-µm RF CMOS process. This work uses the regenerative second-harmonic feedback technique to extend the input locking range. At divide-by-three mode, the measured input locking range is 3.8 GHz (from 33.9 to 37.7 GHz) with a DC power consumption of 11.9 mW. It is worth to note that the proposed regenerative second-harmonic feedback technique also can compensate the input locking range degradation when the ILFD at divide-by-three mode suffers from high frequency substrate losses. With the combined features of a wider input locking range and a higher tolerance to the substrate loss, the proposed regenerative second-harmonic feedback technique is very attractive to the wideband dual-mode ILFD design for the wideband dual-mode millimeter-wave PLLs.
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Chapter 6
Conclusion and Future Work
6.1 Conclusion
This dissertation presents the designs of key component circuits of microwave and millimeter-wave PLLs. The key component circuits include dual-band quadrature VCO, high-division-ratio and dual-mode ILFDs, and integration of VCO and frequency triplers.
They are all implemented and fabricated by using 0.18-µm CMOS process. These circuit designs are introduced in four separate parts from Chapter 2 to Chapter 5 individually.
In the chapter 2, a dual-band quadrature VCO is implemented with low circuit complexity by using switchable inductors. Traditionally, a non-merged switchable inductor will consume larger chip area while a traditional switchable inductor with merged layout will suffer from substrate loss and proximity effect. Through the analysis of switchable inductor, we find these parasitic effects are mainly caused by coupling mechanism between inner and outer coil of switchable inductor. A merged switchable inductor with the IDS layout has been proposed to reduce the coupling mechanism. In contrast, two switchable inductors with the traditional layout and IDS layout have been implemented and compared with each other. According to measurement results, the proposed IDS switchable inductor
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indeed improve the quality factor at both the OFF and ON states. Finally, two dual-band quadrature VCOs using traditional and IDS switchable inductors, respectively, have also been fabricated and verified. The dual-band quadrature VCO using the proposed IDS switchable inductor exhibits lower phase noise and consequently better FOM due to the better quality factor of the IDS inductor at either the OFF state or the ON state.
In the chapter 3, two high-division-ratio ILFDs have been presented. The divide-by-three ILFD combines the shunt-peaking and current-bleeding topologies to enhance both the locking range and operation range. The low power consumption of 4.28 mW is achieved in this ILFD. Besides, the bleeding source effect on the enhancement of locking range has also been verified experimentally. From the experimental data shown, it is found that a locking range extension of about 260 MHz has been achieved with the bleeding source turning on. In the divide-by-five ILFD design, by using a band-pass filter to bypass the unwanted second-harmonic, the input signals is mixed with the peaked fourth-order harmonic. Then the divide-by-five function could be obtained correctly.
In the chapter 4, we have successfully presented two cases of VCO and frequency tripler integrations for wideband and low-power PLL applications. For wideband applications, the tuning range is enlarged by optimally design in low-frequency VCO. Then wide operation frequency range from 22-27 GHz is successfully achieved. For low-power applications, the power consumption is reduced by using the current reuse topology. Then total power consumption of 9 mW has been achieved in this integration.
A wide input locking range dual-mode ILFD has been successfully demonstrated in chapter 5. Using the regenerative second-harmonic feedback technique, the input locking range is indeed extended at both divide-by-three and injection locked oscillator modes. At divide-by-three mode, the measured input locking range is 3.8 GHz (from 33.9 to 37.7 GHz) with a DC power consumption of 11.9 mW. And the proposed regenerative
100
second-harmonic feedback technique can compensate the input locking range degradation when the ILFD at divide-by-three mode suffers from serious frequency substrate losses.
In conclusion, the dual-band quadrature VCO with low complexity, small chip area and better FOM is very suitable for dual-band PLL applications. Divide-by-three and divide-by-five ILFDs with wide-enough locking range, small core area, and low injection power requirement exhibit the great potential for a first-stage divider use in microwave and millimeter-wave PLLs. Two cases of VCO and frequency tripler integrations with remarkable FOMT exhibit a high potential for the use in wideband or low-power PLLs, respectively. Dual-mode ILFD with the features of a wider input locking range and a higher tolerance to the substrate loss is very attractive to the dual-mode ILFD design for the wideband dual-mode millimeter-wave PLLs.
6.2 Future Work
All the circuits in this dissertation have been well designed to achieve high performance. Besides, the PLL system requirements are also properly considered in the designs of these circuits. In the future, these component circuits can be practically incorporated in small-area, dual-band, wideband, and low-power PLLs. Since the circuit function have been proved successfully, high performance PLLs can be done by using our proposed component circuits in 0.18-µm CMOS technology or even advanced ones.
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References
[1] C. Mishra, A. Valdes-Garcia, F. Bahmani, A. Batra, E. Sanchez-Sinencio, and J.
Silva-Matinez, “Frequency planning and synthesizer architectures for multiband OFDM UWB radios,” IEEE Trans. Microw. Theory Tech., vol. 53, no. 12, pp. 3744-3756, Dec.
2005.
[2]Ali M. Niknejad and H. Hashemi (Eds.), mm-Wave Silicon Technology – 60GHz and Beyond, New York: Springer Science+Business Media, LLC, 2007.
[3] V. Jain, F. Tzeng, L. Zhou, and P. Heydari, “A Single-Chip Dual-Band 22–29-GHz/77–81-GHz BiCMOS Transceiver for Automotive Radars,” IEEE J.
Solid-State Circuits, vol.44, no. 12, pp. 3469-3485, Dec. 2009.
[4] H. Wu and L. Zhang, “A 16-to-18GHz 0.18-µm Epi-CMOS divide-by-3 injection-locked frequency divider,” in IEEE Int. Solid-State Circuit Conf. Dig. Tech.
papers, Feb. 2006, pp. 2482-2491.
[5]C.-C. Chen, H.-W. Tsao, and H. Wang, “Design and analysis of CMOS frequency dividers with wide input locking ranges,” IEEE Trans. Microw. Theory Tech., vol. 57, no.
12, pp. 3060-3069, Dec. 2009.
[6]J. Lee and B. Razavi, “A 40-GHz frequency divider in 0.18-µm CMOS technology,”
IEEE J. Solid-State Circuits, vol. 39, no. 4, pp. 594-601, Apr. 2004.
[7] X. P. Yu, H. M. Cheema, R. Mahmoudi, A. v. Roermund, and X. L. Yan, “A 3 mW 54.6 GHz divide-by-3 injection locked frequency divider with resistive harmonic enhancement,” IEEE Microw. Wireless Compon. Lett., Vol. 19, no.9, pp. 575-577, Sep.
2009.
[8]C.-Y. Yang, C.-H. Chang, J.-H. Weng and H.-M. Wu, ”A 0.5/0.8-V 9-GHz frequency synthesizer with doubling generation in 0.13-µm CMOS” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 58, no. 2, pp. 65-69, Feb. 2011.
102
[9] A. Italia, F. Carrara, A. Scuderi, E. Ragonese, C.D. Presti, G. Sapone, and G.
Palmisano, “Radio-frequency front-end for 5 GHz wireless local area network transceivers,” IET Circuits, Devices & Systems, vol. 2, no. 5, pp. 439-450, 2008.
[10] M. Zargari, L. Nathawad, H. Samavati, S. Mehta, A. Kheirkhahi, P. Chen, K. Gong, B.
Vakili-Amini, J. Hwang, M. Chen, M. Terrovitis, B. Kaczynski, S. Limotyrakis, M. Mack, H. Gan, M. Lee, R. Chang, H. Dogan, S. Abdollahi-Alibeik, B. Baytekin, K. Onodera, S.
Mendis, A. Chang, Y. Rajavi, S. Jen, D. Su, and B. Wooley, “A Dual-Band CMOS MIMO Radio SoC for IEEE 802.11n Wireless LAN,” IEEE J. Solid-State Circuits, vol. 43, no. 12, pp. 2882-2895, Dec. 2008.
[11] H.-K. Chen, H.-J. Chen, D.-C. Chang, Y.-Z. Juang, Y.-C. Yang, and S.-S. Lu, “A mm-wave CMOS multimode frequency divider,” in IEEE Int. Solid-State Circuits Tech.
Dig., Feb. 2009, pp. 280-281, 281a.
[12]B. Çatlı and M. M. Hella, “A 1.94 to 2.55 GHz, 3.6 to 4.77 GHz Tunable CMOS VCO Based on Double-Tuned, Double-Driven Coupled Resonators,” IEEE J. Solid-State Circuits, vol. 44, no. 9, pp. 2463-2477, Sep. 2009.
[13]S. Rong and H. C. Luong, "Analysis and Design of Transformer-Based Dual-Band VCO for Software-Defined Radios,” IEEE Trans. on Circuits Syst. I, Reg. Papers, vol. 59, no. 3, pp.449-462, Mar. 2012.
[14] S. Rong and H. C. Luong, "1V 4GHz-and-10GHz Transformer-Based Dual-Band Quadrature VCO in 0.18-µm CMOS," in Proc. IEEE Custom Integr. Circuits Conf. (CICC), 2007, pp. 817-820.
[15] M.A. Do, R.Y. Zhao, K.S. Yeo and J.G. Ma, “New wideband/dualband CMOS LC voltage-controlled oscillator,” IEE Proceedings-Circuits, Devices and Systems, vol.150, no.
5, pp.453- 459, Oct. 2003.
103
[16] S. Yim and K. K. O, “Switched resonators and their applications in a dual-band monolithic CMOS LC-tuned VCO,” IEEE Trans. Microw. Theory Tech., vol. 54, no. 1, pp.
74-81, Jan. 2006.
[17] J.-L. Wang, Y.-R. Tzeng, and T.-H. Huang, “Integrated switchable inductors with symmetric differential layout,” in Proc. Asia-Pacific Microwave Conference (APMC), Dec.
2006, pp.1369-1372.
[18] C.-H. Kim, S.-H. Shin and H.-J. Yoo, ”A Dual Band CMOS Quadrature VCO for Low Power and Low Phase Noise Application,” in Proc. IEEE International Workshop on Radio-Frequency Integration Technology (RFIT), Dec. 2007, pp. 310-313.
[19] P.-K. Tsai, Y.-T. Chen, and T.-H. Huang, “Novel Symmetric-Structure Switchable Differential Inductor Design,” in Proc. Asia-Pacific Microwave Conference, Dec. 2009, pp.
2140-2143.
[20] C. P. Yue and S. S. Wong, “On-Chip Spiral Inductors with Patterned Ground Shields for Si-Based RF ICs,” IEEE J. Solid-State Circuits, vol. 33, pp. 743-752, May 1998.
[21] W. B. Kuhn and N. M. Ibrahim, “Analysis of Current Crowding Effects in Multiturn Spiral Inductors,” IEEE Trans. Microw. Theory Tech., vol. 49, no. 1, pp. 31-38, Jan. 2001.
[22] C. Wang, H. Liao, C. Li, R. Huang, W. Wong, X. Zhang, and Y. Wang, “A Wideband Predictive “Double-À” Equivalent-Circuit Model for On-Chip Spiral Inductors,” IEEE Trans. Electron Devices, vol. 56, no. 4, pp. 609-619, Apr. 2009.
[23] H.-M. Hsu, J. -Z, Chang, and H.-C. Chien, “Coupling Effect of On-Chip Inductor With Variable Metal Width,” IEEE Microw. Wireless Compon. Lett., vol. 17, no. 7, pp.
498-500, Jul. 2007.
[24] P. Andreani, “A 2 GHz, 17% Tuning Range Quadrature CMOS VCO with High Figure-of-Merit and 0.6° Phase Error,” in Proc. European Solid-State Circuits Conference(ESSCIRC), Sep. 2002, pp 815-818.
104
[25] J. Lee, M. Liu, and H. Wang, “A 75-GHz phase-locked loop in 90-nm CMOS technology,” IEEE J. Solid-State Circuits, vol. 43, no. 6, pp. 1414-1426, Jun. 2008.
[26] S.-L. Jang and C.-W. Chang, “A 90 nm CMOS LC-tank Divide-by-3 Injection-Locked Frequency divider with record locking range,” IEEE Microw. Wireless Compon. Lett., vol.
20, no.4, pp. 229-231, Apr. 2010.
[27] S.-L. Jang, Y.-S. Chen, C.-W. Chang, and C.-C. Liu “A Wide-Locking Range ÷3 Injection-Locked Frequency Divider Using Linear Mixer,” IEEE Microw. Wireless Compon. Lett., vol. 20, no.7, pp.390-392, Jul. 2010.
[28] S.-L. Jang, J.-C. Luo, C.-W. Chang, C.-F. Lee, and J.-F. Huang, “LC-tank colpitts injection-locked frequency divider with even and odd modulo,” IEEE Microw. Wireless Compon. Lett., vol. 19, no. 2,pp. 113-115, Feb. 2009
[29] S. Rong and H. C. Luong, “A 1.7 mW 25 GHz transformer-feedback divide-by-3 frequency divider with quadrature outputs,” in Proc. IEEE Asian Solid-State Circuits Conf., Nov. 2007, pp. 328-331.
[30] S.-G. Lee and J.-K. Choi, “Current-reuse Bleeding mixer,” Electron. Lett., vol. 36, no.
8, pp. 696-697, Apr. 2000.
[31] S. Rong, A. W. L. Ng, and H. C. Luong, “0.9mW 7GHz and 1.6mW 60GHz frequency dividers with locking-range enhancement in 0.13µ m CMOS,“ in IEEE Int. Solid-State Circuit Conf. Dig. Tech. papers, Feb. 2009, pp. 96-97.
[32] S.-L. Jang, C.-W. Tai, and C.-F. Lee, “Divide-by-3 injection locked frequency divider implemented with active inductor,” Microw. Opt. Technol. Lett., vol. 50, no. 6, pp.
1682–1685, Jun. 2008.
[33] M.-C. Chaung, J.-J. Kuo, C.-H. Wang, and H. Wang, “A 50-GHz divide-by-4 injection lock frequency divider using matching method,” IEEE Microw. Wireless Compon. Lett., vol.
18, no. 5, pp. 344-346, May 2008
105
[34] T.-N Luo, S.-Y Bai, and Y.-J. E. Chen, “A 44 GHz 0.18µm CMOS Superharmonic Frequency Divider,” in IEEE MTT-S Int. Microw. Symp. Dig., Jun. 2007, pp. 1409-1412.
[35] J.-C. Chien, C.-S. Lin, L.-H. Lu, H. Wang, J. Yeh, C.-Y. Lee, and J. Chern, “A harmonic injection-locked frequency divider in 0.18- µm SiGe BiCMOS,” IEEE Microw.
Wireless Compon. Lett., vol. 16, no. 10, pp. 561-563, Oct. 2006.
[36] Y. Ding and K. K. O, “A 21-GHz 8-modulus prescaler and a 20-GHz phase-locked loop fabricated in 130-nm CMOS,” IEEE J. Solid-State Circuits, vol. 42, no. 6, pp.
1240-1249, Jun. 2007.
[37] A. W. L. Ng, G. C. T. Leung, K.-C. Kwok, L. K. Leung, and H. C. Luong, “A 1-V 24-GHz 17.5-mW Phase-Locked Loop in a 0.18-µm CMOS Process,” IEEE J. Solid-State Circuits, vol. 41, no. 6, pp. 1236-1244, Jun. 2006.
[38] M. Danesh, F. Gruson, P. Abele, and H. Schumacher, "Differential VCO and frequency tripler using SiGe HBTs for the 24 GHz ISM band," in IEEE RFIC Symp. Dig., Jun. 2003, pp. 277-280.
[39] S. Ko, J.-G. Kim, T. Song, E. Yoon, and S. Hong, “K- and Q-bands CMOS frequency sources with X-Band quadrature VCO,” IEEE Trans. Microw. Theory Tech., vol. 53, no. 9, pp. 2789-2800, Sep. 2005.
[40] G. Bu, A. R. Tavakoli, and K. Entesari, “A 24 GHz Indirect VCO in 0.18 µm CMOS Technology” in Proc. of Microwave Integrated Circuits Conference, Oct. 2008, pp. 71-74.
[41] G. Huang and V. Fusco, “A 94 GHz Wide Tuning Range SiGe Bipolar VCO Using a Self-Mixing Technique,” IEEE Microw. Wireless Compon. Lett., vol. 21, no.2, pp. 86-88, Feb. 2011.
[42] J. Yang, C.-Y. Kim, D.-W. Kim and S. Hong, “Design of a 24-GHz CMOS VCO with an asymmetric-width transformer,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 57, no. 3, pp. 173-177, Mar. 2010.
106
[43] C.-C. Li, T.-P. Wang, C.-C. Kuo, M.-C. Chuang, and H. Wang, “A 21 GHz complementary transformer-coupled CMOS VCO,” IEEE Microw. Wireless Compon. Lett., vol. 18, no. 4, pp. 278-280, Apr. 2008.
[44] H.-Y. Lin, S. S. H. Hsu, C.-Y Chan, J.-D. Jin, and Y.-S Lin, “A Wide Locking-Range Frequency Divider for LMDS Applications,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol.
54, no. 9, pp. 750-754, Sep. 2007.
[45] Y.-H. Chen, H.-H Hsieh, and L.-H Lu, “A 24-GHz receiver frontend with an LO signal generator in 0.18-µm,” IEEE Trans. Microw. Theory Tech., vol. 56, no. 5, pp. 1043-1051, May 2008.
[46] B. Catli and M. M. Hella, “Triple-push operation for combined oscillation/division functional in millimeter-wave frequency synthesizers,” IEEE J. Solid-State Circuits, vol.45, no. 8, pp. 1575-1589, Aug. 2010.
[47] E. Hegazi, H. Sjöland and A. A. Abidi, “A Filtering Technique to lower LC oscillator phase noise,” IEEE J. Solid-State Circuits, vol.36, no. 12, pp. 1921-1930, Dec.
2001.
[48] S. Ko, J. -G. Kim, T. Song, E. Yoon, and S. Hong, “K- and Q-bands CMOS frequency sources with X-Band quadrature VCO,” IEEE Trans. Microw. Theory Tech., vol. 53, no. 9, pp. 2789-2800, Sep. 2005.
[49] K. Kwok and J. R. Long, “A 23-to-29 GHz transconductor-tuned VCO MMIC in 0.13 µm CMOS,” IEEE J. Solid-State Circuits, vol.42, no. 12, pp. 2878-2886, Dec. 2007.
[50] V. Jain, B. Javid, and P. Heydari,"A BiCMOS Dual-Band Millimeter-Wave Frequency Synthesizer for Automotive Radars," IEEE J. Solid-State Circuits, vol.44, no. 8, pp.
2100-2113, Aug. 2009.
107
[51] H.-K. Chen, T. Wang, and S.-S. Lu, “A Millimeter-Wave CMOS Triple-Band Phase-Locked Loop With A Multimode LC-Based ILFD,” IEEE Trans. Microw. Theory Tech., vol. 59, no. 5, pp. 1327-1338, May 2011.
[52] T.-N. Luo, S.-Y. Bai, and Y.-J. E. Chen, “A 60-GHz 0.13-µm CMOS divide-by-three frequency divider,” IEEE Trans. Microw. Theory Tech., vol. 56, no. 11, pp. 2409-2415, Nov.
2008
[53] S.-L. Jang, R.-K. Yang, C.-W. Chang, and M.-H. Juang, “Multi-Modulus LC Injeciotn-Locked Frequency Dividers Using Single-Ended Injection,” IEEE Microw.
Wireless Compon. Lett., vol. 19, no. 5, May. 2009.
[54] Y.-T. Chen, M.-W. Li, H.-C. Kuo, T.-H. Huang, and H.-R. Chuang, “Low-voltage K-band divide-by-3 injection-locked frequency divider with floating-source differential injector,” IEEE Trans. Microw. Theory Tech., vol. 60, no. 1, pp. 60-67, Jan. 2012.
[55] C.-Y. Wu and C.-Y. Yu, “Design and Analysis of a Millimeter-Wave Direct
[55] C.-Y. Wu and C.-Y. Yu, “Design and Analysis of a Millimeter-Wave Direct