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Chapter 4 RF MOSFET Intrinsic I-V and C-V Model Calibration

4.3 Intrinsic C-V Model Development

In this section, intrinsic gate capacitance model of multi-finger RF MOSFET is presented.

For submicron MOSFET, the thinner oxide thickness is necessary which can reduce SCE (short channel effect), gate swing, but suffer the penalty of gate leakage and gate capacitances.

Since the details are not our focus. The physical oxide thickness of RF013G NMOS technology is 2.8nm. For this thin oxide thickness, the BSIM3 capacitance model flag capMod=3 was set as default model to consider the finite charge thickness determined by quantum effect, which becomes more important for thinner Tox CMOS technologies.

Capacitances in MOSFET is generally divided into three parts, intrinsic, extrinsic, and extrinsic parasitic. In Bsim3v3 model, intrinsic and extrinsic capacitances model were been

included, but extrinsic parasitic capacitance neither. We will explain this later. The intrinsic is associated with the region between the metallurgical source and drain junction. The extrinsic capacitances model considered in BSIM3 are fringing capacitance and overlap capacitance, both consist of bias dependent and bias independent part. In this thesis, only the bias independent outer fringing capacitances are added between the gate and source as well as the gate and drain (parameter CF). The overlap capacitances are composed of two parts: (1) bias independent component which models the overlap capacitances between the gate and the heavily doped (non-LDD) source/drain (parameter Cgso, Cgdo); (2) bias dependent between gate and the gate and the lightly doped (LDD) source/drain (parameter Cgsl, Cgdl). Finally, the extrinsic parasitic capacitances are due to the metal routing (M1~M3) parasitic capacitances which can not be de-embedding. Because the open dummy pad we used in this thesis was deembedding to M3, and couldn’t clearly de-embedding the metal routing capacitances below M3. So these parasitic capacitances (Cgs_ext, Cgd_ext, Cds_ext) should be added to the original intrinsic MOSFET model. Fig. 4.5. demonstrates a detailed classification of capacitances in MOSFETs.

Capacitances of RF MOSFET with GSG probing structure are conventionally extracted from the intrinsic Y parameter (Yint) at low frequency. Before the extracting process, parasitic capacitances due to probing pad and interconnection metal should be de-embedded from the measured data. Traditionally, the removal of these parasitics is done through open de-embedding mentioned early. In fact, short de-embedding should also be carried out to get rid of the series impedances. This is essential for accurate capacitance extraction. A broadly accepted de-embedding technique is open/short two step de-embedding for two-port three terminal device (source/bulk tied together) [22]. Due to the fact, a conventional open pad leaving only the GSG pad can not de-embedding all the coupling capacitances. Thus remand the metal connecting between DUT and GSG pad. However, the coupling capacitances

between two port is mainly dominated not only GSG pad but also the interconnection line which may influences the accuracy of capacitances extraction on real device. Therefore, a modified open/short de-embedding approach was used to improve these influence. A modified structure is to remove the DUT cell simply, thus leave the connecting metal between DUT cell and signal metal pad. This modification enables us to extract the capacitances of the DUT cell that is sometimes what a circuit designer need in some cases. Appendix B presents this modified de-embedding. The new de-embedding method is especially efficient when an open pad is designed with all the interconnection metal left.

After the open/short de-embedding, intrinsic gate capacitances can be extracted from the formulas given by [23]:

gg int,11

C = Im(Y )/ω (4-1)

gd int,12

C = - Im(Y )/ω (4-2)

gs int,11 int,12

C = Im(Y +Y )/ω (4-3)

ds int,22 int,12

C =Im(Y +Y )/ω (4-4)

Intrinsic gate-to-back capacitance Cgb is negligible due to its small value in triode and saturation regions. This is because the inversion layer in the channel shields between gate and bulk. In the modeling process, extrinsic components Cgs_ext and Cgd_ext were used to model the remanded parasitic capacitance (M1~M3) and model parameters, Cgso, Cgdo, Cgsl, Cgdl, Voffcv were used to complete the result. With little modification on these model parameters, C-V characteristics ca be modeled well. First, adjust Cgso and Cgdo to a value so that simulation result is close to the measured one. Then, use Voffcv to better fit measured near subthreshold region. Cgsl and Cgdl are employed to modulate the gate bias trend of Cgs and Cgd individually.

Finalized model parameters are shown in Table 4.1. Fig. 4.6. present the modeling result of gate capacitances for multi finger (NF=18, 36, 72) NMOS devices.

Table 4.1

Model parameters for gate capacitances modeling

T13RF-95A

WF=4um NF Cgs_ext(fF) Cgd_ext(fF) Cgs0(F/m) Cgd0(F/m) Cgsl(F/m)Cgdl(F/m) CF(F/m) Voffcv

18 5.37 1.99 360p 386p 70p 70p 0 -0.053

36 9.27 3.69 360p 386p 70p 70p 0 -0.053

72 17.07 7.10 360p 386p 70p 70p 0 -0.053

Modified values

0.0 0.2 0.4 0.6 0.8 1.0 1.

0.0 0.2 0.4 0.6 0.8 1.0 1.2

0.0 0.2 0.4 0.6 0.8 1.0 1.2

0.0 0.2 0.4 0.6 0.8 1.0 1.2

Fig. 4.5.Category diagram of gate capacitances in MOSFETs

0.4 0.6 0.8 1.0 1.2

Chapter 5

Lossy Substrate Model to Predict Pad Structure Effect on RF Noise-Broadband Accuracy & Scalability

In this chapter, the enhanced lossy substrate model was further verified by integrating with the intrinsic devices for full circuit (pad+intrinsic) simulation to identify the impact on high frequency and noise characteristics. The particularly interesting and useful application is an accurate and simple noise extraction method to ensure noise simulation accuracy for nanoscale devices. Before starting the full circuit model calibration. The lossy substrate model must be developed firstly by open pad measurement (chapter 3). Then the model calibration was done on the intrinsic device’s I-V and C-V models(chapter 4). Afterward, 4 terminal parasitic R and L (Rg, Rs, Rd, Rbulk, Lg, Ld, Ls) were correctly extracted and deployed in intrinsic MOSFET. Consequently, good match in terms of gm, Cgg, Cgd, Cgs (Y-parameters), and fT (H-parameters) over wide range of biases or currents was realized for 100nm NMOS of various finger numbers (NF=18, 36, 72). The full circuit model accuracy can be verified in terms S-parameters up to 40GHz and noise parameters up to 18GHz.

5.1 Equivalent Circuit Model Verification

Fig. 5.1. illustrates the device characterization and modeling flow. An equivalent full circuit include the pad model and intrinsic MOSFET model were shown in Fig. 5.2. The RLC networks represents the lossy pad, lossy substrate ,and transmission line are linked with the intrinsic MOSFET. The dash block in the full circuit schematic was the equivalent circuit of intrinsic MOSFET which given by foundry. A core BSIM3 MOSFET model was calibrated in terms of I-V and C-V characteristics. Due to that BSIM3 MOSFET model didn’t include the high frequency characteristic components like gate resistances and substrate network.

Therefore, in order to modeling the intrinsic MOSFET accurately up to 40GHz, some

parasitic components must be added to core BSIM3 model. The parasitic components such as gate resistance, substrate network, Cds ,and Rds were the important and necessary elements for high frequency characterization (S-,Y-parameters). In the intrinsic MOSFET model, two junction diodes were implemented to represent the drain-to-body and source-to-body p-n junctions. Cds and Rds were adopted to model the source to drain proximity capacitance and the associate resistance apparent at high frequency, they play an important role in accurate modeling of S22. Rg is the gate resistance extracted from real part of Z-parameters which is mainly dominated by poly gate resistance and distributed channel-coupled resistance [23]. It’s greatly affects the noise performance of the MOSFET. Rd is the parasitic drain resistance due to the metal routing below M3 which can not be de-embedding. Rs is a series resistance of metal interconnection to the source and substrate network due to that metal line connecting the source/bulk common to the ground pad. Lg, Ld, and Ls are parasitic inductances which required to model the high frequency effect (transmission line effect) of metal routing. The substrate network which has significant effect on high frequency characterization which are constructed of Rdb, Rsb, Rb, Cdb, Csb, Cb. This substrate network model was original given by foundry TSMC, and we have only done calibration by adjusting parameters of the RC substrate network but didn’t change the construction of this substrate network. This method was commonly be used to model the substrate effect by using three resistances and capacitances which the resistances and capacitances were parallel to each other. But we got important observation that these substrate components in series with a junction diode does not show visible effect in the simulated results at most affect S22 at high frequency. Finally, the noise current source ΔSid is used to calibrate the abnormal trends on noise parameters near the subthreshold region in noise measurement of sweep drain current.

How do we develop this full circuit model accurate fitting by circuit simulation to the measured one? First, A accurate pad model which previously established from open pad

good agreement with I-V, C-V, S-parameters. It is fortunate that we didn’t need to do any further optimization to get better fitting with the measured S-parameters, Y-parameters when integrated the pad model with the intrinsic MOSFET model. Finally, the full circuit model parameters for various NF and pad structures are given in table 5-1(a) and (b). The pad model parameters verification for various pad structures has been covered in Chapter 3. We will focus on the intrinsic MOSFET model parameters here. It is assumed that parasitic resistance and inductance of metal interconnection can be removed after short de-embedding. Actually, a common shared short and open pad structures for various NF were been used, and the short de-embedding structures which short to M3 may lead to de-embedding the metal line parasitics (M1~M3) not cleanly. Therefore, the small amounts of remaining parasitic resistances and inductances after short de-embedding was revealed. Cds and Rds played an important role in accurate modeling of S22. As for larger NF devices the larger Cds andsmaller Rds were revealed. It was due to the metal of fingers between source and drain were in parallel.

The bulk resistances also revealed this trend due to the parallel effect. Actually, in two port configuration, since the source and body are tied together. The complex signal coupling at port2 which include drain, source and bulk effect make us difficult to observe drain-bulk and source-bulk coupling effect directly. Many approaches have been proposed to established a accurate substrate model and parameters extraction method. However, a standard extraction and modeling method have not been established yet. In this thesis, a complete substrate network model parameters extraction method was not accomplished and not covered in this work. In our work, the parameters of substrate resistances and capacitances was given by foundry with a default value and made a little optimization.

Table 5-1

(a)Intrinsic MOSFET model parameters for various NF

Cds(fF) Rds(Ω) Rs(Ω) Rd(Ω) Rg(Ω) Ls(pH) Ld(pH) Lg(pH) Rb(Ω) Rdb(Ω) Rsb(Ω) NF=18 4.467 161.8 0.17 0.15 4.819 1.99 7.61 3.064 232.3 16.22 16.22 NF=36 19.54 138.4 0.15 0.12 2.34 2.3 4.225 2.585 168.9 11.14 11.14 NF=72 47 64.72 0.199 0.199 1.119 3.012 1.052 0.478 95.6 5.586 5.586

Intrinsic Model parameters after open/short de-embedded

(b)Pad model parameters for various pad structures

Gate Pad RLC model parameters

Pad layout Cpad (fF) Cp1 (fF) CSi1 (fF) LSi1 (pH) RSi1 (Ω) Ltml (pH) Rtml (Ω)

Lossy 77.87 74.97 200 170.7 159.9

Normal 20 28.55 32.68 425.3 511.7 50 0.2

Small 13.89 24.43 33.4 425.3 511.7

Pad layout Cox (fF) Cp2 (fF) CSi2 (fF) LSi2 (pH) RSi2 (Ω) Cc (fF)

Lossy 10.78 1.629 45.98 515.4 328.8

Normal 9.932 2.553 9.316 874.3 638.3 1.103

Small 9.913 2.635 8.741 874.3 638.3

Drain Pad RLC model parameters

Pad layout Cpad (fF) Cp1 (fF) CSi1 (fF) LSi1 (pH) RSi1 (Ω) Ltml (pH) Rtml (Ω)

Lossy 80.99 62 200 83.72 164.3

Normal 20.17 24.05 30 671.3 511.7 50 0.2

Small 12.84 19.72 30 671.3 511.7

Pad layout Cox (fF) Cp2 (fF) CSi2 (fF) LSi2 (pH) RSi2 (Ω)

Lossy 11.07 2 54.15 590.6 270.9

Normal 10.21 2.887 11.73 1059 540.3

Small 9.932 2.635 10.29 1059 540.3

The full circuit as shown in Fig. 5.2. was adopted for high frequency and noise simulation to achieve S-parameter and noise parameters before de-embedding. First, good

match in terms of gm, Cgg, Cgd, Cgs (Y-parameters), and fT (H-parameters) over wide range of biases or currents was realized for 100nm NMOS of various finger numbers (NF=18, 36, 72).

These intrinsic device parameters (gm, Cgg, Cgd, Cgs, fT) played an important factor in accurate modeling high frequency noise characterization which shown as Fig. 5.3. Further, good agreement with both intrinsic and full circuit model S-parameters in wide range of biases was achieved. Fig. 5.4.~5.11. exhibit good match in S-parameters (magnitude and phase) and Y-parameters (real and imagine part) between model and measurement under Vgs=0.8V at maximum gm for full circuits adopting various pad structures and intrinsic ones after pad de-embedding. It is worth to note that intrinsic S-parameters of the devices after de-embedding are almost the same from different pad structures. It suggested that the de-embedding method could be de-embedding all the parasitic components from GSG pad clearly. In Fig. 5.4.(a)-(c), the phase sign change from negative to positive revealed by full circuits of larger devices (NF=36, 72) at sufficiently high frequency accounts for the parasitic inductance effect. This effect can be eliminated for intrinsic devices in Fig. 5.4.(d) subject to pad and lossy substrate de-embedding. In practice, we can not observe the pad effect obviously with various pad structures in S-, Y- parameters. Furthermore, we will focus on the pad structures effect on RF noise in next section.

5.2 Pad Structure Effect on RF Noise

In this section, we will focus on the lossy substrate effect on high frequency noise and the excess noise introduced through pad and TML for various pad structures. Before this work, the model calibration must be done on the intrinsic device’s I-V, C-V (chapter4), gm, Cgg, Cgd, Cgs (Y-parameters), fT (H-parameters) over wide range of biases or currents was realized for 100nm NMOS of various finger numbers (NF=18, 36, 72), and full circuit S-parameters (pad+intrinsic) for various pad structures. Then this full circuit model accuracy can be

verified in terms noise parameters. Noise parameters (NFmin, Rn, Γopt or Yopt) were measured by ATN-NP5B under Vgs=0.8V at maximum gm, and sweeping frequency to 18GHz. Fig.

5.12.(a)-(c) indicate the simulated extrinsic NFmin and good agreement with measurement for full circuit adopting various pad structures such as lossy, normal, and the small pads respectively. Very interestingly, the devices adopting lossy pad reveal abnormally large finger number dependence and nonlinear frequency response (Fig. 5.12.(a)) while the finger number dependence is much relieved and frequency dependence was recovered to be linear for normal and small pads (Fig. 5.12.(b), (c)). It is very important to research what factors induce this nonlinear frequency response. According to the analytical expression related NFmin to devices parameters as follows:

min 1 m 2 gs

T

( )

F = 1 + K g ( ) = 1 + K C +

g + s ⋅ ⋅ ⋅ g s

m

R R

f R R f

f g (5-1)

According to equation (5-1). For intrinsic devices, it must revealed linear frequency dependence for intrinsic NFmin. So we suggested that this abnormal nonlinear frequency response is due to a great deal of noise coupling (larger Cpad on lossy pad) from lossy substrate which might covered up the real noise characterization on intrinsic devices. The larger NFmin revealed by the smaller finger number (NF) in the category of lossy pads suggested the amplification effect through larger noise resistance Rn for small NF devices (Fig.

5.13.). The larger noise resistance Rn indicate more sensitive to the source impedance.

Another opinion is due to the fact that the pad capacitance may overwhelm the gate capacitance for miniaturized devices. So the small finger number (NF =18) device revealed great influence by pad effect. The intrinsic NFmin simulated by the calibrated model as shown in Fig. 5.12.(d) presents near constant free from finger number dependence over wide range of frequency up to 18GHz. It is due to that the larger gm but smaller Rg for big devices, according to equation (5-1), gm and Rg are complementary to each other which keeping near

10GHz and can be further suppressed to around 0.55dB under Vgs=0.5V corresponding to minimum NFmin. Fig. 5.14.~15. indicate the real(Yopt), imag(Yopt) respectively and good agreement with measurement for full circuit adopting various pad structures (a)~(c) and intrinsic one(d).

Pad structure effect on four noise parameters NFmin, Rn, Re(Yopt), and Im(Yopt) are illustrated in Fig. 5.16.~18. for NF=18, 36, 72, to investigate finger number dependence of excess noise coupled through different pad structures. We can observe that the smallest device (NF=18) in Fig. 5.16.(a)-(b) reveals the largest sensitivity to pad structures with substantial increase in NFmin, Re(Yopt), and Im(Yopt) for lossy pad. The pad sensitivity is obviously suppressed by increasing finger numbers. The pad effects that increase of mentioned excess noise becomes much smaller for NF=72 in Fig. 5.18.(a)-(b). The noise resistance Rn is the key point for this phenomenon. The smaller devices reveal larger noise resistance Rn indicate more sensitive to the source impedance. We suggest it is due to the smaller gm and gate capacitances (Cgg) in small device. The pad capacitances (Cpad) in lossy pad and normal pad are around 100fF and 20fF respectively which close to the small device NF=18 (Cgg≈100fF).

Therefore, the pad capacitances will affects the source impedance greatly in small device (NF=18) but not obvious affects on large device (NF=72 for Cgg ≈ 400fF). As a result, the smaller device reveals larger sensitivity to various pad structures. Note that Rn is effectively reduced by increasing NF attributed to smaller Rg and larger gm but keeps nearly constant for different pad structures. The pad effects were revealed on Re(Yopt) and Im(Yopt) then responded to NFmin. The scalability and broadband accuracy of the lossy substrate model is proven by good agreement with measured noise parameters corresponding to various pads as well as finger numbers and over wide range of frequencies to 18GHz. Based on the proven lossy substrate model and calibrated intrinsic MOSFET model, lossy substrate de-embedding can be done by removing the elements of the lossy pad and substrate R-L-C network from the full circuit model in Fig. 5.2. The parasitic resistance like Rg, Rd, Rs, Rb, etc, which can not be

removed through de-embedding were left with intrinsic MOSFET model to account for the excess noise. The intrinsic noise parameters extracted through lossy substrate de-embedding indicates effective reduction and recovery to linear frequency dependence in NFmin, Re(Yopt), and Im(Yopt). The extracted intrinsic Re(Yopt) and Im(Yopt) were compared with extrinsic Yopt

(measured or simulated) to identify the effect through lossy substrate de-embedding. This obvious reduction of Re(Yopt) through de-embedding contributes to the significant suppression of NFmin. It is worth to note that NFmin of small pads are effectively suppressed near the intrinsic values. The physical parameters Cpad was play an important role on lossy substrate excess noise coupling. The larger Cpad caused the larger excess noise coupling path from the silicon substrate. With careful observe, the most amount of excess noise was contributed from lossy substrate under the signal pad (through Cpad), and minor amount of excess was contributed from lossy substrate under inter connection line (through Cox).

As a result, the enhanced lossy substrate model of two R-L-C networks introduced via pad and TML justify themselves scalable through the physical parameters Cpad and Cox, which consistently follow the pad and TML layout as well as metal topology parameters. The extreme conditions of fully open or fully short along pad and TML can be simulated by the scalable model to explore the optimized layout to approach the intrinsic noise characteristics.

The simulation subject to extreme conditions suggests that elimination of Cpad, fully open along pad can minimize substrate loss induced excess noise and attain the intrinsic characteristics. On the other hand, elimination of Cox, full isolation along TML makes minor contribution provided that Cpad stays not reduced. The proven scalable model is useful to guide pad and TML layout to minimize noise for miniaturized devices.

RF MOSFETs

T

OX

, L

g

, W

F

, N

F

Noise mea.

NF

min

Rn

Y

opt

opt

) AC mea.

Y, H-parameter

C

gg

, C

gd

, C

gs

f

T

Intrinsic MOSFET

R, L extraction

Finalized full circuit S-par mea.

open de-embedding

short de-embedding DC mea.

I

d

g

m

, g

ds

S-par

open pad

through pad

BSIM3 I-V

model BSIM3 C-V model

Intrinsic MOSFET model

I

d

, g

m

, g

ds

C

gg

, C

gd

, C

gs

f

T

Lossy pad & lossy substrate RLC equivalent ckt analysis

Initial guess of RLC parameters

Lossy pad & lossy substrate RLC equivalent ckt calibration and optimization

Noise simulation

S-parameters

Noise paramters

Fig. 5.1.MOSFET device modeling flow

Rs

Fig. 5.2.Full circuit model includes intrinsic MOSFET device and pad model

0.0 0.2 0.4 0.6 0.8 1.0 1.2

Fig. 5.3. Intrinsic MOSFET modeling results with good match in terms of (a)gm, (b)fT (c)Cgg, (d)Cgd, and over wide range of biases or currents

0 10 20 30 40 Full ckt, Lossy pad

Vg@max gm=0.8V Full ckt, small pad

Vg@max gm=0.8V

Full ckt, normal pad Vg@max gm=0.8V

Fig. 5.4.Comparison of measured and simulated S11 by full circuit model for 100nm NMOS(NF=18,36,72) adopting 3 different pads,(a)lossy pad (b)normal pad (c)small pad (d)intrinsic S11 by pad de-embedding

0 10 20 30 40 Full ckt, Lossy pad

Vg@max gm=0.8V Full ckt, small pad

Vg@max gm=0.8V

Full ckt, normal pad Vg@max gm=0.8V

Full ckt, Lossy pad Vg@max gm=0.8V Full ckt, small pad

Vg@max gm=0.8V

Full ckt, normal pad Vg@max gm=0.8V

Fig. 5.5.Comparison of measured and simulated S22 by full circuit model for 100nm NMOS(NF=18,36,72) adopting 3 different pads,(a)lossy pad (b)normal pad (c)small pad (d)intrinsic S22 by pad de-embedding

0 10 20 30 40

Mag(S 21) Mag(S 21)

Measure N=18 N=36 N=72 Line: model Full ckt, Lossy pad

Vg@max gm=0.8V Full ckt, small pad

Vg@max g

m=0.8V

Full ckt, normal pad Vg@max g Full ckt, Lossy pad

Vg@max gm=0.8V Full ckt, small pad

Vg@max gm=0.8V

Vg@max gm=0.8V

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