Chapter 3 Low-Standby-Power Output Feedback Scheme
3.6 Comparison
In Section 2.3, we have introduced three different solutions trying to reduce the
power loss of the conventional feedback network. The primary-side control solution
leaves out the entire feedback network while suffering from poor output voltage
regulation. The system output power (continuous-conduction mode is avoided) and the
minimum output load (dummy load is needed) are both limited. These disadvantages are
in fact originated from the removal of the explicit feedback path and are not going to
bother designers in [55], [56], and this proposed work.
In comparison to the output voltage control method [55] and the feedback
impedance modulation technique [56], this proposed method does not explicitly change
the system feedback behaviors such as the feedback impedance or the controlled target.
No matter how the load changes, from a light to a heavy load or vice versa, the feedback
loop will constantly exist and automatically react to the present load condition without
any purposely interrupting by the controller. As long as the loop gain is properly
designed, there is basically no risk of instability under which the converter system leaps
back and forth between the heavy-load and the light-load modes. As for the performance
on saving the power under very light/no-load conditions, the proposed scheme clears
out both the primary and the secondary-side currents of the optocoupler by separating
the supply current of the reverse-type shunt regulator from flowing through the
optocoupler. The loss caused by the supply current is thus not replicated. Accordingly,
this proposed feedback network consumes even less power than those two previous
techniques do. However, a main shortcoming is that the proposed reverse-type shunt
regulator requires a 4-pin encapsulation rather than only 3 pins as the conventional
shunt regulator does, leading to a slightly increase in cost.
3.7 Conclusion
The phase reversal concept is proposed to address the power loss issue of the
feedback network. With this idea, the currents (I and I ) flowing though the
optocoupler and thus the generated power loss are decreased with the output power.
Following that, a complete feedback network is designed in accordance with the
proposed concept. On the secondary side, on account of the feasibility of building the
Miller compensation, we use a reverse-type shunt regulator to source current to the
optocoupler. The current controlling device inside the regulator is realized with a pMOS
rather than an nMOS to avoid the body effect. Also, the supply current of the
reverse-type shunt regulator is not going to flow through the optocoupler, which makes
this part of power dissipation not reproduced on the primary side. On the primary side,
an additional inverting amplifier is adopted right before the PWM modulator to reverse
the feedback signal again for achieving a negative feedback loop. The power loss
analysis of the proposed feedback network shows an evident improvement over the
traditional circuit when the converter operates in the burst mode. Also, the control loop
of the proposed network is analyzed to check its validity, which shows that the midband
gain will never be limited by RLED. In comparison with prior techniques, the proposed
feedback network not only really minimizes its power loss under very light/no load
conditions but also possesses no potential instability issue when the output load
suddenly changes from a light to a heavy load.
Chapter 4 Experiments
4.1 Introduction
In this chapter, material regarding experiments is presented. To verify the
effectiveness of the proposed feedback network, we intend to apply the feedback
network to a flyback converter and carry out a set of experiments. Therefore, the first
part in this chapter presents the designs of a PWM controller and a reverse-type shunt
regulator which is used for implementing the proposed system. Following that, a
conventional and a proposed testing systems are implemented for comparison.
Experimental results together with discussions are described at last.
4.2 Integrated Circuit Design
The chip design is of much great importance for a reliable system and hence
should be done with great caution. We present the design considerations for key
building blocks in the two integrated circuits.
4.2.1 Reverse-Type Shunt Regulator
The whole circuit diagram of the reverse-type shunt regulator is illustrated in Fig.
4.1. It features 4-pin connections, including a supply pin VDD, a pin VOF for the
positive input terminal of the error amplifier, a pin VDT for the drain terminal of M ,
Fig. 4.1. The reverse-type shunt regulator.
and a ground pin VSS. In the system configuration, VDD is supplied by the converter
output, whereas VOF is tied to the properly divided one. The reference generator shown
in the left part of the figure employs the three-terminal bandgap reference technique
[58], and it directly produces a temperature-compensated output voltage of 2.5 V with a
simple circuit structure. The bandgap core circuit is composed of a pMOS current
mirror which takes the difference between I1 and I2 to drive the next stage, a pair of npn
transistors with Q2 larger than Q1 by a ratio of 8 to 1, and resistors R1 and R2. For
narrowing the variation of the generated reference voltage, an additional common-
source amplifier stage made of M3 and M4 is inserted between the bandgap core circuit
and the output stage to increase the loop gain. Its bias current is mirrored directly from
the current mirror M1-2. R4 and R5 are tuned such that a voltage of 2.5 V is obtained,
while R3 is set according to [58] for minimizing the base current effect. For stabilizing
the loop, we utilize the added common-source amplifier to build the Miller
compensation. The simulation (Fig. 4.2) shows that this reference generator presents a
voltage variation of 0.34% with VDD varying from 4.5 V to 12.5 V and temperature from
−40 °C to 100 °C. The loop possesses a DC gain of 73 dB while maintaining an overall
phase margin greater than 70°. It should be noted that the start-up circuit (the gray
portion in Fig. 4.1) is appended to prevent the bandgap core from getting stuck in the
zero-current state. As the reference voltage is high enough, the pull-down device (M11)
will be turned OFF and in the long run leave no effect on the performance of the
reference generator.
For the consideration of large output swing, the error amplifier adopts the
two-stage operational amplifier structure with its bias current mirrored from the
reference generator. The output of the amplifier drives an open-drain configured pMOS
MP for controlling ILED. The error amplifier must provide a sufficient speed while
consuming a power as little as possible. For large-signal operations, we ensure that the
slew rate is large enough to pull the gate voltage of MP up to VDD or down to ground
within a switching cycle period. Since the maximum switching frequency in our system
would be 60 kHz, the target slew rate is set 0.8 V/μs. For the small-signal behavior, the
3-dB corner frequency is kept beyond 10 kHz in order to have little impact on the
Fig. 4.2. Simulation result of the reference generator.
compensator design of converter system. The simulation shows that the corner
frequency is at 15 kHz. The simulated equivalent transconductance Gmrv at low
frequency is 4.86 Ω−1 under the condition that MP conducts a ILED of 1 mA.
4.2.2 PWM Controller
Owing to the fact that, as described previously, the phase of the feedback signal is
reversed, existing PWM controllers on the market are not applicable to power
converters using the proposed feedback network. Besides, to measure how much benefit
will result from the proposed feedback scheme, we plan to design and compare two
converters with different feedback topologies; however, their performances are highly
dependent on the qualities of their controllers, making it very hard to purely evaluate the
relative merits of feedback methods if an arbitrary commercial controller is used to
build the conventional converter. For these two reasons, we design a PWM controller in
which a proposed and a conventional feedback paths are both integrated. Adopting this
specially designed controller in converters with respectively the proposed and the
conventional feedback schemes can promise a fair comparison between them because
they are different only in the feedback circuits while all the other building blocks
are the same.
Fig. 4.3 shows the block diagram. VCC is the power supply pin, from whose
voltage VCC an on-chip LDO regulates an output voltage VLO of 5 V. Except the gate
driver, the under-voltage-lockout (UVLO) circuit, and the LDO, all the other circuits are
supplied by VLO. The dual-mode feedback circuit includes a conventional and a
proposed feedback paths and can be manually selected by applying an external voltage
to VMS. Once VMS is given, the feedback circuit will receive the output voltage
information from FBP or FBC pin and send an analogue signal VCT to the PWM
modulator and the oscillator. The switching frequency fSW provided by the oscillator is
normally set 60 kHz. Nonetheless, under light-load conditions, the oscillator which is
controlled by VCT will enter the power-saving mode and the frequency will be gradually
decreased with a minimum value of 20 kHz. If even less current is demanded by the
output load such that VCT continuously drops below the burst-mode threshold voltage,
the oscillator will stop switching. Fig. 4.4 shows the simulated switching frequency
versus VCT. The burst-mode threshold voltages for the proposed (VRBUP, from the
viewpoint of V ) and the conventional (V ) networks are different and are also
Fig. 4.3. Block diagram of the PWM controller.
Fig. 4.4. Simulated switching frequency versus VCT.
selected according to VMS. The reason for the difference will be explained later. In order
to ensure a successful start-up, a soft-start level generator that offers preset voltage
levels for the PWM modulator is also included. The modulator simultaneously takes VST
and VCT as the current limit, but only the lower one of them involves in the pulse
generation process. Note that the sensed inductor current VCS is slope-compensated for
achieving a stable current-mode control when the converter operates in the
continuous-conduction mode.
The detailed primary-side feedback circuit is illustrated in Fig. 4.5. There are two
major blocks. The upper one is just the conventional feedback path, while the lower one
is for the proposed feedback scheme. The actual path in use depends on the one-bit
selection voltage VMS which is externally applied. Thus, the PWM controller is capable
of the dual-mode operation. Note that, although not clearly illustrated in the figure for
simplicity, VMS not only determines which path is to be used, but also is responsible for
activating a mechanism to turn OFF all the circuits in the unselected path. That is, when
one of the two paths is chosen for operation, the other one will be completely disabled
and consume zero current. Consequently, adopting this controller in converters with
different feedback schemes ensures a fair comparison. Now, let us look into the block of
the proposed feedback path. The inverting amplifier is implemented by incorporating
the Opamp together with RI1 and RI2. The values of RI1 and RI2 are selected to be much
larger than RP1 so as to reduce the loading effect imposed on VFBP. In addition, the
corner frequency of this inverting amplifier should be kept sufficiently large; otherwise
it will affect the frequency compensation of system. In our design, we choose RP1 = RP2
= 4 kΩ and R = R = 300 kΩ, resulting in an amplifier gain of −1 V/V and a 3-dB
Fig. 4.5. Dual-mode feedback circuit.
bandwidth of 70 kHz. Note that the bias voltage of the Opamp’s positive input terminal
is 2.5 V; hence, the Opamp’s output voltage and VFBP are in fact symmetric about VLO/2.
In Section 3.4, we say that in the proposed scheme the burst-mode threshold voltage
VBUP from the viewpoint of VFBP should be set close to VLO. This can be done as well by
setting the threshold voltage VRBUP from the viewpoint of VCT to be close to the ground
because when the proposed feedback path is selected, VFBP and VCT have opposite
phases. In the burst mode, the lower VRBUP is, the higher VFBP and thus the lower IFBP
would be. This is why we set VRBUP lower than VBUC as Fig. 4.4 shows.
Another issue that we have to cope with is related to the start-up. When the
proposed feedback network is adopted, we expect that if the converter output voltage
VOUT is below the nominal value, the optocoupler would draw large currents on both
sides and VFBP in Fig. 4.5 would be pulled down. This prediction is true, however, only
when VOUT is at least larger than a certain value that enables the reverse-type shunt
regulator to function normally and to draw sufficiently large current (ILED). To inspect
what really happens during start-up, we illustrate some key waveforms in Fig. 4.6. The
start-up process will begin after the UVLO is triggered (VUV is high). At the very
beginning of this period, VFBP will be directly pulled up to VLO because of zero ILED and
IFBP. This phenomenon will lead to a minimum ON-time of the power switch, which
will cause a strong possibility of start-up failure. In order to fix this problem, the
soft-start level generator along with some control logics can help get over it. Also
shown in Fig. 4.5, two switches S1 and S2 controlled by a pair of complementary signals
from an SR latch are applied to pass through the feedback signal or directly to short VCT
to VLO. Before all the reference/bias voltages are settled down, the SR latch is reset.
Therefore, VCT is shorted to VLO and the duty cycle of driving pulses is preliminary
determined by the soft-start levels (VST) because in this time VCT is larger than VST.
Later, VFBP will gradually slide down to zero with VOUT climbing up. Once VFBP drops
below V (1 V in our design), the comparator will change its output state. If V is also
Fig. 4.6. Simulated waveforms during start-up.
logic HIGH in the meantime, the AND gate will set the SR latch such that S1 and S2
interchange their states. Afterwards, the feedback loop is established to take over the
system control. The purpose of VDE is to blank the time period at which VFBP is charged
to VLO. Since this period is relatively short (e.g., it takes about 120 μs for VFBP to
achieve 90% of VLO with CP1 = 10 nF) compared to the overall start-up duration, we allocate a blanking time interval of 500 μs, therefore. Simulations give that when this
controller drives a 1-nF capacitor, the average current consumption is 1.8 mA with VFBP
= 2.5 V and becomes 0.3 mA with VFBP = 5 V. The reduction in power is principally
resulted from both the zero IFBP and the ceasing of gate driving.
4.2.3 Chip Fabrication
The proposed reverse-type shunt regulator and the PWM controller have been
(a) (b)
Fig. 4.7. Die micrographs of (a) the PWM controller and (b) the reverse-type shunt regulator.
designed and fabricated in VIS 0.5-μm 5-V/40-V high-voltage CMOS technology. Fig.
4.7 shows the die micrographs, where the PWM controller occupies 4.67 mm2 and the
reverse-type shunt regulator 1.22 mm2 including pads. Single-chip measurements
confirm that RP1 = RP2 = 4 kΩ and VLO is 5 V. The burst-mode threshold voltages VBUP
and VBUC are measured to be 4.5 V and 1 V, respectively. The measured supply current
IQ of the reverse-type shunt regulator is around 250 μA.
4.3 System Design
After the PWM controller and the reverse-type shunt regulator are ready,
converters for experiments can be designed. The system specification we choose is a
12-V/18-W single-output flyback converter with universal inputs, and the crossover
frequency is at 2 kHz with a phase margin of 90°. Fig. 4.8 shows the well-designed
Fig. 4.8. Power stage of the flyback converter for experiments.
TABLE 4.1
Component Values and Part Numbers in the Power Stage
power stage with all component values and part numbers listed in Table 4.1. To design
the feedback network, we should first use a simulator to obtain the transfer function of
the power stage from VCT to the output. The result is portrayed using the lighter line in
Fig. 4.9. Bode plot of the designed power stage and the proposed feedback network.
Fig. 4.10. The designed loop gain of the converter
Fig. 4.11. The off-chip feedback circuit of the converter adopting the proposed feedback scheme.
TABLE 4.2
Component Values and Part Numbers in the Proposed Feedback Circuit
Fig. 4.12. The off-chip feedback circuit of the conventional converter.
Fig. 4.9 which shows that the feedback loop should provide an additional gain of about
7.8 dB and a phase boost of 57° at fC. The designed frequency response of the proposed
feedback loop is depicted using the darker line in Fig. 4.9. Fig. 4.10 gives the Bode plot
TABLE 4.3
Component Values and Part Numbers in the Conventional Feedback Circuit
Fig. 4.13. The designed loop gain of the conventional converter.
of the overall loop gain, and it shows that the phase margin is nearly 90° at 2 kHz. Fig.
4.11 shows the overall proposed off-chip feedback circuit with all component values
and part numbers listed in Table 4.2. Similarly, the conventional feedback network
designed for the same power stage is illustrated in Fig. 4.12 with all component values
(a)
(b)
Fig. 4.14. Testing boards of (a) converter adopting the proposed feedback topology and (b) converter with the conventional feedback topology.
overall loop gain. Note that the power stages of the two converters are exactly the same.
In addition, output voltage dividers of the two converters are set identical, making them
dissipate the same amount of power to ensure fairness. Fig. 4.14 shows the testing
boards of the two converters. The bare dies of both the PWM controller and the
reverse-type shunt regulator are first placed and wire-bonded to printed circuit boards,
and then those boards can be plugged into sockets on the system boards.
4.4 Experimental Results and Discussions
The two demo boards shown in Fig. 4.14 are next taken for testing. We describe
the experimental results and make some discussions as follows.
4.4.1 No-Load Power Loss
First, we measure the performances of the two converters with no load applied.
The testing setup for this experiment is shown in Fig. 4.15. A power analyzer is
connected in series between a DC power supply and the device under test, and an
oscilloscope is used to observe the waveforms. Fig. 4.16(a) shows the captured
operating waveforms of the converter with the proposed feedback network under the
no-load condition. Since the burst mode threshold voltage VBUP is set 4.5 V and VFBP
remains at VLO for about three quarters of one burst period, the power loss resulted from
the second term in (3.3) or (3.4) can be estimated to be well below 1 mW, which proves
the validity of the approximation equations (3.7) and (3.8). As for the conventional
converter, its waveforms under the no-load condition are shown in Fig. 4.16(b). In this
case, VFBC almost sticks to the burst-mode threshold voltage VBUC of 1 V, and the
measured IFBC is 1 mA. These truths rationalize the calculation of PL,con. in Section
2.2.4.
The power analyzer PM1000+, which is capable of low-standby-power
measurements, is used to capture and average the output power of the DC supply in
measurements, is used to capture and average the output power of the DC supply in