PWM Controller

Owing to the fact that, as described previously, the phase of the feedback signal is

reversed, existing PWM controllers on the market are not applicable to power

converters using the proposed feedback network. Besides, to measure how much benefit

will result from the proposed feedback scheme, we plan to design and compare two

converters with different feedback topologies; however, their performances are highly

dependent on the qualities of their controllers, making it very hard to purely evaluate the

relative merits of feedback methods if an arbitrary commercial controller is used to

build the conventional converter. For these two reasons, we design a PWM controller in

which a proposed and a conventional feedback paths are both integrated. Adopting this

specially designed controller in converters with respectively the proposed and the

conventional feedback schemes can promise a fair comparison between them because

they are different only in the feedback circuits while all the other building blocks

are the same.

Fig. 4.3 shows the block diagram. VCC is the power supply pin, from whose

voltage VCC an on-chip LDO regulates an output voltage VLO of 5 V. Except the gate

driver, the under-voltage-lockout (UVLO) circuit, and the LDO, all the other circuits are

supplied by VLO. The dual-mode feedback circuit includes a conventional and a

proposed feedback paths and can be manually selected by applying an external voltage

to VMS. Once VMS is given, the feedback circuit will receive the output voltage

information from FBP or FBC pin and send an analogue signal VCT to the PWM

modulator and the oscillator. The switching frequency fSW provided by the oscillator is

normally set 60 kHz. Nonetheless, under light-load conditions, the oscillator which is

controlled by VCT will enter the power-saving mode and the frequency will be gradually

decreased with a minimum value of 20 kHz. If even less current is demanded by the

output load such that VCT continuously drops below the burst-mode threshold voltage,

the oscillator will stop switching. Fig. 4.4 shows the simulated switching frequency

versus VCT. The burst-mode threshold voltages for the proposed (VRBUP, from the

viewpoint of V ) and the conventional (V ) networks are different and are also

Fig. 4.3. Block diagram of the PWM controller.

Fig. 4.4. Simulated switching frequency versus VCT.

selected according to VMS. The reason for the difference will be explained later. In order

to ensure a successful start-up, a soft-start level generator that offers preset voltage

levels for the PWM modulator is also included. The modulator simultaneously takes VST

and VCT as the current limit, but only the lower one of them involves in the pulse

generation process. Note that the sensed inductor current VCS is slope-compensated for

achieving a stable current-mode control when the converter operates in the

continuous-conduction mode.

The detailed primary-side feedback circuit is illustrated in Fig. 4.5. There are two

major blocks. The upper one is just the conventional feedback path, while the lower one

is for the proposed feedback scheme. The actual path in use depends on the one-bit

selection voltage VMS which is externally applied. Thus, the PWM controller is capable

of the dual-mode operation. Note that, although not clearly illustrated in the figure for

simplicity, VMS not only determines which path is to be used, but also is responsible for

activating a mechanism to turn OFF all the circuits in the unselected path. That is, when

one of the two paths is chosen for operation, the other one will be completely disabled

and consume zero current. Consequently, adopting this controller in converters with

different feedback schemes ensures a fair comparison. Now, let us look into the block of

the proposed feedback path. The inverting amplifier is implemented by incorporating

the Opamp together with RI1 and RI2. The values of RI1 and RI2 are selected to be much

larger than RP1 so as to reduce the loading effect imposed on VFBP. In addition, the

corner frequency of this inverting amplifier should be kept sufficiently large; otherwise

it will affect the frequency compensation of system. In our design, we choose RP1 = RP2

= 4 kΩ and R = R = 300 kΩ, resulting in an amplifier gain of −1 V/V and a 3-dB

Fig. 4.5. Dual-mode feedback circuit.

bandwidth of 70 kHz. Note that the bias voltage of the Opamp’s positive input terminal

is 2.5 V; hence, the Opamp’s output voltage and VFBP are in fact symmetric about VLO/2.

In Section 3.4, we say that in the proposed scheme the burst-mode threshold voltage

VBUP from the viewpoint of VFBP should be set close to VLO. This can be done as well by

setting the threshold voltage VRBUP from the viewpoint of VCT to be close to the ground

because when the proposed feedback path is selected, VFBP and VCT have opposite

phases. In the burst mode, the lower VRBUP is, the higher VFBP and thus the lower IFBP

would be. This is why we set VRBUP lower than VBUC as Fig. 4.4 shows.

Another issue that we have to cope with is related to the start-up. When the

proposed feedback network is adopted, we expect that if the converter output voltage

VOUT is below the nominal value, the optocoupler would draw large currents on both

sides and VFBP in Fig. 4.5 would be pulled down. This prediction is true, however, only

when VOUT is at least larger than a certain value that enables the reverse-type shunt

regulator to function normally and to draw sufficiently large current (ILED). To inspect

what really happens during start-up, we illustrate some key waveforms in Fig. 4.6. The

start-up process will begin after the UVLO is triggered (VUV is high). At the very

beginning of this period, VFBP will be directly pulled up to VLO because of zero ILED and

IFBP. This phenomenon will lead to a minimum ON-time of the power switch, which

will cause a strong possibility of start-up failure. In order to fix this problem, the

soft-start level generator along with some control logics can help get over it. Also

shown in Fig. 4.5, two switches S1 and S2 controlled by a pair of complementary signals

from an SR latch are applied to pass through the feedback signal or directly to short VCT

to VLO. Before all the reference/bias voltages are settled down, the SR latch is reset.

Therefore, VCT is shorted to VLO and the duty cycle of driving pulses is preliminary

determined by the soft-start levels (VST) because in this time VCT is larger than VST.

Later, VFBP will gradually slide down to zero with VOUT climbing up. Once VFBP drops

below V (1 V in our design), the comparator will change its output state. If V is also

Fig. 4.6. Simulated waveforms during start-up.

logic HIGH in the meantime, the AND gate will set the SR latch such that S1 and S2

interchange their states. Afterwards, the feedback loop is established to take over the

system control. The purpose of VDE is to blank the time period at which VFBP is charged

to VLO. Since this period is relatively short (e.g., it takes about 120 μs for VFBP to

achieve 90% of VLO with CP1 = 10 nF) compared to the overall start-up duration, we allocate a blanking time interval of 500 μs, therefore. Simulations give that when this

controller drives a 1-nF capacitor, the average current consumption is 1.8 mA with VFBP

= 2.5 V and becomes 0.3 mA with VFBP = 5 V. The reduction in power is principally

resulted from both the zero IFBP and the ceasing of gate driving.