Oxide Thinning and Structure Scaling Down Effect of Low-Temperature Poly-Si Thin-Film Transistors

12 JOURNAL OF DISPLAY TECHNOLOGY, VOL. 8, NO. 1, JANUARY 2012

Oxide Thinning and Structure Scaling Down Effect

of Low-Temperature Poly-Si Thin-Film Transistors

William Cheng-Yu Ma, Tsung-Yu Chiang, Je-Wei Lin, and Tien-Sheng Chao, Senior Member, IEEE

Abstract—In this paper, the gate oxide thickness, and the channel length and width of low-temperature poly-Si thin-film transistors (LTPS-TFTs) have been comprehensively studied. The scaling down of gate oxide thickness from 50 to 20 nm significantly improves the subthreshold swing (S.S.) of LTPS-TFTs from 1.797 V/decade to 0.780 V/decade and the threshold voltage _THfrom 10.87 V to 5.00 V. Moreover, the threshold voltage _TH roll-off is also improved with the scaling down of gate oxide thickness due to gate capacitance density enhancement. The channel length scaling down also shows significant subthreshold swing S.S. im-provement due to a decreasing of the channel grain boundary trap density . However, the scaling down of channel length also increases the series resistance effect, resulting in the degradation of the field-effect mobility _FE. Therefore, the channel length dependence of field-effect mobility _FEis slightly different with different channel width due to the competition of channel grain boundary trap density effect and series resistance effect.

Index Terms—Gate oxide thickness, low-temperature poly-Si thin-film transistors (LTPS-TFTs), scaling down.

I. INTRODUCTION

L

OW-TEMPERATURE polycrystalline silicon (LTPS) thin-film transistors (TFTs) have been used for active-ma-trix liquid crystal displays (AMLCDs) on glass substrates as pixel and driving integrated circuits instead of amorphous silicon [1]–[8]. This is because the field-effect mobility in polycrystalline silicon is significantly higher (by two or-ders of magnitude) than that in amorphous silicon [6], so that CMOS devices with reasonably high drive currents can be achieved in polycrystalline silicon. Recently, the topic of system-on-panel (SOP) is attracting much attention. Therefore, high-performance TFTs with high driving current, low gate leakage current, low threshold voltage and subthreshold swing S.S. are required urgently for high-speed display driving circuits [9], [10]. Increasing the gate capacitance density is a direct and simple method of improving the performance and specifically the driving current of LTPS-TFTs. Therefore, a comprehensive study of the effect of reducing gate oxide thickness in LTPS-TFTs is important for further development. Here, we investigate the gate oxide thickness scaling impacts of LTPS-TFTs with different channel length and width

Manuscript received April 26, 2011; revised July 09, 2011; accepted July 18, 2011. This work was supported by the National Science Council of the Republic of China under Contract NSC 100-2221-E-009-012-MY3. Date of publication September 29, 2011; date of current version January 04, 2012.

The authors are with the Institute and Department of Electrophysics, National Chiao Tung University, Hsinchu 300, Taiwan (e-mail: [email protected]; [email protected]; [email protected]; tschao@mail. nctu.edu.tw).

Color versions of one or more of the figures are available online at http:// ieeexplore.ieee.org.

Digital Object Identifier 10.1109/JDT.2011.2162938

on the electrical behavior of threshold voltage , field-effect mobility , and subthreshold swing S.S.

II. EXPERIMENTALPROCEDURE

The fabrication of devices was started by depositing an undoped amorphous Si ( -Si) layer 55-nm at 550 C in a low-pressure chemical vapor deposition (LPCVD) system on Si wafers capped with a 500-nm thick thermal oxide layer. Then, the -Si layer was recrystallized by a solid-phase-crys-tallization (SPC) process in furnace at 600 C for 24 h in a N ambient. After the crystallization of the channel film, the active region was patterned by dry etching. Then, three thicknesses of gate oxide 20, 32, and 50 nm were deposited by plasma-enhanced chemical vapor deposition (PECVD) system at 300 C. 250-nm in situ N doped -Si is deposited by LPCVD at 550 C as the gate electrode. After gate stack patterning, the gate and source/drain regions are implanted with phosphorus (15 keV at 5 10 cm ) and activated at 600 C for 24 h annealing in a N ambient. A 500-nm PECVD oxide is deposited for the passivation layer. After the patterning of contact holes, aluminum was deposited by thermal evaporation system and patterned as the probe pads to complete the TFT devices. The grain size of the polycrystalline Si channel is about 250–300 nm [9]. Generally, LTPS-TFT with SPC process has many grain boundaries within the poly-Si channel, resulting in many electrical traps exist. These traps would capture carriers to create potential barriers, resulting in poor subthreshold swing S.S., higher threshold voltage , lower field-effect mobility and poor performance. Therefore, hydrogenation process is usually used to passivate these traps to improve the electrical behavior of LTPS-TFTs [11]. In order to study the intrinsic electrical property of LTPS-TFTs, there is no any defect passivation process in our fabrication of LTPS-TFTs.

The threshold voltage is defined as at which reaches 100 nA and V. The field-effect mobility is extracted from the maximum transconductance

.

III. RESULTS ANDDISCUSSION

Fig. 1 shows the transfer curves – and field-effect mobility of LTPS-TFTs with different gate oxide thick-ness. The subthreshold swing S.S. is significantly improved from 1.797 V/decade to 0.780 V/decade when the gate oxide thickness is scaled from 50 to 20 nm. The subthreshold swing S.S. should be strongly related to the gate capacitance density and interface states according to the Dimitriadis model [12]

(1)

Fig. 1. Transfer curve(I –V ) and field-effect mobility  of LTPS-TFTs with three gate oxide thickness 50, 32, and 20 nm.

TABLE I

IMPORTANTDEVICEPARAMETERS OFLTPS-TFTSWITHDIFFERENTOXIDE THICKNESSt , 55-NMCHANNELFILMTHICKNESS,W=L = 10 m=10 m

Fig. 2. Transfer curve(I –V ) and field-effect mobility  of LTPS-TFTs with 50-nm gate oxide thickness, channel widthW = 10 m and four channel lengthL = 10; 2; and 1 m.

The extracted interface states and other important pa-rameters are listed in the Table I. It shows that the interface states of LTPS-TFTs with different gate oxide thickness are the same, indicating the subthreshold swing S.S. improve-ment is completely attributed to the increase in the gate capaci-tance density . It also indicates the oxide/Si interface quality of LTPS-TFTs with different gate oxide thickness is the same. In addition, the field-effect mobility of LTPS-TFTs with different gate oxide thickness are comparable, indicating the

Fig. 3. Threshold voltageV versus channel lengthL of LTPS-TFTs with three gate oxide thickness 50, 32, and 20 nm.

Fig. 4. Threshold voltageV versus gate oxide thickness of LTPS-TFTs with four channel lengthL = 10; 5; 2; and 1 m.

field-effect mobility is less dependent on gate capacitance density if the oxide–Si interface and channel film quality is the same.

Fig. 2 shows the transfer curves of LTPS-TFTs with different channel length . Significant threshold voltage roll-off is observed, as shown in Fig. 3, and reducing the gate oxide thick-ness from 50 to 20 nm enhances the control afforded by the gate, thereby improving the threshold voltage roll-off. Fig. 4 shows the gate oxide thickness dependence of threshold voltage , indicating that the threshold voltage is almost linearly proportional to oxide thickness whether the channel length is long or short.

In addition to threshold voltage behavior, the channel length dependence of field-effect mobility and sub-threshold swing S.S. are also shown in Fig. 5. The reduction in subthreshold swing S.S. with decrease of the channel length is due to the decreasing of channel grain boundary trap density

when the channel length is decreasing, resulting in fewer surface interface states . The channel grain boundary trap

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Fig. 5. Channel lengthL dependence of field-effect mobility  and sub-threshold swing S.S of LTPS-TFTs with channel widthW = 10 m and three gate oxide thickness 50, 32, and 20 nm.

Fig. 6. Plot ofln[I =(V 0V )] versus 1=(V 0V ) curves of LTPS-TFTs atV = 1:0 V and high V with channel widthW = 10 m and four channel lengthL = 10; 5; 2; and 1 m.

density of LTPS-TFTs with different channel length are extracted from the plot of versus

curves at V and high [13], [14], as shown in Fig. 6. When the channel length or width is much larger than the grain size, the average grain boundary density is fairly constant, resulting in less device dimension dependence of electrical behavior of LTPS-TFTs. As the device dimension is reduced the number of grain boundaries in the channel becomes small, and therefore the varying number of grain boundaries between devices becomes significant, resulting in greater variation in device characteristics. Fig. 5 also shows that the field-effect mobility is reduced when the channel length is decreased. With the reduction of channel length , the grain boundary trap density would decrease, and the series resistance effect would be more serious [15], [16]. A reduced grain boundary density could

Fig. 7. Channel lengthL dependence of field-effect mobility  of LTPS-TFTs with channel widthW = 10 m before and after series resistance R calibration.

Fig. 8. Transfer curve(I –V ) and field-effect mobility  of LTPS-TFTs with 50 nm gate oxide thickness, channel widthW = 1 m and four channel lengthL = 10; 5; 2; and 1 m.

improve the field-effect mobility and subthreshold swing S.S. due to a reduced trap density and less carrier scattering in the conduction channel. However, the series resistance ef-fect would lead to less drain voltage drop in the conduction channel, resulting in less drain current and lower field-effect mobility . Therefore, the effect of the grain boundary trap density decreasing and the series resistance effect are in competition when the channel length is reduced. In the subthreshold region, a small drain current would not lead to a significant reduction in actual voltage across the channel due to the series resistance, and the grain boundary trap density decrease effect could improve the subthreshold swing S.S. as the channel length is reduced. However, for a high driving current, the series resistance effect would significantly degrade the field-effect mobility as the scaling down of channel length even the grain boundary trap density

Fig. 9. Plot ofln[I =(V 0V )] versus 1=(V 0V ) curves of LTPS-TFTs atV = 1:0 V and high V with channel widthW = 1 m and four channel lengthL = 10; 5; 2; and 1 m.

Fig. 10. Channel lengthL dependence of field-effect mobility  and sub-threshold swing S.S of LTPS-TFTs with channel widthW = 1 m and three gate oxide thickness 50, 32, and 20 nm.

decreased. In order to estimate the series resistance effect of LTPS-TFTs, the modified field-effect mobility ' is defined as follows [17]:

(2)

' ' (3)

' (4)

' (5)

where is the total applied voltage. The voltage drop should occur in the series resistance and conductive channel of TFTs. ' is thus the real applied voltage across the channel of TFTs. About 6.1 k series resistance of device is extracted from drain current relation of gate voltage and channel length [17]. The modified field-effect mobility ' with and without se-ries resistance calibration is shown in Fig. 7. It shows that

Fig. 11. Transfer curve(I -V ) and field-effect mobility  of LTPS-TFTs with 50-nm gate oxide thickness, channel lengthL = 10 m and four channel widthL = 10; 5; 2; and 1 m.

Fig. 12. Field-effect mobility versus channel widthW of LTPS-TFTs with three gate oxide thickness 50, 32, and 20 nm.

the modified field-effect mobility ' is increased with the re-duction in channel length , and the field-effect mobility without calibration shows the 6.1 k series resistance would result in series degradation. As for the narrower channel width m, the transfer curves of LTPS-TFTs with dif-ferent channel are shown in Fig. 8. Comparing to wide channel width m, the grain boundary trap density decreasing effect is more significant as shown in Fig. 9, resulting in that the field-effect mobility exhibiting a slight increase first before it decreases with the reduction of channel length , as shown in Fig. 10. Moreover, the subthreshold swing improve-ment from channel length m to 1 m is also enhanced from V to 0.8 V/decade with the reduction of channel width from m to 1 m. Fig. 11 shows the transfer curves of LTPS-TFTs with different channel width. The channel width dependence of field-effect mobility is shown in Fig. 12. It shows that the field-effect mobility is independent of gate oxide thickness and increases with the reduction in the channel width. As mentioned above, the

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Fig. 13. Plot ofln[I =(V 0 V )] versus 1=(V 0 V ) curves of LTPS-TFTs atV = 1:0 V and high V with channel lengthL = 10 m and four channel widthL = 10; 5; 2; and 1 m.

channel width reduction can decrease the grain boundary trap density in the channel film, as shown in Fig. 13, resulting in higher field-effect mobility . Finally, the impacts of re-ducing gate oxide thickness, channel length and width on LTPS-TFTs are all extracted simultaneously.

IV. CONCLUSION

A comprehensive study of scaling down effects of LTPS-TFTs with various gate oxide thicknesses, channel length and width are studied simultaneously. Gate oxide thickness strongly affects the electrical performance of LTPS-TFTs, including threshold voltage , subthreshold swing S.S., channel length dependence of field-effect mo-bility and subthreshold swing S.S. The thin gate oxide thickness of LTPS-TFTs results in the most stable and superior electrical behavior. In addition, the competition of channel grain boundary trap density effect and series resistance effect is also observed; the different channel width of LTPS-TFTs exhibit slightly different channel length dependence of field-ef-fect mobility .

ACKNOWLEDGMENT

The authors would like to thank the processes support from National Nano Device Labs and the Nano Facility Center of the National Chiao Tung University, Hsinchu, Taiwan.

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William Cheng-Yu Ma was born in Taipei, Taiwan,

in 1980. He received the B.S. degree in Electro-physics from National Chiao-Tung University, Hsinchu, Taiwan, in 2002, and the M.S. and Ph.D. degrees in electronics engineering from National Chiao-Tung University, Hsinchu, Taiwan, in 2004, and 2008, respectively.

In 2009, he had changed his name from Ming-Wen Ma to William Cheng-Yu Ma in 2009. He is currently working on the research and design of 28-nm node CMOS technology. His research interests are the fabrication and characterization of low-temperature polycrystalline thin-film transistor (LTPS-TFT), silicon-on-insulator (SOI) device, metal-gate/high-K (MG/HK) technology, and RF metal–insulator–metal capacitor (MIM).

Tsung-Yu Chiang was born in Yunlin, Taiwan, in

1984. He received the B.S. degree in physics from National Chung Cheng University, Chiayi, Taiwan, in 2006, and is currently working toward the Ph.D. degree in the Department of Electrophysics, National Chiao Tung University, Hsinchu, Taiwan.

His research interest includes the studies of semiconductor device physics, including low-tem-perature polycrystalline-silicon thin-film transistor (LTPS-TFT), metal-gate/high-k technology, strain technique, and nonvolatile Flash memories.

Je-Wei Lin was born in Yilan, Taiwan, in 1981.

He received the B.S. and M.S. degrees from the Department of Electrical Engineering, Chung Hua University, HsinChu, Taiwan, in 2004 and 2007, respectively, and is currently working toward the Ph.D. degree from same university.

His research interest includes the studies of elec-trooptical semiconductor device physics, including high-efficiency monocrystalline silicon solar cells and metal insulator semiconductor solar cells.

Tien-Sheng Chao (SM’01) was born in Penghu,

Taiwan, in 1963. He received the Ph.D. degrees in electronics engineering from National Chiao-Tung University, Hsinchu, Taiwan in 1992.

He joined the National Nano Device Laboratories (NDL) as an associate researcher in July, 1992, and became as a researcher in 1996. He was engaged in developing the thin dielectrics preparations, cleaning processes, and CMOS devices fabrication. Since 2001, he has been with the Department of Electrophysics, National Chiao Tung University, Hsinchu, Taiwan. He has published over than 140 papers in this field.