Investigation on NMOS-based power-rail ESD clamp circuits with gate-driven mechanism in a 0.13-mu m CMOS technology

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Investigation on NMOS-based power-rail ESD clamp circuits with gate-driven

mechanism in a 0.13-

l

m CMOS technology

Shih-Hung Chen

a,b,*

_{, Ming-Dou Ker}

a,c

a

Nanoelectronics and Gigascale Systems Laboratory, Institute of Electronics, National Chiao-Tung University, 1001 Ta-Hsueh Road, Hsinchu, Taiwan

b

Circuit Design Department, SoC Technology Center, Industrial Technology Research Institute, Hsinchu, Taiwan

c

Department of Electronic Engineering, I-Shou University, Kaohsiung, Taiwan

a r t i c l e

i n f o

Article history: Received 17 March 2009

Received in revised form 23 September 2009

Available online 18 February 2010

a b s t r a c t

NMOS-based power-rail ESD clamp circuits with gate-driven mechanism have been widely used to obtain the desired ESD protection capability. All of them are usually based on a similar circuit scheme with mul-tiple-stage inverters to drive the main ESD clamp NMOS transistor with large device dimension. In this work, the designs with 3-stage inverter and 1-stage inverter controlling circuits have been studied to ver-ify the optimal circuit schemes in the NMOS-based power-rail ESD clamp circuits. Besides, the circuit per-formances among the main ESD clamp NMOS transistors drawn in different layout styles cooperated with the controlling circuit of 3-stage inverters or 1-stage inverter are compared. Among the NMOS-based power-rail ESD clamp circuits, an abnormal latch-on event has been observed under the EFT test and fast power-on condition. The root cause of this latch-on failure mechanism has been clearly explained by the emission microscope with InGaAs FPA detector.

1. Introduction

Electro static Discharge (ESD) protection has become a trouble-some task on the reliability of CMOS integrated circuits fabricated in the advanced nanoscale CMOS technology. The power-rail ESD clamp circuit is an efficient design to achieve whole-chip ESD pro-tection in IC products[1–3]. It not only can improve ESD robust-ness of VDD-to-VSS ESD stress, but also can significantly enhance ESD robustness of input/output-to-VDD/VSS and pin-to-pin ESD stresses [2]. Furthermore, to efficiently protect the core circuits realized with much thinner gate oxide in nanoscale CMOS technol-ogy, some studies had reported the efficient power-rail ESD clamp circuits with modified circuit designs[3–6]. All of them were based on the power-rail ESD clamp circuits with gate-driven mechanism which was basically implemented by the RC-based ESD-transient detection circuit with a controlling circuit[1–6], as illustrated in Fig. 1. Besides, those previous works also adopted the power-rail ESD clamp NMOS transistor with no snapback operations to obtain excellent turn-on efficiency. The snapback phenomenon usually occurs in NMOS transistors, npn bipolar transistors, or silicon con-trolled rectifiers (SCRs) under higher voltage and current stress conditions. No snapback means that the huge ESD current was

dis-charged by the channel current of NMOS transistors. Therefore, those NMOS transistors in the power-rail ESD clamp circuits were traditionally drawn with huge channel width of several-thousand micrometer to achieve the required ESD robustness under no snap-back operation. They were often called as Big FET (BFET) in some previous literatures[3–6].

The RC-based ESD-transient detection circuits were used to dis-tinguish ESD-stress conditions from normal circuit operation con-ditions due to the difference in the rise time between these two conditions [1,2]. Then, 3-stage inverters, which were adopted as a function of tapered buffer[7–11], usually performed the control-ling circuit to efﬁciently turn on or turn off the BFET, which has large capacitive load from the NMOS transistor with a huge chan-nel width in power-rail ESD clamp circuit, as shown inFig. 1. The tapered buffer, which is the multiple inverter stages with cascaded arrangement, is constantly applied to drive the large loading capacitance under a desirable propagation delay and power con-sumption [7–9]. However, such design concerns are not always appropriate to the function of the controlling circuits in the power-rail ESD clamp circuits because of two main reasons. First, the controlling circuits are only required to propagate a unity sig-nal, such as logical high or logical low, in order to turn on the main ESD clamp devices under ESD-stress conditions, but they are not required to propagate a dynamic signal or alternating logic under normal circuit operation conditions. Second, the controlling cuits are always biased at the static off state under the normal cir-cuit operation conditions in the power-rail ESD clamp circir-cuits.

* Corresponding author. Address: Rm. 247, Bldg. 14, No. 195, Sec. 4, Chung Hsing Rd., Chutung, Hsinchu 31040, Taiwan, ROC. Tel.: +886 3 591 7017; fax: +886 3 591 2040.

E-mail addresses:[email protected](S.-H. Chen),[email protected](M.-D. Ker).

Microelectronics Reliability 50 (2010) 821–830

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Microelectronics Reliability

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Some basic circuit performances, such as short-circuit dissipation and propagation delay, would not be improved by the controlling circuits with the tapered buffer arrangement. Therefore, the con-trolling circuits with tapered buffer concepts should be unneces-sary and even be unsuitable for power-rail ESD clamp circuits.

The comparison between 1-stage and 3-stage inverters in the controlling circuits has been studied in this work. The circuit per-formances of both controlling circuits in power-rail ESD clamp cir-cuits are measured and compared under ESD-stress conditions and normal circuit operation conditions. On the other hand, the drain-contact-to-poly-gate spacing (D) of the main ESD clamp NMOS transistor has been also split from 0.25

l

m to 2.0

l

m in order to investigate the inﬂuence of this spacing on the ESD protection capability. Through the arranged combinations of different control-ling circuits and main ESD clamp NMOS transistors in different lay-out styles, the inﬂuence can be thoroughly investigated from the characteristic and performance of each power-rail ESD clamp cir-cuit in silicon. Moreover, the impact of the fast power-on applica-tion[5,6]or the transient noise on power/ground lines[12,13]on the power-rail ESD clamp circuits has been also discussed in this work. According to these experimentally measured results, the optimized circuit scheme for controlling circuits and layout style for the main ESD clamp NMOS transistors can be suggested for using in the power-rail ESD clamp circuits.

2. Power-rail ESD clamp circuits with different controlling circuits and layout styles on main ESD clamp NMOS

It has been studied and reported that the RC-time constants of the RC-based ESD-transient detection circuits made an impact on the ESD robustness of the power-rail ESD clamp circuits. In a pre-vious work[14], all main ESD clamp NMOS transistors were drawn as the BFETs with the drain-contact-to-poly-gate spacings from 0.22

l

m to 0.44

l

m and no silicide blocking on the diffusions. The total channel widths of those BFETs were identically 2000

l

m; however, they occupied different silicon areas. Accord-ing to the measured results in that previous work, the ESD robust-ness were not signiﬁcantly improved or enhanced by increasing the RC-time constant from 0.1

l

s to 1.0

l

s. More speciﬁcally, the

longest RC-time constant of 1.0

l

s could slightly induce some deg-radation on ESD robustness of the power-rail ESD clamp circuit. Based on these related measured results in previous research [14], the RC-time constant has been ﬁxed at 0.2

l

s in this work to reduce the occupied silicon area of the resistance and capaci-tance in this testchip.

Both controlling circuits, which are the 1-stage inverter and the 3-stage inverters, are respectively arranged to command the main ESD clamp NMOS transistors with different drain-contact-to-poly-gate spacings. One of the main ESD clamp NMOS transistors has the layout style with minimized drain-contact-to-poly-gate spac-ing (D) and no silicide blockspac-ing (SB) on its diffusion, as shown in Fig. 2a. This NMOS transistor, which is the Big FET (BFET), will be expected to have no snapback operation. However, another one has a totally different layout style with extended drain-contact-to-poly-gate spacing (D) and silicide blocking (SB) on its diffusion,

Fig. 2. The main ESD clamp NMOS transistor has (a) the BFET layout style with the drain-contact-to-poly-gate spacing (D) of 0.25lm and no silicide blocking (SB) on its diffusions, and (b) the standard layout style with the drain-contact-to-poly-gate spacing (D) of 2.0lm and silicide blocking (SB) on its drain-side diffusions. Fig. 1. Typical design scheme for NMOS-based power-rail ESD clamp circuit with

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as shown inFig. 2b. It is a standard ESD clamp NMOS transistor with snapback operation. It has been proven that the parasitic npn bipolar transistor was turned on induce the snapback opera-tion in such ESD clamp NMOS transistor[15,16]. The drain-con-tact-to-poly-gate spacings of the BFET and standard ESD clamp NMOS transistors are 0.25

l

m and 2.0

l

m, respectively. Besides, another different layout style, called as modiﬁed design in this work, has been also implemented in this testchip. The modiﬁed de-signs have the main ESD clamp NMOS transistor with a drain-con-tact-to-poly-gate spacing of 0.75

l

m. Moreover, there are two different main ESD clamp NMOS transistors with or without sili-cide blocking on their drain-side diffusion in modiﬁed designs. Through such splits in layout, the inﬂuences of the drain-side equivalent resistance on circuit performance and ESD robustness can be used to judge the optimal layout style for the main ESD clamp NMOS transistor.

Totally, eight designs of power-rail ESD clamp circuits from the combinations of the main ESD clamp NMOS transistor in different layout styles and the controlling circuit with different inverter stages have been drawn in the testchip for comparison, as shown inTable 1For comparison purpose, the layout areas of the main ESD clamp NMOS transistors among those eight designs are kept the same in layout. Therefore, the total channel width of the stan-dard main ESD clamp NMOS transistor is 624

l

m, whereas that of the BFET is about 2600

l

m. For all modiﬁed designs, the main ESD clamp NMOS transistors have a total channel width of 1144

l

m. Then, the two type controlling circuits implemented by 3-stage inverters and 1-stage inverter also occupied similar layout areas. The device sizes (W/L) of PMOS and NMOS transistors are 444/ 0.18

l

m and 62/0.18

l

m in the design with 1-stage inverter, respectively. They are 14/0.18

l

m (70/0.18

l

m and 360/0.18

l

m) and 2/0.18

l

m (10/0.18

l

m and 50/0.18

l

m) in 1st-stage inverter (2nd-stage and 3rd-stage inverters) of the design with 3-stage inverters, respectively. This testchip has been fabricated in a 0.13-

l

m 1.2-V CMOS process.

3. Experimental results in component-level tests 3.1. Turn-on veriﬁcation under ESD-like stress condition

To observe the turn-on efﬁciency among the different power-rail ESD clamp circuits, a 2.4-V ESD-like voltage pulse with 2-nano-seconds (ns) rise time is applied on the VDD terminal with VSS terminal grounded in each circuit. The voltage pulse with a rise time of 2 ns and duration of 600 ns generated from a pulse gener-ator is used to simulate the fast rising edge of HBM ESD event[17]. The sharp-rising edge of the ESD-like voltage pulse will be detected by the RC-based ESD-transient detection circuit and then to turn on the main ESD clamp NMOS transistor. When the main ESD clamp NMOS is turned on, the voltage waveform on VDD node will be clamped as the measured results shown inFig. 3a and b. Stan-dard1 and BFET1, both of which have 1-stage inverter in the

con-trolling circuits, presented similar voltage waveforms under 2.4-V ESD-like voltage pulses. Besides, Standard2 clamped the over-shoot voltage pulses to a lower voltage level during the ﬁrst 300 ns of the ESD-like voltage pulses. However, the BFET2 per-forms an excellent ability to clamp the overshoot voltage pulse to a much lower voltage level, as shown inFig. 3a. On the other hand, the inﬂuences of drain-side silicide blacking on turn-on behaviors of the power-rail ESD clamp circuits have been mea-sured inFig. 3b. Under the same drain-contact-to-poly-gate spac-ings of 0.75

l

m, Modified3 exhibits the best turn-on efficiency among other designs. Besides, the turn-on efficiency of Modified4 is higher than that of Modified1 and Modified2 during the first 350-ns pulse duration. According to the measured results, the controlling circuit with 3-stage inverters seems to be an optimal

Table 1

Eight designs of the power-rail ESD clamp circuits veriﬁed in this work.

Design Controlling circuit Main ESD clamp NMOS

Drain-contact-to-poly-gate spacing (D) and total channel width (W) Silicide blocking (SB)

Standard1 1-Stage inverter D = 2.0lm and W = 624lm Yes

Standard2 3-Stage inverters D = 2.0lm and W = 624lm Yes

Modiﬁed1 1-Stage inverter D = 0.75lm and W = 1144lm No

Modiﬁed2 1-Stage inverter D = 0.75lm and W = 1144lm Yes

Modiﬁed3 3-Stage inverters D = 0.75lm and W = 1144lm No

Modiﬁed4 3-Stage inverters D = 0.75lm and W = 1144lm Yes

BFET1 1-Stage inverter D = 0.25lm and W = 2600lm No

BFET2 3-Stage inverters D = 0.25lm and W = 2600lm No

Fig. 3. The measured voltage waveforms of (a) Standard1, Standard2, BFET1, and BFET2, and of (b) Modified1, Modified2, Modified3, and Modified4, under 2.4-V ESD-like voltage pulses with 2-ns rise time.

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candidate to implement the main ESD clamp NMOS transistor with BFET layout style in the power-rail ESD clamp circuit. The control-ling circuit would hold a dominant factor on the turn-on behaviors of the power-rail ESD clamp circuit.

3.2. TLP I–V characteristics and HBM ESD robustness

The Transmission Line Pulse (TLP)[18]measured I–V character-istics of the power-rail ESD clamp circuits are shown inFigs. 4a, b and 5a, b. This TLP system has a 100-ns pulse width and 10-ns rise time. InFig. 4a, the TLP I–V curves can be simply discriminated be-tween the main ESD clamp NMOS transistors with standard or BFET layout styles. Although the second breakdown currents (It2) of these four designs can achieve over 6 A, the difference of on resistance (Ron) clearly distinguished the designs with standard main ESD clamp NMOS transistor from those with BFET. Due to smaller total channel widths in Standard1 and Standard2, their clamp voltage (Vclamp) and Ron are signiﬁcation higher than those of BFET1 and BFET2. Higher Vclamp and Ron in Standard1 and Standard2 easily induced some damages to the internal circuits. In addition, the TLP I–V curves of Standard1 and Standard2 pre-sented obvious two-stage Ron in Fig. 4a. The phenomenon of two-stage Ron can be attributed to the changes of the discharging paths. The currents were conducted through the channel of the main ESD clamp NMOS transistor under the low-current region, and they would be discharged by the parasitic npn bipolar transis-tor of the main ESD clamp NMOS transistransis-tor[19].

Moreover, the controlling circuits with 3-stage inverters can en-hance the turn-on efficiency, such as lower trigger voltage (Vt1) and smaller on resistance, especially under the low-current region in both standard and BFET designs, as shown inFig. 4b. It was ever reported that the higher Vt1 and insufficient turn-on duration in the ESD devices will induce some damages to interface circuits [20]. The enhancement of the turn-on efficiency is more empha-sized on the design with the controlling circuit of 3-stage inverter cooperated with BFET. However, the influence of the different con-trolling circuits with 3-stage inverters and 1-stage inverter on the turn-on efficiency is gradually indistinct under the high current re-gion. When the measured current is over 2.5 A, no obvious differ-ence of Vclamp between BFET1 and BFET2, both of which have the total channel widths of 2600

l

m, is observed inFig. 4a. The phe-nomenon can be also attributed to the changes of the discharging paths. Under such high current region, the huge current can not be totally discharged by the channel of the main ESD clamp NMOS transistor. The parasitic npn bipolar transistor would be triggered on discharge huge current. Therefore, the gate-driven enhance-ment by the 3-stage inverters will disappear under the high cur-rent region. The similar measured results also can be observed in Modified1, Modified2, Modified3, and Modified4. Fig. 5a and b present the TLP I–V curves of these modified designs. These four TLP I–V curves have the similar trends, especially in the high cur-rent range. The trigger voltages of Modified3 and Modified4 are lower than those of Modified1 and Modified2. The second break-down currents (It2) of the modified designs with silicide blocking (Modified2 and Modified4) are higher than those without silicide

Fig. 4. (a) The TLP I–V curves of Standard1, Standard2, BFET1, and BFET2. (b) The

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blocking (Modified1 and Modified3), as shown in the insert of Fig. 5a. The influence of the drain-side silicide blocking on the Ron and Vclamp is not obvious, as illustrated in Fig. 5a and b. According to the TLP measured results, the design scheme of con-trolling circuit would affect the trigger voltage of the power-rail ESD clamp circuit. However, the on resistance and Vclamp would be dominated by the drain-side layout style in the main ESD clamp NMOS transistor.

The second breakdown currents and HBM ESD robustness of the eight different power-rail ESD clamp circuits are listed inTable 2. The power-rail ESD clamp circuit with design of BFET2 sustains the highest HBM ESD stress of 7 kV. However, the ESD robustness of Standard2 is below 6 kV. The four modiﬁed designs have the similar ESD robustness from 5.5 kV to 6.0 kV. The ESD robustness of these four designs do not have signiﬁcant enhancement by depositing silicide blocking oxide layer on their drain-side diffu-sions of the main ESD clamp NMOS transistors or by adopting 3-stage inverters in the controlling circuit. A faint relation between the ESD robustness and the controlling circuits (or the layout style of the main ESD clamp NMOS transistor) is summarized inTable 2. The 3-stage inverters in controlling circuit could be suitable for the main ESD clamp NMOS transistor without silicide blocking on its diffusion. Such NMOS transistor has a lower parasitic resistance on its surface channel. But, the controlling circuit with 3-stage inverters would induce some degradation on ESD robustness of the designs with drain-side silicide blocking in the main ESD clamp NMOS transistor. Therefore, based on the measured results of the TLP I–V characteristics and HBM ESD robustness, the 3-stage inverters in controlling circuit did not have obvious improvement for the power-rail ESD clamp circuits in nanoscale CMOS technology.

3.3. Power-on condition and normal circuit operation condition In general, the normal VDD power-on voltage waveform of CMOS ICs has a rise time in the order of milli-second (ms). Due to such a slow rise time in normal power-on conditions, the ESD-transient detection circuit with a RC-time constant of

l

s can dis-tinguish the power-on signal to keep the main ESD clamp NMOS transistor off. All of the power-rail ESD clamp circuits studied in this work can successfully achieve this desired task under normal power-on conditions. However, the power-rail ESD clamp circuits with RC-based ESD-transient detection circuits were easily mis-triggered to cause themselves into a ‘‘latch-on” state, which the po-tential on VDD node will be continuously clamped at a lower volt-age, under some abnormal fast power-on conditions [5,6] or transient noise on VDD power lines[12,13]. In this work, the eight different power-rail ESD clamp circuits were veriﬁed by a 1.2-V voltage pulse with 100-ns rise time, which is used to simulate the abnormal fast power-on condition, to investigate their immu-nities from the mis-trigger and latch-on state. The measured re-sults are respectively shown inFigs. 6 and 7.

Unfortunately, the power-rail ESD clamp circuits with 3-stage inverters in controlling circuit present the worse immunity against mis-trigger under the 1.2-V fast power-on test conditions. BFET2 will be mis-triggered on enter latch-on state under the 1.2-V fast power-on test condition. The voltage waveform is clamped at a very low voltage level around 0.3–0.6 V, as illustrated in Fig. 6. Such phenomenon is much harmful for the applications of the power-rail ESD clamp circuits in real IC products. Besides, Modi-fied3 also presents a similar measured result to that of BFET2. Stan-dard2 and Modified4, both of which have the silicide blocking on their drain sides, will be mis-triggered at the first 250 ns and first

Table 2

HBM ESD robustness of the eight power-rail ESD clamp circuits.

Designs HBM Second breakdown current (It2) (A)

Positive (kV) Negative (kV) Standard1 6.5 >8.0 >6 Standard2 5.5 >8.0 >6 Modified1 5.5 >8.0 5.4 Modified2 6.0 >8.0 >6 Modified3 6.0 >8.0 5.2 Modified4 5.5 >8.0 >6 BFET1 6.5 >8.0 >6 BFET2 7.0 >8.0 >6

Fig. 6. The measured voltage waveforms of Standard1, Standard2, BFET1, and BFET2 under the 1.2-V fast power-on condition with 100-ns rise time.

Fig. 7. The measured voltage waveforms of Modified1, Modified2, Modified3, and Modified4 under the 1.2-V fast power-on condition with 100-ns rise time. S.-H. Chen, M.-D. Ker / Microelectronics Reliability 50 (2010) 821–830 825

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420 ns, respectively, under the 1.2-V fast power-on test condition with 100-ns rise time. However, all of designs with 1-stage inverter in the controlling circuit, such as Standard1, BFET1, Modiﬁed1, and Modiﬁed2, exhibit the higher mis-trigger immunity under this 1.2-V fast power-on test condition. Their voltage waveforms can follow up with the fast power-on voltage waveforms, as presented in Figs. 6 and 7. Although the 3-stage inverters for controlling circuit would enhance the gate-driven ability to slightly increase the ESD robustness and decrease Vclamp (and Ron), they will dramatically degrade the immunity against mis-trigger and latch-on issues un-der the fast power-on condition. Based on the aforementioned re-sults, the controlling circuits with 1-stage inverter should be the optimal choice among the power-rail ESD clamp circuits with RC-based ESD-transient detection circuit.

4. Experimental results in system-level test

The reliability of microelectronic products has been put more emphasis on the electromagnetic compatibility (EMC). In order to avoid the occurrence of the malfunction and mis-trigger during normal system operation conditions, the on-chip ESD protection circuits also has been required to meet the EMC regulation. For power-rail ESD clamp circuits, the impact of the transient noise coupled from microelectronic system on the power (or ground) line has attracted more attentions. The transient noise could in-duce some power-rail ESD clamp circuits into serious latch-on fail-ure according to the previous studies [12,13]. In this work, the electrical fast transient (EFT) test [21] has been applied on the eight different power-rail ESD clamp circuits to judge their immu-nities against fast transient noise on their power lines. The EFT voltage waveforms consist of many bursts with 15-ms duration and these bursts are repeated every 300 ms, as shown inFig. 8a. Besides, each voltage pulse in the burst has a rise time of 5 ns and a pulse width of 50 ns, as illustrated inFig. 8b. Moreover, be-cause the minimum EFT voltage waveforms of 200 V provided by

EFT generator would easily destroy the on-chip devices in nano-scale CMOS technology, the EFT voltage waveforms were decayed by a 100-time attenuator before they were directly applied to the VDD terminals of the power-rail ESD clamp circuits. The measure-ment setup for the EFT test was demonstrated inFig. 9. Besides monitoring the inﬂuence of voltage waveforms on the VDD termi-nals, the abnormal variations in currents from VDD to VSS also have been observed through the current probe.

Fig. 10a shows the measured results of BFET1 and BFET2 under the 4-V EFT test on the VDD terminals. The overshooting voltages on the VDD nodes can be effectively clamped by these two power-rail ESD clamp circuits. BFET1 exhibits a smooth waveform, only decaying the voltage amplitude on the VDD terminal, whereas BFET2 presents a rough waveform during the period of the EFT exe-cution. Besides, the measured results of Standard1 and Standard2 have been illustrated inFig. 10b. The overshooting voltage on the VDD nodes also can be clamped by the designs with the standard ESD clamp NMOS transistor (D = 2.0

l

m with SB). Standard1 and Standard2 show similar waveforms and the clamp voltage of Stan-dard2 is slightly lower than that of Standard1. In addition, the

cur-Fig. 8. Speciﬁed electrical fast transient (EFT) waveforms of (a) burst, and (b) single pulse, with a repetition frequency of 5 kHz.

Fig. 9. Measurement setup for electrical fast transient (EFT) test on the DUT with the VDD bias of 1.2 V.

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rent waveforms of these four designs only vibrated during the per-iod of the EFT execution. No abnormal current from VDD to VSS was observed after the 4-V EFT stresses. With the 9.5-V EFT voltage stress on the VDD terminals, the measured results are presented in Fig. 11a and b. All of the designs still can efﬁciently clamp the over-shooting voltage pulses on the VDD nodes during the EFT stresses. However, after the duration of the EFT voltage pulse, the voltage potential on VDD terminal is not successfully recovered to the nor-mal operation voltage of 1.2 V in BFET2, as clearly shown in Fig. 11b. Moreover, the current waveform of the BFET2 will drasti-cally rise and ﬁnally hold at around 200 mA. Such phenomenon could be attributed to the main ESD clamp NMOS transistor is still kept at on state after 9.5-V EFT stress, which is the occurrence of latch-on event. The further explanation of this latch-on mechanism will be analyzed and discussed in the next paragraphs. In contrast, the voltage waveforms of other designs can be quickly recovered to 1.2 V after the duration of the EFT voltage pulse and no abnormal current from VDD to VSS was observed after 9.5-V EFT stress. According to the measured results inFig. 11b, the recovery period of Standard2 is larger than that of Standard1. Standard2 would in-duce an irregular overshooting voltage pulse at the end of the duration of the EFT voltage pulse. Its current waveform also man-ifests the irregular transient under this duration. In a nutshell, the RC-based ESD-transient detection circuit with the controlling cir-cuit of 3-stage inverters and the main ESD clamp NMOS transistor with BFET (D = 0.25

l

m without SB) layout style are unreliable to

be used as the power-rail ESD clamp circuit due to the mis-trigger and latch-on concern.

5. Failure analysis and latch-on mechanism 5.1. Failure analysis

According to the measured results of the EFT test and fast power-on condition, BFET2 would induce the latch-on phenome-non if the fast transient noises applied on the VDD terminal. The potential on the VDD node will be clamped into a lower voltage le-vel or the huge conducting current from VDD to VSS will be ob-served, as shown in Figs. 6 and 11a,b. However, such power-rail ESD clamp circuit with RC-based ESD-transient detection circuit should maintain in a high impedance state from VDD to VSS after the turn-on duration of main ESD clamp NMOS transistor. Stan-dard2 clearly presents this characteristic, as shown inFig. 6. But, the voltage waveforms of BFET2 are always clamped to a lower voltage potential under the fast power-on condition. There is an abnormal mechanism to contribute a positive feedback path that in turn triggers the occurrence of the latch-on event. In order to ob-serve the root cause of this latch-on mechanism, the failure analy-sis has been executed by the emission microscope with InGaAs focal plane arrays (FPA) detector[22], which has an excellent capa-bility to capture the photon emission of wavelength range from

Fig. 10. Under the 4-V EFT voltage pulse, the measured voltage waveforms of (a) BFET1 and BFET2, and (b) Standard1 and Standard2.

Fig. 11. Under the 9.5-V EFT voltage pulse, the measured voltage waveforms of (a) BFET1 and BFET2, and (b) Standard1 and Standard2.

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800 nm to 1700 nm. This failure analysis equipment is suitable for the abnormal location with very slight photon emissions[22–24] because of the higher quantum efﬁciency.

Fig. 12a–c illustrated the results of the failure analysis after the EFT test. According to the images inFig. 12a and b, the main ESD clamp NMOS transistor with BFET layout style is turned on into the latch-on status after the 9.5-V EFT voltage stress because the PMOS transistor in the 3rd-stage inverter and the NMOS transistor in the 2nd-stage inverter are also in the on state. The PMOS tran-sistor in the 3rd-stage inverter and the NMOS trantran-sistor in the 2nd-stage inverter kept in the on state could be attributed to volt-age drop across the n-well resistance of the RC-based ESD-tran-sient detection circuit. The failure mechanism of this latch-on event was illustrated inFig. 12d. In general, the n-well resistance is usually regarded as a common choice in such RC-based ESD-transient detection circuit to obtain an adequate resistance and a sufﬁcient RC-time delay. However, based on the previous studies [25,26], a few electrons would be captured by this n-well resis-tance since this n-well resisresis-tance could be performed as the guard ring of the minority to capture the minority carriers (electrons) in the p-substrate, as shown inFig. 12d. The slight hot spots on the n-well resistance have been observed in Fig. 12c. In the layout, although the n-well resistance has been surrounded by the

N+/n-well minority guard rings connected to VDD, some escaped elec-trons still were captured by the n-well resistance. It induces some voltage drop across the n-well resistance because the electrons were captured and conducted by this n-well resistance. Due to the slight voltage drop across the n-well resistance, the PMOS tran-sistor in 1st-stage inverter can be slightly turned on. Then, through the ampliﬁcation of the 1st-stage inverter, the NMOS transistor in the 2nd-stage inverter and the PMOS transistor in the 3rd-stage in-verter are thoroughly in the on state, as shown inFig. 12b with bright hot spots.

5.2. Discussion on the latch-on mechanism

According to the measured results in the power-on and FET tests, this latch-on event of BFET2 relied on a mis-trigger status of the main ESD clamp NMOS transistor which was induced by a sufﬁcient transient noise (or power-on signal). For example, the latch-on event was not observed under the power-on condition with ms-order rise time and under the 4-V EFT stress. Under the sufﬁcient transient noise (or power-on signal), such as 9.5-V EFT test (or 100-ns power-on signal), the main ESD clamp NMOS tran-sistor was initially into on state and conducted huge current from VDD to VSS. Then, a few escaped electrons were captured by the

Fig. 12. Through the emission microscope with InGaAs FPA detector. (a) The abnormal emission spots after the EFT test are located at the NMOS transistor of the 2-stage inverter, the PMOS transistor of the 3-stage inverter, and main ESD clamp NMOS transistor. (b) The zoomed-in view around the controlling circuit and the RC-based ESD-transient detection circuit. (c) The emission image is only located at the n-well resistance of the RC-based ESD-ESD-transient detection circuit. (d) The failure mechanism of this latch-on event.

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n-well resistance to induce the voltage drop across the n-well resistance. Through the ampliﬁcation gain of the 3-stage inverters, the main ESD clamp NMOS transistor was kept at the further on state. Such on state main ESD clamp NMOS transistor would also conduct huge current and unavoidably induce the voltage drop across the n-well resistance. Finally, the main ESD clamp NMOS transistor in BFET2 was continuously held at the latch-on state. Therefore, the latch-on mechanism consists of three essential steps which are initial mis-trigger of main ESD clamp NMOS transistor, inducement of voltage drop across the n-well resistance, and ampliﬁcation gain of 3-stage inverters.

The latch-on phenomenon was not observed in the designs with 1-stage inverter, such as BFET1 and Standard1, since they have the higher immunities against mis-trigger to avoid the main ESD clamp NMOS transistor entering into on state. More impor-tantly, they lack the ampliﬁcation gain of multi-stage inverters. Even though their main ESD clamp NMOS transistors were mis-triggered and into a short-period on state under large transient stresses, they still could not be held at latch-on state. On the other hand, because Standard2 with the standard ESD clamp NMOS transistor (D = 2.0

l

m with SB) has a smaller channel width to generate less channel conduction current and substrate injection current, the deficient electrons can not induce adequate voltage drop across the n-well resistance. Although it suffered from the mis-trigger and possessed the amplification gain of 3-stage inverter, the insufficient voltage drop could not hold itself into the latch-on state. For the power-rail ESD clamp circuits in modified designs, the latch-on event can be only observed in Modified3 since it can exactly satisfy the three essential steps of the latch-on mechanism. However, the latch-on event was not observed in Modified1, Modified2, and Modified4. According to the further measured results, besides BFET2 and Modified3, the latch-on phenomenon was not observed in the other designs under the 44-V EFT stresses (44 V is the maximum value in the EFT measurement setup shown inFig. 9).

In addition, the latch-on event in BFET2 or Modified3 would vanish by some modifications of layout style and n-well resistance. Consequently in layout, the width of N+/n-well minority guard rings connected to VDD and the distance between the n-well resis-tance and the main ESD clamp NMOS transistor should be further enlarged to prevent the threat of latch-on event under the EFT test and fast power-on condition. However, such adjustments would extend some layout areas of the power-rail ESD clamp circuit in the standard I/O cell library. Another approach is to replace the n-well resistance by poly resistance. Since the poly resistance is thoroughly separated from the silicon substrate, the poly resis-tance would not capture the escaped electrons to induce the volt-age drop across itself. This approach would successfully conquer the latch-on failure in the BFET2 and Modified3. However, based on the related studies on the power-rail ESD clamp circuits, the 3-stage inverters in controlling circuit would be susceptible to the transient signal on VDD node. Although such design could en-hance the turn-on efficiency of main ESD clamp NMOS transistor under ESD stresses, it would also suffer from the mis-trigger under the transient noise (or power-on signal). More specifically, the immunity level against mis-trigger in the design with 1-stage in-verter is far higher than that in the design with multi-stage invert-ers. Most importantly, the power-rail ESD clamp circuit with 1-stage inverter also possesses acceptable turn-on efficiency, clamp ability, and ESD robustness.

6. Conclusion

The designs with controlling circuits of 3-stage inverters and 1-stage inverter have been studied to verify the optimal circuit

schemes in NMOS-based power-rail ESD clamp circuits. In addi-tion, the circuit performance among the four different main ESD clamp NMOS transistors drawn with different drain-contact-to-poly-gate spacings and co-designed with different inverter stages in the controlling circuits are compared. According to the experi-ments and analyses, the 3-stage inverters for controlling circuit and BFET layout style for the main ESD clamp NMOS transistor can slightly increase the ESD robustness, but they will dramatically degrade the immunity against mis-trigger and latch-on issues un-der the EFT test and fast power-on condition. The 1-stage inverter should be an appropriate and reliable candidate for the controlling circuit in the power-rail ESD clamp circuits. Finally, the latch-on phenomenon has been successfully observed by the emission microscope with InGaAs FPA detector. The root cause to induce such failure can be attributed to the abnormal mechanism of the voltage drop across the n-well resistance after the EFT test. Acknowledgement

This work was supported by SoC Technology Center, Industrial Technology Research Institute, Hsinchu, Taiwan.

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