Digital Object Identifier 10.1109/JEDS.2016.2594837
High Performance Metal-Gate/High-
κ GaN
MOSFET With Good Reliability for Both Logic
and Power Applications
SHIH-HAN YI1, DUN-BAO RUAN2, SHAOYAN DI3, XIAOYAN LIU3, YUNG HSIEN WU1, AND ALBERT CHIN2(Fellow, IEEE)
1 Department of Engineering and System Science, National Tsing Hua University, Hsinchu 300, Taiwan 2 Department of Electronics Engineering, National Chiao Tung University, Hsinchu 300, Taiwan
3 Key Laboratory of Microelectronic Devices and Circuits, Institute of Microelectronics, Peking University, Beijing 100871, China CORRESPONDING AUTHOR: A. CHIN (e-mail: albert_achin@hotmail.com)
This work was supported by the Ministry of Science and Technology of Taiwan.
ABSTRACT The gate-recessed GaN MOSFET on a Si substrate is demonstrated to achieve a record highest normalized transistor current (μCox) of 335 μA/V2 (410 mA/mm at LG= 5 μm and only VG= 4 V),
ION/IOFF of 9 orders of magnitude, small 79 mV/dec sub-threshold slope, a low oxide/GaN interface
trap density of 1.2 × 1010 eV−1/cm2, a low on-resistance of 17.0-mm, a high breakdown voltage of 720–970 V, and excellent reliability of only 40 mV VT after 175 ◦C 1000 s stress at maximum drive current. Such excellent device integrities are due to the high-κ gate dielectric and the high conduction band offset (EC) of SiO2/GaN. From the calculation results of self-consistent Schrödinger and Poisson equations, the good reliability of GaN MOSFET is related to the confined carrier density within the GaN channel, which is in sharp contrast to the strong wave-function penetration into the high-trap density AlGaN barrier in the AlGaN/GaN HEMT.
INDEX TERMS GaN, MOSFET, high-κ, reliability, interface.
I. INTRODUCTION
The ideal transistor requires low off-state current (IOFF) to save power, high on-current (ION) to increase the cir-cuit speed, small turn-on sub-threshold swing (SS) to lower switching power, small supply voltage (VDD) for low power
operation, versatile high VDDfor power electronics and
com-munication applications, and good reliability. To reach these goals simultaneously, both high mobility and wide energy-bandgap materials are the key solution [1]. Besides, the wide bandgap channel MOSFET has new application for logic CMOS, because it can lower the increased IOFF in the highly scaled deep X-nm FinFET by quantum-mechanical direct tunneling [1].
Among available materials, the GaN is one of the ideal candidates with the merits of high mobility, high saturation velocity, and high breakdown field [1]–[17]. Thus, excellent RF power performance has been realized by AlGaN/GaN HEMT [14]–[17]. Yet the GaN MOSFET [1]–[13] has the positive threshold voltage (VT) and lower leakage current
than HEMT, which is more preferable for system application. Besides, the AlGaN barrier in AlGaN/GaN HEMT is difficult to scale down due to the gate leakage current, which lim-its further improvement of gate capacitance and transistor’s drive current.
Previously, using a high-κ gate dielectric, we reported high ION and reasonable breakdown voltage (VBD) in
gate-recessed GaN MOSFET [11]. However, the very poor IOFF and SS are the major drawbacks. In this paper, we report a normally-off gate-recessed GaN MOSFET on Si sub-strate, using the HfAlO/SiO2 gate dielectric. In addition to the reached highest normalized drive current (ION,nor) of 335 μA/V2, 109 ION/IOFF, small SS of 79 mV/dec,
a low oxide/GaN interface trap density (Dit) of 1.2 × 1010
eV−1/cm2, a positive VT of 0.55 V, and a high VBD of
720∼970 V were achieved simultaneously. Besides, excel-lent reliability of only 40 mVΔVTwas measured after 175◦C 1000 sec stress at the maximum drive current. The excellent reliability is further supported by the quantum-mechanical
2168-6734 c 2016 IEEE. Translations and content mining are permitted for academic research only. Personal use is also permitted, but republication/redistribution requires IEEE permission.
simulation, where the electron wave-function is confined in GaN channel and quite different from the severe wave-function penetration into the AlGaN barrier in a HEMT. This device has steep SS comparable with metal-gate/high-κ Si MOSFET, with much better ION/IOFFand much higher VBD.
II. EXPERIMENTS
The device structure in Fig. 1 has a low-temperature grown AlGaN buffer on (111) Si wafer, a 1-μm GaN active layer, a 30-nm AlGaN barrier, and a 2-nm GaN. A thin 2.5-nm thick AlN etching stop layer was inserted in AlGaN barrier to improve the etching selectivity [13], [18]. Then mesa iso-lation and gate region were recess etched by using BCl3/Cl2 RIE. A thin 3-nm thick AlGaN layer beneath the AlN layer was used to prevent RIE damage to GaN channel. The gate dielectric of 1-nm SiO2and 5-nm high-κ HfAlO were formed by ALD [19]–[23]. Then the gate dielectric was annealed at 400 ◦C for 5 min under oxygen ambient, to improve the quality of gate oxide and oxide/GaN interface [20]–[23]. In comparison with previous PVD-deposited SiO2, the in-situ formed SiO2 shows much improved interface trap density. The interfacial SiO2not only lowers the interface reaction but also increases the oxide/GaN barrier height [11], [12], [23]. After opening contact window, the ohmic contacts were formed by Ti/Al/Ti/Au deposition and rapid thermal anneal-ing (RTA) at 850 ◦C for 30 sec in a nitrogen ambient. Then high work-function Pt/Au was deposited and patterned to form the metal-gate with a size of 5-μm × 100-μm. An asymmetric drain and source was used to improve the VBD [11], [24]. For comparison, the control AlGaN/GaN
HEMT devices, without the AlN layer, were also made. The
C−V data were measured by using Agilent E4980A at a step
voltage of 0.2 V and sweep time of 110 to 88 ms.
FIGURE 1. The schematic device structure of gate-recessed metal-gate/ high-κ GaN MOSFET.
III. RESULTS AND DISCUSSION
The unique feature of GaN MOSFET for logic application is its large bandgap that increases the quantum-mechanical tunneling barrier height from source to drain [1]. As the FinFET scales to deep X-nm region, the IOFF is limited by direct tunneling current density (JDT) under electrical
channel length, without considering the drain depletion. The
JDT can be approximately expressed as [1], [25]:
JDT = BE2 φb 1−√1− qEtb/φb 2 × exp −C √ m∗φb3/2 E 1− 1−qEtb φb 3/2 (1) The B and C are the constant; φb, E, tb, and m∗ are the tunneling barrier height, electric field, thickness, and effective mass, respectively. The conventional method to lower the JDT is to decrease the tunneling E field, where the lowered drain current (ID) can be compen-sated by the high mobility channel. Unfortunately, the high mobility Ge [23] and InGaAs has much smaller bandgap and φb than Si that increase JDT exponentially. The better method is to increase φb, decrease E field, and use high mobility channel at the same time, which can be realized by using high-mobility wide-bandgap material such as GaN.
Fig. 2 plots the φb dependence on JDT for Si and GaN MOSFET with a 7 nm electrical channel length. The JDT can be lowered by increasing theφb using highly p+
chan-nel doping, where the maximum φb is close to bandgap
energy. However, the random dopant variation is a severe issue in such small dimension. To avoid this problem, the channel doping can be lowered under the fully depleted condition. Unfortunately, the maximumφbdecreases to half
of the bandgap energy that increases the JDT exponentially. Besides, the drain-induced barrier lowering (DIBL) will also lower theφb. The source-drain dopant diffusion into
chan-nel will further decrease the electrical tbwith an exponential
dependence on JDT. As shown in Fig. 2, the JDT can be low-ered by several orders of magnitude if the Si is replaced by GaN. Nevertheless, the lacking of high performance GaN MOSFET on Si substrate is the major challenge for this technology.
FIGURE 2. JDTversusφbfor Si and GaN MOSFET with a 7-nm electrical
channel length. Theφbof Eg, Eg/2, and Eg/2-0.1 eV is related to highly p+ channel doping, fully depleted channel, and further 0.1 V DIBL lowering, respectively.
FIGURE 3. (a) ID− VDand (b) ID− VGand IG− VGcharacteristics of
gate-recessed metal-gate/high-κ GaN MOSFETs; (c) ID− VDand (d) ID− VG
characteristics of AlGaN/GaN HEMT with the similar epitaxial material structure but without the extra AlN layer.
Figs. 3(a) and 3(b) show the ID − VD and ID − VG data of gate-recessed metal-gate/high-κ GaN MOSFETs, respectively. The measured gate current (IG) is orders of
magnitude lower than ID. The high-κ MOSFET has a very high ION of 410 mA/mm at LG = 5 μm and VG = 4 V,
or record highest ION,nor of 335 μA/V2, a small Ron of 17-mm, a very low SS of only 79 mV/dec, an ION/IOFF
of 109, and a positive VTof 0.55 V. The ION,noris normalized by gate size and gate overdrive of VG− VT:
ION,nor= ION∗ (2LG/WG) / (VG− VT)2= μCox (2)
The LG, WG, VG, Cox, and μ are the gate length, width,
voltage, gate capacitance, and mobility, respectively. For low-power logic CMOS application, the steep SS, comparable with metal-gate/high-κ Si MOSFET [19], is essential to turn on the transistor fast; the even better ION/IOFFor IOFFthan Si MOSFET is vital to improve the leakage power consumption. For power application, the high ION is important to improve the power density, chip size and cost of power module for system application [24]. The low VT is required to integrate with the low VDD of Si sub-μm CMOS control IC [11].
For comparison, the ID−VDand ID−VGcharacteristics of AlGaN/GaN HEMT were also shown in Figs. 3(c) and 3(d), respectively. Here the HEMT has the similar epitaxial mate-rial structure with the gate-recessed GaN MOSFET but without the extra AlN layer. The AlGaN/GaN HEMT has a standard device performance of−3 V VT, 115 mV/dec SS, and 10−4mA/mm IOFFbut are significantly worse than those of MOSFET. It is important to notice that the ION,nor of control AlGaN/GaN HEMT is comparable with or slightly better than the published data in [14]–[17]. It is essential to notice that the battery in mobile communication only pro-vides a positive voltage and requires extra circuit to generate the negative VGbias. Although the high mobility is the merit of HEMT, the gate-recessed MOSFET has 5 times higher
ION,nor than that of HEMT. Thus, both gate capacitance (Cox = ε0κ/t) and mobility at high VG, or high effective
field (Eeff), should be considered to reach the high ION,nor. Besides, the mobility in a transistor decreases rapidly with increasing VG and Eeff [19]–[23], and therefore the HEMT mobility operated at high VG is much lower than the Hall
mobility measured at a low electric field. The small Cox of
thick AlGaN gate dielectric in HEMT is another limiting factor to cause the low ION,nor.
Figs. 4(a) and 4(b) show the Gm − VG characteris-tics of gate-recessed metal-gate/high-κ GaN MOSFETs and AlGaN/GaN HEMT, respectively. The Gmdata were obtained from the ID− VG curves of Figs. 3(b) and 3(d). For gate-recessed metal-gate/high-κ GaN MOSFET, the Gmincreases with increasing VG that is typical for MOSFET device. In contrast, the Gm of AlGaN/GaN HEMT increases ini-tially with increasing VG but gradually decreases at higher
VG values, which is due to the small AlGaN/GaN bar-rier to cause carbar-rier leakage. The peak Gm values are 112 and 25 mS/mm for metal-gate/high-κ GaN MOSFET and AlGaN/GaN HEMT, respectively. The very high Gm is the merit of metal-gate/high-κ MOSFET as compared with HEMT.
FIGURE 4. Gm− VGcharacteristics of (a) gate-recessed metal-gate/high-κ
GaN MOSFETs, and (b) AlGaN/GaN HEMT without the extra AlN layer.
FIGURE 5. The RIE etching depth as a function of etching time of the AlGaN/GaN HEMT structure.
One reason to reach the excellent IOFF compared with previous gate-recessed GaN MOSFET [11] is due to the good RIE etching controllability. The gate over recess can cause device failure, while under recess leads to negative
VT and high IOFF. Fig. 5 shows the etching depth versus time. The etching rate is slower when the AlGaN is etched to AlN. However, the AlN thickness is limited to 3 nm, because the thick AlN will cause the high strain, interface
FIGURE 6. Frequency dependent (a) CG− VGcharacteristics and (b) Dit and Gp/ω of gate-recessed metal-gate/high-κ GaN MOSFETs.
roughness, and poor mobility. Careful RIE etching control is still needed even with AlN layer.
We further measured the frequency ( f )-dependent CG−VG characteristics of GaN MOSFET. As shown in Fig. 6(a), little change of CG−VGslopes from depletion to accumulation can be found as increasing f from 3 kHz to 1 MHz. These results indicate the good oxide/GaN interface. The C− V curves of metal-gate/high-κ GaN MOSFETs, swept between −4 and 7 V and measured at 3 kHz to 1 MHz, has small hysteresis of 0.25∼0.08 V, indicating the good high-κ dielectric quality. We also used the conductance (Gp) method to extract the Dit.
Fig. 6(b) shows the Ditand Gp/ω as a function of f. The Ditis
obtained from the Gp/ω peak [26]–[29], where ω is the
angu-lar frequency. A low Ditof 1.2× 1010eV−1/cm2is obtained,
the lowest reported data among GaN MOSFET [2]–[13]. Because of the large high-κ gate capacitance and the small
Dit, the Dit extraction by conductance method is accurate due to Cox > qDit [29]. Such a low Dit value is also
con-sistent with the measured small SS of only 79 mV/dec. In high-κ/Si [22] and high-κ/Ge MOSFETs [23] without inter-facial SiO2, the interface reaction largely degrades the Dit.
The excellent Dit in this work is due to the SiO2 to lower high-κ and GaN reaction.
The high voltage operation and good reliability are the necessary characteristics for power device. Fig. 7 shows
FIGURE 7. The VBDcharacteristics of gate-recessed high-κ GaN MOSFET.
the ID − VD characteristics of gate-recessed high-κ GaN MOSFET. A high VBD of 720 and 970 V are obtained at
VG of 0.1 and 1 V, indicating the breakdown is sensitive to defects in GaN. These VBD values are high enough for 600 V system application.
Fig. 8(a) is the ID-stress versus time characteristics of gate-recessed metal-gate/high-κ MOSFET during maximum
ION (ION,max) at VG= 4 V, VD= 20 V and elevated 175◦C
stress. The ION has only slight variation during stress, but the IOFF becomes better with increasing stress time. The ION/IOFFimproves from initial 109to 1010after stress, which
may be related to the electrons trapping/de-trapping inside GaN. Fig. 8(b) shows the ID− VG characteristics before and after stress at 175◦C and ION,maxfor 1000 sec. TheΔVTafter 175◦C stress is only 40 mV, which is the best data among reported GaN MOSFET [2]–[13]. This result further sup-ports the excellent gate oxide and MOS interface, consistent with the small SS and very low IOFF. For comparison, the
ID− VG hysteresis of fresh device before bias-temperature stress is also plotted in Fig. 8(c), which has a small ΔVT of 15 mV.
To further investigate such excellent stress reliability, the self-consistent Schrödinger and Poisson equations were solved for both AlGaN/GaN HEMT and gate-recessed metal-gate/high-κ GaN MOSFET. Figs. 9(a) and 9(b) are the calculated data of electron wave-function and carrier density distributions for AlGaN/GaN HEMT, respectively. The polar-ization induced a thin layer of charge at the interface [30] with a two-dimensional electron gas (2DEG) density of 1× 1013 cm−2that agrees with the Hall measurement data well. At this high 2DEG density, electron wave-functions of ground and two excited states were populated, but penetrates into AlGaN.
The wave-function penetration into AlGaN barrier can be observed clearly from the carrier density distribution, which is due to the small conduction band offset (ΔEC) of 0.34 eV and the elevated quantum energy levels. It is well known the Al-content compound semiconductor such as AlGaAs, InAlAs, and AlGaN have high trap densities. During the
FIGURE 8. (a) The IDas a function of time during stress at ID,maxand 175◦C for 1000 sec. (b) Forward and reversed ID− VGsweep curves after
1000 sec stress at 175◦C and VD= 20 V. (c) The fresh device before bias-temperature stress.
device operation, the energetic channel hot electrons can be easily trapped inside the AlGaN defect centers and cause device performance degradation.
Figs. 9(c) and 9(d) present the calculated data of electron wave-function and carrier density distributions for gate-recessed metal-gate/high-κ GaN MOSFET, respectively. At an inversion density of 1 × 1013 cm−2 induced by MOS
VG, the ground and two excited states were also found. Although the quantum confinement lifts the energy lev-els, the electron wave-functions are still confined within the
FIGURE 9. (a) The electron wave-function distribution and (b) carrier density distribution of AlGaN/GaN HEMT. (c) The electron wave-function distribution and (d) carrier density distribution of gate-recessed metal-gate/high-κ GaN MOSFET.
GaN well. The interfacial SiO2gate dielectric not only low-ers the remote phonon scattering and increase the mobility, but also increasesΔEC. Such largeΔECis crucial to confine
the energetic channel hot electrons during device operation, which explains the excellent reliability even at ION,max and 175◦C stress. This large bandgap ultra-thin SiO2 interfacial layer has been implemented in metal-gate/high-κ Si CMOS manufacture to improve the remote phonon scattering and increase the drive current [19], [22]. The oxidized AlGaN under selective-etching process may be the other potential mechanism to passivate the GaN surface and reach good interface compared with previous work [11].
IV. CONCLUSION
Excellent device performance of the highest ION,nor, high
VBD, low Ron, and the best reliability are achieved in gate-recessed metal-gate/high-κ GaN MOSFET simultaneously. This device has steep SS comparable with the metal-gate/high-κ Si MOSFET, but having significantly larger ION/IOFF and higher VBD. The excellent stress reliability is
attributed to the largeΔEC between the high-κ gate dielec-tric and GaN channel, which is in sharp contrast to the strong wave-function penetration into AlGaN barrier in the AlGaN/GaN HEMT.
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SHIH-HAN YI, photograph and biography not available at the time of
publication.
DUN-BAO RUAN, photograph and biography not available at the time of
publication.
SHAOYAN DI, photograph and biography not available at the time of
publication.
XIAOYAN LIU, photograph and biography not available at the time of
publication.
YUNG HSIEN WU, photograph and biography not available at the time of
publication.
ALBERT CHIN, photograph and biography not available at the time of
