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氮化處理與氟摻雜對二氧化鉿堆疊式閘極介電層金氧半場效電晶體其電性特性與可靠性影響

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(1)國 立 交 通 大 學 電子工程學系 電子研究所 博 士 論 文 氮化處理與氟摻雜對二氧化鉿堆疊式閘極介電層 金氧半場效電晶體其電性特性與可靠性影響 Effects of Nitridation and Fluorine Incorporation on the Electrical Characteristics and Reliabilities of MOSFETs with HfO2/SiON Gate Stack. 研 究 生:盧文泰 指導教授:黃調元 博士. 中 華 民 國 九十四 年 九 月.

(2) 氮化處理與氟摻雜對二氧化鉿堆疊式閘極介電 層金氧半場效電晶體其電性特性與可靠性影響. Effects of Nitridation and Fluorine Incorporation on the Electrical Characteristics and Reliabilities of MOSFETs with HfO2/SiON Gate stack 研 究 生:盧 文 泰. Student :Wen-Tai Lu. 指導教授:黃 調 元 博士. Advisors:Dr. Tiao-Yuan Huang. 國 立 交 通 大 學 電子工程學系 電子研究所 博 士 論 文 A Dissertation. Submitted to Department of Electronics Engineering and Institute of Electronics College of Electrical and Computer Engineering National Chiao Tung University In Partial Fulfillment of the Requirements for the Degree of Doctor of Philosophy in Electronics Engineering September 2005 Hsinchu, Taiwan, Republic of China. 中 華 民 國 九十四 年 九 月.

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(6) 氮化處理與氟摻雜對二氧化鉿堆疊式閘極介電層 金氧半場效電晶體其電性特性與可靠性影響. 研究生 : 盧文泰. 指導教授 : 黃調元 博士. 國立交通大學 電子工程學系 電子研究所 博士論文. 摘要. 隨著 CMOS 技術急速的微縮到奈米技術點,傳統閘極介電層二氧化矽層將 達到其物理與電性限制。主要的問題是的量子效應引發無法接受的大量的载子直 接穿隧電流(Direct Tunneling Current)穿隧超薄二氧化矽層。為了可以有效的抑制 此漏電流,高介電常數的閘極介電層材料會被使用來取代傳統的二氧化矽層而可 以維持在相同的等效電性氧化層厚度(EOT)下增加實際介電層膜的厚度。在本論 文中,我們對於具有二氧化鉿堆積式閘極介電層之金氧半元件與電晶體,研究不 同氮化處理,如沉積前的不同氣體電漿處理、沉積後的 N2O 氣體電漿處理、後 沉積低溫氨氣處理及氟併入到閘極介電層,對二氧化鉿堆積式閘極介電層其電性 特性(如電荷捕捉)及固定偏壓電應力(constant voltage stress)、負偏壓不穩定 (negative bias-temperature instability,NBTI),AC 電性應力(AC stress)..等可靠性 議題。此外,我們也針對目前文獻很少發表有關於高介電層材料,其電漿損害效. -i-.

(7) 應做了深入探討,及其對於 NBTI 效應之影響和氟對於漿損害效應的改善影響。 我們也對於目前高介電層材料的另一大問題,由於快速電荷捕捉所引起的電壓不 穩定(Threshold voltage instability),架設了可以對這些快速缺陷(Fast Transient Charge Trap, FTCT)作探討的單一脈波 Id&Vg 量測(Single-Pulsed Id&Vg)。 首先,我們探討了我們利用氨氣及一氧化二氮高密度電漿來處理矽基板表 面,形成一層薄的含氮的介面層,及與ㄧ般傳統的二氧化矽介面層或是直接沉積 HfO2 薄膜在矽基板上的閘極介電層,他們在電性上和可靠度上的差異,結果顯 示經過高密度電漿處理過後的介面層電性較差,且漏電流仍然未達到我們要的標 準,必須經由傳統的快速升溫回火來修補這些損害,所以修補後呈現出較小的漏 電流、較小的磁滯、較小的頻率分散、較大的崩潰電壓。而就可靠度來說,經由 氨氣電漿處理的試片會有最大的崩潰時間、崩潰電荷,以及最好的特性存活時 間,所以用氨氣來作為表面處理的氣體是很好的選擇!我們發現對於由氮化鈦作 為電極的電容,在二氧化鉿薄膜裡面主要的捕捉電荷機制是電洞捕捉而不是電子 捕捉。而這種行為可以用捕獲面積模型來適當敘述。特別的是,平帶電壓平移是 由於陷阱填補而不是陷阱產生.而電洞捕捉為主要機制可以歸因於電洞由基板注 入的機率遠大於電子由閘極注入的機率而這是因為氮化鈦電極的功函數造成電 洞具有較短的穿透路徑。 其次,我們提出一個改善二氧化鉿電性特性的後沉積低溫氨氣處理方法。 於二氧化鉿介電層沉積後,但於後沉積退火前,使用低溫 (~400 ℃) 氨氣對二 氧化鉿介電層做氮化處理,我們發現並有低溫氨氣處理的試片呈現出較好 C-V 特性、較小的頻率分散、較低的漏電流、崩潰電場等等。此外,低溫氨氣處理的 試片也呈現出較少的二氧化鉿本體內部缺陷(bulk trap),且對於電壓應力抵抗能 力也明顯被改善,即使於高溫的 700℃的 PDA。最後,我們發現經過電壓應力後, 漏電流主要是由於電洞的 SILC 所主導。 此外,我們也嘗試使用一氧化二氮氣體對二氧化鉿作電漿氮化處理,來改善 二氧化鉿閘極介電層的品質。我們發現一氧化二氮電漿氮化處理後,可以得到諸 - ii -.

(8) 如較低閘極漏電流、較高電導頂峰值(higher peak of transconductor)、較佳次臨界 擺幅(substhreshold swing)、較低界面缺陷、和較低二氧化鉿本體缺陷等優點。我 們也發現,在固定電壓應力(CVS)、及負偏壓-溫度應力(NBTI)的可靠性測試中, 不管是否經過 N2O 處理,電晶體之退化,主要是由於本體中之捕捉行為,而非 界面缺陷的增加。且經氮化處理後,原本呈現捕捉電洞之行為,會轉變成捕捉電 子。在動態應力(dynamic AC stress)可靠性測試下,我們發現,關閉時間(off-time) 時釋放電洞之行為,及因開啟時間(on-time)太短,而來不及捕捉電洞,二者均須 加以考量,方能解釋動態應力下臨界電壓漂移之行為。透過載子分離(carrier separation)量測,我們得以釐清,崩潰究竟是發生於二氧化鉿本體內部或是界面 層。 最後,本論文中,我們探討氟對具有 HfO2/SiON 閘極介電層之 p 型電晶體 其可靠性的影響。利用氟摻雜在源極/汲極摻雜過程前,然後藉由接下來的高溫 摻雜活化過程使氟原子擴散到通道和閘極介電層中去形成氟的併入。發現導入氟 對所製造的元件其基本特性沒有明顯的改變,但在固定電壓應力(CVS)和負偏壓溫度應力(NBTS)測試時,觀察到有氟併入的元件有較低的界面狀態產生和較少 的電荷捕捉,因而改善元件的穩定性和可靠性。其次,則是探討電漿效應對具有 HfO2/SiON 閘極介電層之 p 型電晶體電性與其對 NBTI 可靠性的影響,以及氟併 入對這些結果的影響也有深入探討。我們發現不論在 NBTS 前後,界面狀態密度 均會隨天線面積比而增加。且負偏壓-溫度應力 (NBTS) 所導致的臨界電壓漂 移,也會因受到電漿充電損傷而更加惡化,且其會造成嚴重的電洞缺陷。更重要 的是,電漿充電效應會使在二氧化鉿內的的電洞捕捉現象的惡化比界面產生的缺 陷更嚴重。這和傳統以二氧化矽為閘極之 p 型通道電晶體為電子捕捉是不同的。 利用氟併入可有效增加對電漿充電損傷的免疫,因此降低具有大天線面積比之元 件在 NBTS 時的嚴重電洞捕捉現象。氟併入仍然維持相同的臨界電壓漂移與界面 狀態密度產生的活化能,分別為 0.08eV 與 0.12eV。實驗結果發現,AC 電性應 力下,臨界電壓漂移會從 DC 電性應力下的負漂移轉變成的正漂移。這可能是因 - iii -.

(9) 為在 AC 電性應力一週期裡的 on time 時有較少的電洞捕捉及 off time 時有較多電 洞被釋放。此外,AC 電性應力下,界面狀態密度產生不易受頻率與 duty cycle 影響且電洞捕捉現象是ㄧ主要的劣化原因。. - iv -.

(10) Effects of Nitridation and Fluorine Incorporation on the Electrical Characteristics and Reliabilities of MOSFETs with HfO2/SiON Gate Stack. Student : Wen-Tai Lu. Advisors : Dr. Tiao-Yuan Huang. Department of Electronics Engineering & Institute of Electronics National Chiao-Tung University. Abstract. As CMOS devices are scaled aggressively into nanometer regime, SiO2 gate dielectric is approaching its physical and electrical limits. The primary issue is the intolerably huge leakage current caused by the direct tunneling of carriers through the ultrathin oxide. To substantially suppress the leakage current, high-k materials are recently employed by exploiting the increased physical thickness at the same equivalent oxide thickness (EOT). In this dissertation, the electrical characteristics of pMOSFETs with HfO2/SiON gate stack subjected various Nitridation, i.e., pre-deposition plasma treatments, post-deposition N2O plasma Nitridation, low temperature NH3 Nitridation, and incorporated with Fluorine were discussed. The related reliabilities, including CVS stress, NBTS, dynamic unipolar AC stress, and charge traping, were comprehensively investigated. In addition, the characteristics of. -v-.

(11) plasma charging damage of the HfO2 high k film few reported and the impact of plasma charging damage on NBTI effects also were studied in detail. Moreover, we also investigate the threshold voltage instability in high k film, due to fast charge trapping at Fast Transient Charge Trap (FTCT), by using the single pulse Id-Vg measurement. First, we investigated the effects of various pre-deposition plasma treatments (NH3 and N2O) on Si surface to form an interfacial layer before deposition HfO2 gate dielectric. In order to significantly reduce gate leakage current, a good quality interfacial layer is essential before deposition of high k film. However, our results show that samples with various gas plasma pre-treatments still result in poor electrical properties and the leakage current does not meet device criterion. A conventional RTA is found to be necessary to repair the damage in the interfacial layer. Samples with plasma pre-treatment and RTA anneal depict lower leakage current, smaller hysteresis and frequency dispersion, and higher breakdown voltage. In addition, NH3 pre-treatment also results in longer time to breakdown, larger charge to breakdown and better characteristics life time. The samples with conventional RTA show much lower leakage current, lower frequency dispersion, and smaller hysteresis than as-deposited, spike RTA and no RTA samples because of a thicker interfacial layer. Therefore, RTA is still an essential process after pre-treatment to densify nitrided interfacial layer. We also found that the dominant charge trapping mechanism in the high-k gate stack is hole trapping rather than electron trapping. This behavior can be well described by the distributed capture cross section model. In particular, the flatband voltage shift (∆Vfb) is mainly caused by the trap filling instead of the trap creation. The dominant hole trapping can be ascribed to a higher probability for hole tunneling from the substrate, compared to electron tunneling from the gate, due to a. - vi -.

(12) shorter tunneling path over the barrier for holes due to the work function of the TiN gate electrode. Second,. we. proposed. a. post-deposition. low-temperature. (~. 400°C). NH3-treatment on the HfO2/SiO2 gate stacks with TiN gate electrode. Our results indicate that samples subject to the LTN treatment exhibit superior C-V characteristics, less frequency dispersion, and lower gate leakage. In addition, the defect density in the bulk and the immunity against trap generations are significantly improved, especially for samples with subsequent 700°C PDA. Moreover, we find that the trap-assisted hole tunneling mechanism is responsible for the increase in gate leakage current after constant voltage stress. Next, we used post-deposition N2O plasma treatment to improve the characteristics of pMOSFETs with HfO2/SiON gate stack. We have found that the improvements include many aspects, such as the reduced leakage current, the better subthreshold swing, the enhanced normalized tranconductance, and the higher driving current. Those were ascribed to the lower interface states and bulk traps, confirmed by various type of charge pumping measurement. In evaluation of the reliability, it was found that the degradation caused by the voltage stress and NBTI was dominated by the charge trapping in the bulk of HfO2 films rather than interface states generation no matter whether the N2O plasma treatment was employed or not. In addition, it was observed that the N2O plasma treatment did significantly improve the charge trapping - vii -.

(13) characteristics and the electron trapping is the main mechanism during stressing, which was opposite to the hole trapping observed in the case without the N2O plasma treatment. Under dynamic AC stress, both the off-time de-trapping and the lack of hole trapping due to short on-time are required to explain the behavior of threshold voltage degradation. Finally, through the help of carrier separation experiments, we have clarified whether the breakdown originates in the bulk or the interfacial layer. Finally, we investigate the effects of fluorine (F) incorporation into HfO2/SiON gate stack on the reliabilities of pMOSFETs with HfO2/SiON gate stack. Fluorine was incorporated before the source/drain implant step, which was subsequently diffused into the gate stack during later dopant activation. We found that F introduction only negligibly impacts the fundamental electrical properties of the fabricated transistors. In addition, under constant voltage stress (CVS) and negative bias temperature stress (NBTS), lower generation rates of interface states and charge trapping are observed for devices with F incorporation, thus enhances high-k devices’ stability and reliability. Next, effects of plasma charging and fluorine incorporation were also explored thoroughly. We find that the interface-state density is increased for devices with large antenna ratio, both before and after the BTS. It is clearly shown that the threshold voltage shift during negative bias-temperature stressing (NBTS) is deteriorated by plasma charging damage, causing severe hole traps, which is different from that. - viii -.

(14) observed in traditional pMOSFETs with SiO2 gate dielectric where electron trapping is dominant. More importantly, we also found that hole trappings are aggravated in HfO2 film as compared to interface trap generation by plasma charging. Fluorine incorporation would effectively improve plasma charging immunity, thus reducing the severe hole trapping under NBTS for devices with large antenna area ratios. F incorporation is effective in suppressing hole trapping as well as interface trap generation, thus improving threshold voltage instability. Furthermore, fluorine incorporation maintains almost the same activation energies of threshold voltage shift is 0.08 eV and that of interface trap generation is 0.14 eV for both devices. Fluorine is found to be able to electrically passivate traps without changing the NBTI mechanism. The experimental results of dynamic AC stressing show that threshold voltage shifts toward more negative voltage in DC stress, but shifts toward more positive voltage under AC unipolar stress. This is believed to be due to less hole charge trapping during on-time of a AC cycle and more hole charge de-trapping during off-time of a AC cycle. The interface trap generation depends weakly on both frequency and duty cycle. Instead of interface trap, the bulk trap of HfO2 eventually plays a preponderant role during AC stress.. - ix -.

(15) 誌謝 在博士班的研究生涯裡,我很幸運地可以在黃調元教授的指導下,學習做研 究與思考問題的方法。因此,我要特別感謝我的指導教授:黃調元博士。感謝他 在論文的方向與實驗上,提供了很多的寶貴意見與協助,使論文得以順利地完 成。此外,我十分感激國家奈米元件實驗室(NDL)的簡昭欣博士,一位亦師亦友 亦兄的長輩,在我博士班期間,在生活上、知識上、實驗上同時都不順暢時,給 予我極大精神支柱與專業上指導和照顧,讓我可以找到屬於自己的方向與興趣。 且從他熱忱與嚴謹的研究態度,我學到從不同角度去觀察事物與不放棄的精神。 沒有他的協助,博士論文是不可能進行地如此順利,在此真由衷的感謝他,謝謝 你的幫助。同時,也要感謝林鴻志老師,會提供我很多的親身經驗與專業態度, 對我而言實在是獲益良多。也要感謝自己帶的學弟林博青、林盈彰、藍文廷、李 聰杰,有他們在實驗上的互相協助幫忙,實驗得以很順利。 我也要感謝跟我一起成長的學長陳經緯博士、同學陳永裕博士、同學彭辭修 博士、學弟陳世璋、楊紹明、鄭兆欽、陳怡誠,及幫助我實驗順利的 NDL 工程 師,楊明瑞、黃瑞豪、沈世文、呂正傑、許世祿等先生的幫忙,也感謝彭馨怡、 蔣秋芬、徐台鳳、陳琇芝、李春杏、范瑞雲小姐在我趕實驗時的大力相助。及實 驗室所有的學弟妹們在過去幾年對我的幫助。 最後,感謝我的父母及家人對我的支持與栽培。因為你們的關心與支持,我 才得以完成學業。以及感謝前女友傳莉,謝謝她給了我,完全屬於自己的時間於 實驗上,在這邊只能跟她說聲:謝謝,謝謝妳! 這本論文的完成,是很多人的努力及支持下完成的,有太多人要感謝了,若 沒有提到的,在此一起說聲謝謝,因為沒有你們,這本論文就沒辦法完成,謝謝 大家的幫忙!. x.

(16) Contents. Abstract (in Chinese) ............................................................................................... i Abstract (in English) ................................................................................................ iv Acknowledgements ................................................................................................. x Contents ................................................................................................................... xi Table Captions .........................................................................................................xiv Figure Captions ....................................................................................................... xv. Chapter 1 Introduction ........................................................................................... 1 1.1. General Background ........................................................................................ 1. 1.2. Organization of the Dissertation ...................................................................... 4. Chapter 2 Characteristics The Effects of Surface Pre-deposition Treatments on the Properties of HfO2 Thin Films ..................................................... 13 2.1. Introduction .................................................................................................... 13. 2.2. Experimental .................................................................................................. 15. 2.3. Physical and Electrical Characteristics........................................................... 15. 2.4. 2.3.1.1. C-V and J-V characteristics………………………………………..... 15. 2.3.1.2. Reliability………………………………. .......................................... 18. Characteristics of Hole Trapping in HfO2/SiO2 Gate Stack with TiN Electrode………………………………………………………………......... 19. 2.5. Pre-Existing Charges and Current Transport Mechanism…………….......... 22. 2.6. Summary ........................................................................................................ 23. xi.

(17) Chapter 3 Effects of low-temperature NH3-treatment on the characteristics of HfO2/SiO2 gate stack............................................................................ 48 3.1. Background and Motivation ………………………………........................... 48. 3.2. Experimental………............................................................................... ....... 49. 3.3. Results and Discussions ................................................................................. 50. 3.4. Summary ........................................................................................................ 54. Chapter 4 Effects on the electrical characteristics of pMOSFETs with HfO2 gate stacks by Post-Deposition N2O plasma treatment ................... 67 4.1. Background and Motivation ……………………………….......................... 67. 4.2. Experimental………....................................................................................... 69. 4.3. Results and Discussions ................................................................................. 70. 4.4. Summary ........................................................................................................ 79. Chapter 5 Impacts on the Reliability of HfO2/SiON Gate Stacks by Post-Deposition N2O Plasma Treatment.......................................... 106 5.1. Introduction .................................................................................................. 106. 5.2. Results and Discussions ............................................................................... 106. 5.2.1. Appropriate Measurement Setup for High-k Gate Dielectrics……....... 106. 5.2.2. Breakdown characteristics of HfO(N)/SiON gate stack by using Carrier Separation Method Method ........................................................108. 5.2.3. Dynamic AC stress……………………………………………………...111. 5.2.4. NBTI in HfO2/SiON Gate stacks……………………………………….113. 5.3. Summary .......................................................................................................116. Chapter 6 Effects of Fluorine Incorporation on the Electrical Characteristics of xii.

(18) pMOSFETs with HfO2/SiON Gate Stack………………….…….…145 6.1. Background and Motivation ………………………………..........................145. 6.2. Experimental……….................................................................................…. 146. 6.3. Results and Discussions ................................................................................ 147. 6.3.1. Basic Electrical Properties of Devices ……………………………….... 147. 6.3.2. Appropriate Measurements for Evaluating High-K Gate ....................... 152. 6.3.3. NBTI of Control and Fluorine-Incorporated Devices .............................153. 6.3.4. Dynamic AC stress……………………………………………………...157. 6.3.5. Fast Transient Charge Trapping Technique (FTCT)…………………....159. 6.4. Summary .......................................................................................................160. Chapter 7 Improved Immunity against Plasma Charging Damage of pMOSFETs with HfO2/SiON Gate Stack by Fluorine Incorporation ………………………………………………………. 204 7.1. Introduction .................................................................................................. 204. 7.2. Results and Discussions ................................................................................204. 7.2.1. Plasma Charging Damage of Control and Fluorine-Incorporated Devices…………………………….…..….…....................................... 205. 7.2.2 7.3. Effects of Plasma Charging Damage on NBTI...................................... 207. Summary ..................................................................................................... 210. Chapter 8 Conclusions and Suggestions for Future Work .............................. 227 8.1. Conclusions .................................................................................................. 227. 8.2. Suggestions for future work ......................................................................... 230. xiii.

(19) Table Captions. Chapter 1 Table 1.1 Metal oxides thermodynamically stability in direct contact with silicon.. xiv.

(20) Figure Captions. Chapter 1 Fig. 1.1. Measured and simulated Ig-Vg characteristics under inversion condition for nMOSFETs. The dotted line indicates the 1A/cm2 limit for the leakage current.. Fig. 1.2. By using high k material to suppress gate direct tunneling current.. Fig. 1.3. Bandgap and band alignment of high-k dielectric with respect to silicon. The dash line represents 1eV above/below the conductive/valence bands.. Fig. 1.4. Several high-k gate dielectric materials with their bandgaps and dielectric constants.. Chapter 2 Fig. 2.1. (a) C-V and (b) J-V curves of NH3 pre-treatment with different N2 conventional RTA temperature.. Fig. 2.2. The HRTEM images show the (a) as-deposited sample, and the sample with NH3 pre-treatment and conventional N2 RTA at (b) 900℃ (c) 950℃ (d) 1000℃ annealing.. Fig. 2.3. The (a) C-V and (b) J-V curves of NH3 pre-treatment with N2 spike RTA temperature.. Fig. 2.4. The (a) C-V and (b) J-V curves of N2O pre-treatment with N2 conventional RTA.. Fig. 2.5. The (a) C-V and (b) J-V curves of N2O pre-treatment with N2 spike RTA.. Fig. 2.6. The (a) C-V and (b) J-V curves of 900℃ N2 annealing with N2O/NH3 plasma pre-treatment by conventional RTA and spike RTA.. Fig. 2.7. Frequency dispersion as a function of various RTA temperature for N2O and NH3 pre-treatment samples.. Fig. 2.8. Hysteresis seems to be improved by using conventional N2 RTA following the interfacial layer formation. The formation of interfacial layer by using NH3 plasma treatment shows the better hysteresis characteristics.. Fig. 2.9. (a) The J-V characteristics with different I.L (RTO, N2O, NH3) treatment method at same post-treatment annealing (900oC). (b) The Weibull plot shows the gate current densities at Vg= −1V with different I.L. treatment method (RTO, N2O, NH3). xv.

(21) Fig. 2.10 The TEM images of the HfO2 with (a) RTO I.L.(b) N2O pre-treatment and 900℃ N2 RTA annealing. (c) NH3 pre-treatment and 900℃ N2 RTA annealing. Fig. 2.11 The Weibull plot shows the effective breakdown field with different I.L. treatment method (RTO, N2O, NH3) at same post-treatment annealing (900oC). Fig. 2.12 (a) Definition of breakdown for the sample under constant voltage stress (b)The Weibull plot shows the time to breakdown under constant voltage stress with different I.L. treatment method (RTO, N2O, NH3) at same post-treatment annealing (900oC). Fig. 2.13 The Weibull plot shows the charges to breakdown under −4.8V stress voltage with different I.L. treatment method (RTO, N2O, NH3). Fig. 2.14 10-year lifetime projection for the samples with different I.L. treatment method (RTO, N2O, NH3) at same post-treatment annealing (900oC). Fig. 2.15 (a) C-V curves and (b) G-V curves measured at 100 kHz with increasing stress time as a parameter. The stress voltage (Vg) was – 3.5 V. The curve labeled t = 0 s corresponds to the data before stressing. Fig. 2.16 Dependence of flat band voltage on (a) injected charge density (b)stress time at various stress voltages; symbols are measured data; solid curves are fitting curves. Fig. 2.17 Energy diagram of HfO2/SiO2 gate stack capacitor with mid-gap TiN metal gate electrode under constant voltage stress (Vg = – 4.2 V). Fig. 2.18 Gate current density as a function of injection charge density for various stress voltages. Fig. 2.19 (a) Flat band voltage versus stress time under positive constant voltage stress, and (b) Flat band voltage shift versus stress time under dynamic stressing with stress and passivation duration both 1000 sec. Fig. 2.20 (a) The J-V curves measurement under various temperatures from 25℃ to 150℃ (a) before and (b) after stress of – 4.0V 600s. Fig. 2.21 (a) ln (J/E) v.s. 1000/T under different HfO2/ SiOx stack voltage, and the symbols are experiment data and the solid line are fit curve. (b) Energy band diagram of HfO2/SiOx stack to illustrate the conduction mechanism of Frankel-Poole emission.. Chapter 3 Fig. 3.1. Cross-sectional HRTEM images of the HfO2/SiO2 gate stacks (a) for as xvi.

(22) deposited film; (b) annealed at 600°C; (c) annealed at 700°C; (d) annealed at 700°C and subjected to LTN treatment. Fig. 3.2. (a) C-V characteristics and (b) frequency dispersion rates and EOT values of the HfO2/SiO2 gate stacks with/without LTN for various temperatures PDA.. Fig. 3.3. Plot of hysteresis as a function of the PDA temperature of the HfO2/SiO2 gate stacks with/without LTN.. Fig. 3.4. J-V characteristics of HfO2/SiO2 gate stack with/without LTN for various PDA temperature treatments.. Fig. 3.5. Dependences of gate leakage current density on temperature for the 700°C- PDA-treated HfO2/SiO2 gate stacks with or without LTN.. Fig. 3.6. Weibull distributions of dielectric breakdown voltage for the HfO2/SiO2 gate stacks, with/without LTN, with various temperatures PDA treatments.. Fig. 3.7. J-V characteristics as a function of stress time under constant voltage stress (Vg = -3.75 V) for the 700°C- PDA-treated HfO2/SiO2 gate stacks without LTN.. Fig. 3.8. C-V curves measured at 100 kHz with stress time as a parameter under constant voltage stress (Vg = - 3.75 V) for the 700°C-PDA-treated HfO2/SiO2 gate stacks without LTN.. Fig. 3.9. (a) Schematic energy band diagram of the gate stack under Vg = -3.75 V stress (b) trap-assisted hole tunneling mechanism responsible for the increase in gate leakage current.. Fig. 3.10 Trap generation rate of the HfO2/SiO2 gate stacks with/without LTN under constant voltage stress (Vg = -3.75 V).. Chapter 4 Fig. 4.1. Gate leakage current of p+ poly-gated pMOSFETs with HfO2/SiON high-k gate stacks subjected to N2O plasma treatment or no additional treatment was shown under (a) inversion and (b) accumulation region, respectively.. Fig. 4.2. Capacitance−voltage (C−V) characteristics measured at 100 kHz for the HfO2/SiON high-k gate stacks with/without N2O plasma treatment. The equivalent oxide thickness (EOT) was determined by measuring the maximum inversion capacitance.. Fig. 4.3. Cross-sectional HRTEM images of the HfO2/SiO2 gate stacks (a) without (b) with N2O plasma treatment.. Fig. 4.4. Id-Vd characteristics of pMOSFETs with HfO2 gate stacks with/without xvii.

(23) N2O plasma treatment. Fig. 4.5. (a). Id-Vg. characteristics and (b) normalized transconductance characteristics of pMOSFETs with HfO2 gate stack with/without N2O plasma treatment.. Fig. 4.6. Schematic illustrations for the charge pumping (CP) measurement with (a) fixed amplitude sweep (b) fixed base sweep (c) fixed peak sweep. The arrows indicated the sweep direction.. Fig. 4.7. Results of the charge pumping (CP) measurements with (a) fixed amplitude (b) fixed base sweep (c) fixed peak sweep as a function of the frequency of gate pulse for the pMOSFETs with HfO2 gate stack with/without N2O plasma treatment.. Fig. 4.8. Possible current contributions in a CP measurement with high-k gate dielectrics. Beside the recombination current due to interface states (1), the charging and discharging of bulk defects (2), recombination of inversion carriers due to geometry effect (3), the gate current contribution (4) and minority carrier diffusion (not shown) need to be considered.. Fig. 4.9. Interface states density as a function of Vgl for the HfO2 gate stacks with/without N2O plasma treatment measured by fixed amplitude sweep at frequency of 1 MHz.. Fig. 4.10 NCP and NDS were determined from the CP current and source/drain current measured by fixed base sweep at 5 kHz. Lower bulk traps were obtained by applying N2O plasma treatment. Fig. 4.11 Dependence of threshold voltage shift (△Vth) on injected charge densities (Ninj) under constant gate overdrive voltage of Vg-Vth= −2.2V (open symbol) and Vg-Vth= -2.6V (solid symbol). Fig. 4.12 Dependence of generated interface state densities (△Nit) and trapping charges (△Ntot) on injected charge densities (Ninj) under constant gate overdrive stress voltage of Vgo=Vg−Vth= −2.2V (open sympol) and Vgo=Vg−Vth= −2.6V (solid sympol). Fig. 4.13 The results of carrier separation of HfO2/SiON gate stacks without N2O plasma treatment under inversion region. Gate current is dominated by hole current. Fig. 4.14 Dependence of (a) IG , IB and (b) IDS current on substrate bias for HfO2/SiON high-k gate dielectrics without post-N2O plasma treatment. Fig. 4.15 (a) The current components of asymmetric band diagrams (b) The flows of current components of the HfO2/SiON gate stacks at inversion region are shown. xviii.

(24) Fig. 4.16 The results of carrier separation of HfO2/SiON gate stacks with N2O plasma treatment under both inversion and accumulation regions. Fig. 4.17 Dependence of ISD, IG, and IB on substrate bias for HfO2/SiON high-k gate dielectrics with post-N2O plasma treatment. Fig. 4.18 Dependence of carrier separation results of ISD, IG, and IB on substrate bias of HfO2/SiON high-k gate dielectrics (w/ post-N2O plasma treatment). Fig. 4.19 Carrier separation results versus gate voltage for fresh devices at various temperatures of As-dept. samples. Fig. 4.20 Carrier separation results versus gate voltage for fresh devices at various temperatures of post-N2O plasma treatment samples. Fig. 4.21 Frenkel-Poole plot for the source/drain current in the inversion region, good fitting curves can be observed (solid line) for the As-dept. sample. Fig. 4.22 Frenkel-Poole plot for the substrate current in the inversion region, good fitting curves can be observed (solid line) for the As-dept. sample. Fig. 4.23 Frenkel-Poole plot for the source/drain current in the inversion region, good fitting curves can be observed (solid line) for the post-N2O plasma treatment sample. Fig. 4.24 Frenkel-Poole plot for the substrate current in the inversion region, good fitting curves can be observed (solid line) for the post-N2O plasma treatment sample. Fig. 4.25 Energy band diagram for HfO2/SiON gate stacks without N2O plasma treatment to illustrate the conduction mechanism of Frenkel-Poole emission. Fig. 4.26 Energy band diagram for HfO2/SiON gate stacks with N2O plasma treatment to illustrate the conduction mechanism of Frenkel-Poole emission.. Chapter 5 Fig. 5.1. Repetitive Id-Vg traces for HfO2/SiON high-k gate dielectric using measurement sequence (a) [Vg=0V ↔ Vg=−2V], (b) [Vg=1V ↔ Vg=−2V]. (w/o post-N2O plasma treatment).. Fig. 5.2. Repetitive Id-Vg traces for HfO2/SiON high-k gate dielectric using measurement sequence of [Vg=1V ↔ −2V], [Vg=1V ↔ −2.2V], … , to [Vg=1V ↔ −2.8V] (w/o post-N2O plasma treatment).. Fig. 5.3. Repetitive Id-Vg traces for HfO2/SiON high-k gate dielectric using measurement sequence (a) [Vg=0V ↔ −2V], (b) [Vg=1V ↔ −2V]. (with xix.

(25) post-N2O plasma treatment). Fig. 5.4. Repetitive Id-Vg traces for HfO2/SiON high-k gate dielectric using measurement sequence of [Vg=1V ↔ −2V], [Vg=1V ↔ −2.2V], … , to [Vg=1V ↔ −2.8V] (with post-N2O plasma treatment).. Fig. 5.5. Evolutions of three kinds of current, gate current (IG), S/D current (ISD), and the substrate current (IB) under negative constant voltage stress of −4.2V (w/o post-N2O plasma treatment).. Fig. 5.6. Current of (a) IG, (b) IB, (c) IDS versus gate voltage for Fresh, SILC, and SBD conditions (w/o post-N2O plasma treatment).. Fig. 5.7. Illustrations of damage situations under SILC (a), and after SBD (b) (w/o N2O treatment).. Fig. 5.8. Current of (a) IG, (b) IB, (c) IDS versus gate voltage for Fresh, SILC, and SBD conditions (without post-N2O plasma treatment).. Fig. 5.9. Illustrations of damage situations under SILC (a) and after SBD (b) (without post-N2O plasma treatment).. Fig. 5.10 Setup structure of AC stress with the definition of frequency, on-time, off-time, and duty cycle. Fig. 5.11 Generated interface state densities as a function of stress time for various stress voltage frequencies. (Vgo= −2.2V, duty cycle of 50%, w/o post N2O plasma treatment). Fig. 5.12 Threshold voltage shift as a function of stress time for various stress voltage frequencies. (Vgo= −2.2V, duty cycle of 50%, w/o post N2O plasma treatment). Fig. 5.13 Threshold voltage shift at stress time of 1000 seconds versus gate pulse frequency (w/o post N2O plasma treatment). Fig. 5.14 Generated interface state densities as a function of stress time for various duty cycle of stress voltage. (Vgo= −2.2V, w/o post- N2O plasma treatment). Fig. 5.15 Dependence of threshold voltage shift versus stress time for various stress voltage duty cycles. Vgo= −2.2V at (a) 10k Hz (b) 100 Hz, and (c) 10 Hz. (w/o post- N2O plasma treatment). Fig. 5.16 Dependence of generated interface state densities versus stress time for various stress voltage frequencies. (Vgo= −2.2V, duty cycle of 50%, with post N2O plasma treatment). Fig. 5.17 Dependence of threshold voltage shift versus stress time for various stress voltage frequencies. (Vgo= −2.2V, duty cycle of 50%, with post N2O xx.

(26) plasma treatment). Fig. 5.18 Dependence of threshold voltage shift versus stress time for various stress voltage duty cycles. Vgo=-2.2V at 1k Hz (w/ post-N2O plasma treatment). +. Fig. 5.19 Id,Gm-Vg characteristics for p gated pMOSFETs before and after 1000 seconds stress for (a) room temperature, and (b) 125℃ (w/o post-N2O plasma treatment). Fig. 5.20 Generated interface state densities as a function of stress time under BTS at various stress temperatures. Vgo= −1.5V (w/o post-N2O plasma treatment). Fig. 5.21 Threshold voltage shift as a function of stress time under BTS at various stress temperatures. Vgo= −1.5V (w/o post-N2O plasma treatment). Fig. 5.22 Dependence of △Nit and △Ntot on stress time under Vgo= −2V at various temperatures (w/o post-N2O plasma treatment). +. Fig. 5.23 Id, Gm-Vg characteristics for p gated pMOSFETs before and after 1000 seconds for (a) room temperature, and (b) 125℃ (w/o post-N2O plasma treatment). Fig. 5.24 Generated interface state densities as a function of stress time under BTS at various stress temperatures. Vgo= −2V (w/o post-N2O plasma treatment). Fig. 5.25 Threshold voltage shift as a function of stress time under BTS at various stress temperatures. Vgo= −2V (w/o post-N2O plasma treatment). Fig. 5.26 Dependence of △Nit and △Ntot on stress time under Vgo= −2V at various temperatures (w/o post-N2O plasma treatment). Fig. 5.27 Dependence of Id degradation on stress time under Vgo= −2V at various temperatures (w/o post-N2O plasma treatment). Fig. 5.28 Gate, source/drain, substrate currents for fresh pMOSFETs at various temperatures. Vgo= −2V (w/o post-N2O plasma treatment). +. Fig. 5.29 Id, Gm-Vg characteristics for p gated pMOSFETs before and after 1000 seconds for (a) room temperature, and (b) 125℃. (w/o post-N2O plasma treatment). Fig. 5.30 (a)Threshold voltage shift (b)△Nit and △Ntot as a function of stress time under BTS (Vgo= −2.5V) at various stress temperatures. (w/o post-N2O plasma treatment). Fig. 5.31 (a)Interface trap shift and (b) Threshold voltage shift as a function of stress time under BTS at various stress temperatures. (Vgo= −2.5V).. Chapter 6 xxi.

(27) Fig. 6.1. C-V curves for p-channel MOSFETs with HfO2/SiON gate stack, both with and without F incorporation.. Fig. 6.2. (a) Initial Id-Vg and Gm-Vg characteristics for fresh p-channel devices (b) Cumulative probability of initial threshold voltage (Vth) for HfO2/SiON gate stack with and without F incorporation.. Fig. 6.3. Initial Id-Vd characteristics for fresh p-channel devices with and without F incorporation.. Fig. 6.4. Initial interface trap (Nit) characteristics for fresh p-channel devices with and without F incorporation.. Fig. 6.5. Gate leakage current versus gate bias for fresh p-channel devices with and without F incorporation at room temperature.. Fig. 6.6. Carrier separation under inversion region (a) w/o F sample (b) with F sample.. Fig. 6.7. Carrier separation under accumulation region (a) w/o F sample (b) with F sample.. Fig. 6.8. p+-gated pMOSFET with HfO2/SiON gate stack under inversion region (a) Band diagrams (b) A schematic illustration of carrier separation experiment.. Fig. 6.9. p+-gated pMOSFET with HfO2/SiON gate stack under accumulation region (a) Band diagrams (b) A schematic illustration of carrier separation experiment.. Fig. 6.10 Gate leakage current versus gate bias for fresh p-channel devices at various temperatures (a) w/o F sample (b) with F sample. Fig. 6.11 The conduction mechanism for source/drain current fitting under inversion region (a) w/o F sample (b) with F sample. Fig. 6.12 The conduction mechanism for substrate current fitting under inversion region (a) w/o F sample (b) with F sample. Fig. 6.13 The HRTEM image of the device with HfO2/SiON gate stack. Fig. 6.14 Id-Vg characteristics for p+-gate pMOSFET without F incorporation (a) w/o small stress (b) with small stress. Fig. 6.15 Id-Vg characteristics for p+-gate pMOSFET with F incorporation (a) w/o small stress (b) with small stress. Fig. 6.16 A schematic illustrate for the possible case of Fast Charging Effects (FCE) Fig. 6.17 Id-Vg characteristics for p+-gate pMOSFETs before stress and after stress 1000 s at 25 oC (a) w/o F sample (b) with F sample Fig. 6.18 Threshold voltage shift as a function of stress time, stressed at 25 oC, Vg = xxii.

(28) −3.5 V & −4 V (a) linear scale (b) logarithm scale. Fig. 6.19 nterface trap shift and (b) total trap shift as a function of stress time, stressed at 25 oC, Vg = −3.5 V & −4 V. Fig. 6.20 Drain current degradation in a saturation regime of stress time, stressed at 25 oC, Vg = −3.5 V & −4 V. Fig. 6.21 Threshold voltage shift (b) Interface trap shift as a function of channel length, stressed at 25 oC, Vg =−4 V. Fig. 6.22 Id-Vg characteristics for p+-gate pMOSFETs before stress and after stress 1000 s at 125 oC (a) w/o F sample (b) with F sample. Fig. 6.23 Interface trap shift as a function of stress time under BTS at different stress temperature, Vg =−3.5 V (a) w/o F sample (b)with F sample. Fig. 6.24 Threshold voltage shift as a function of stress time under BTS at different stress temperature, Vg =−3.5 V (a) linear scale (b) logarithm scale. Fig. 6.25 Interface trap shift and (b) total trap shift as a function of stress time under BTS at different stress temperature, Vg = −3.5 V. Fig. 6.26 Drain current degradation in a saturation regime of stress time, stressed at different stress temperature, Vg = −3.5 V. Fig. 6.27 Temperature dependence of both (a) △Vth (b) △Nit. NBT stress was applied under Vg = −3.5 V. Fig. 6.28 Schematic setup and several parameters for measuring threshold voltage instability under AC dynamic stress. Fig. 6.29 Vth shift time evolution for pMOSFETs with HfO2/SiON gate stack, under static and dynamic stresses of different frequency (a) w/o F sample (b) with F sample. Fig. 6.30 Nit shift time evolution for pMOSFETs with HfO2/SiON gate stack, under static and dynamic stresses of different frequency (a) w/o F sample (b) with F sample. Fig. 6.31 Vth shift time evolution for pMOSFETs with HfO2/SiON gate stack, under static and dynamic stresses of different duty cycle (a) w/o F sample (b) with F sample. Fig. 6.32 Nit shift time evolution for pMOSFETs with HfO2/SiON gate stack, under static and dynamic stresses of different duty cycle (a) w/o F sample (b) with F sample. Fig. 6.33 (a) Frequency dependence of △Nit, stressed at 25 oC, Vg =-4 V under duty cycle = 50% (b) Duty Cycle dependence of △Nit, stressed at 25 oC, Vg =-4 V under unipolar 10KHz. xxiii.

(29) Fig. 6.34 Frequency dependence of △Vth, stressed at 25 oC, Vg = −4 V under duty cycle = 50% (b) Duty Cycle dependence of △Vth, stressed at 25 oC, Vg = −4 V under unipolar 10KHz. Fig. 6.35 The transistor is used in an inverter circuit with the gate receiving a single pulse from the pulse generator. The voltage is measured at the transistor drain and converted to drain current because the load resistance value is known. Fig. 6.36 (a) Example data of the pulsed Id-Vg where ∆Vt is measured at 50% of the maximum Id on a W/L = 10/1 µm transistor. (b) Example data of the pulsed Id versus time on a W/L = 10/1 µm transistor where the ‘droop’ at the top is associated with the drop of pulsed Id-Vg at Vg = 2.5 V. Fig. 6.37 A new single pulsed Id-Vg method to improve the noises and parasitic capacitance of conventional method (Fig. 6.35). Fig. 6.38 Single Pulse Id-Vg characteristics for different rising and falling time of (a) 20μs (b) 15μs (c) 6μs illustrating increased trapping (Vt shift) with increased rising and falling time for pMOS. The included pMOS DC ramp Id-Vg result demonstrates the effect of hole charge trapping during the slower measurement, except electron trapping.. Chapter 7 Fig. 7.1. The schematic of metal antenna transistor and definition of Antenna Area Ratio (AAR).. Fig. 7.2. Wafer maps of (a) negative and (b) positive potential values recorded by CHARM-2 sensors.. Fig. 7.3. Nit of PMOS devices with and without F incorporation (a) before sintering (b) after sintering as a function of device location.. Fig. 7.4. Vth of PMOS devices with and without F incorporation (a) before sintering (b) after sintering as a function of device location.. Fig. 7.5. Cumulative probability of the (a) threshold voltage (Vth) and (b) interface trap (Nit).. Fig. 7.6. Output characteristics for fresh devices with AAR of 1K and 60K.. Fig. 7.7. Threshold voltage shift as a function of stress time, stressed at 25 oC, Vg = −4 V (a) linear scale (b) logarithm scale.. Fig. 7.8. (a) Interface trap shift and (b) total trap shift as a function of stress time, stressed at 25 oC, Vg = −4 V.. Fig. 7.9. Drain current degradation in a saturation regime of stress time, stressed at xxiv.

(30) 25 oC, Vg = −4 V. Fig. 7.10 Threshold voltage shift as a function of stress time, stressed at 125 oC, Vg = −3.5 V (a) linear scale (b) logarithm scale. Fig. 7.11 (a) Interface trap generation and (b) total trap density as a function of stress time, stressed at 125 oC, Vg = −3.5 V. Fig. 7.12 Drain current degradation in a saturation regime of stress time, stressed at 125 oC, Vg = −3.5 V. Fig. 7.13 Threshold voltage shift as a function of stress time under BTS at different stress temperature, Vg =−3.5 V. AAR is 60K (a) linear scale (b) logarithm scale. Fig. 7.14 (a) Interface trap generation and (b) total trap density as a function of stress time under BTS at different stress temperature, Vg = −3.5 V. AAR =60K.. xxv.

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