寬頻一進二出放大器設計

國

立

交

通

大

學

電子工程學系 電子研究所

碩 士 論 文

寬頻一進二出放大器設計

Wideband Splitter Amplifier Design

研 究 生：黃瀞瑩

指導教授：胡樹一 教授

寬頻一進二出放大器設計

Wideband Splitter Amplifier Design

研 究 生： 黃瀞瑩 Student : Ching-Ying Huang

指導教授： 胡樹一 博士 Advisor : Dr. Shu-I Hu

國 立 交 通 大 學

電子工程學系 電子研究所

碩 士 論 文

A Thesis

Submitted to Department of Electronics Engineering and Institute of Electronics

College of Electrical and Computer Engineering National Chiao Tung University

in partial Fulfillment of the Requirements for the Degree of

Master in

Electronics Engineering

July 2010

Hsinchu, Taiwan, Republic of China

I

寬頻一進二出放大器設計

學生：黃瀞瑩 指導教授：胡樹一教授

國立交通大學

電子工程學系 電子研究所

摘要

由於積體電路的元件設計和系統整合皆已經發展相當成熟，接收器陣 列是未來主流之一。如果把一組接收器系統比擬為一雙眼睛，那麼接收器 陣列就像是蒼蠅的複眼，不但可以接收到更微弱的訊號，還可以增加接收 訊號的廣度;在一個超寬頻的接收器系統當中，由於接收的訊號太寬，必 頇先經由功率分配器輸出多路訊號之後再做切割與降頻，以提供較低頻且 窄頻的訊號給後級的類比數位轉換器處理。然而，傳統的功率分配器大多 使用由被動式元件組成的多階項功率分配器來達到寬頻的效果（例：威爾 金森功率分配器）。此種功率分配器雖然不消耗功率，卻會佔用相當可觀 的面積，無法順利做成接收器陣列。此外，被動式功率分配器在寬頻的應 用之下在隔絕度上有很大的限制，如果使用在對於輸出訊號獨立性要求特 別高的系統當中，通常需要外接其他元件才能夠達到足夠的隔絕度，實用 性上不是很高。為了更進一步的改善傳統被動式功率分配器在面積消耗和 寬頻之下隔絕度的限制，在此提出結合主動式元件的功率分配兼放大器。 利用主動式元件本身具有良好的隔絕度，輸出獨立性極高的兩路訊號，更 能夠以積體電路來取代原本需要極大面積的被動式功率分配器。

II

Wideband Splitter Amplifier Design

Student: Ching-Ying Huang Advisor: Dr. Shu-I Hu

Department of Electronics Engineering & Institute Electronics

National Chiao Tung University

ABSTRACT

Since the developments of the IC components design and system integration have been quite mature, receiver array is one of mainstream in the future. If we compare a receiver system to eyes, the receiver array would be the compound eyes of the flies which can catch weaker signals and possess the more extensive range. However, it requires power dividers to split out multiple signals; Multi-section Wilkinson power divider is one of the most common power dividers which can reach wideband achievement. Although such passive power divider does not consume any DC power, it requires considerable area. Besides, Wilkinson power divider has a severe limit to isolation in the wideband application. Inevitably we have to add other device to achieve enough isolation while a system demanding of particularly independence between two output signals. This solution is not that efficient. In order to overcome the area consumption and isolation limit problems, we report the active splitter amplifiers integrating active devices. Active power dividers can provide two highly independent signals by employing active device which has good isolation in itself, and reduce area to an IC size.

III

Tables of Contents

Chinese Abstract……...………..…I

Abstract……...………II

Tables of Contents………... III

Chapter1 Introduction……….………....1

1.1 The Motivation and Research Development……….……...…..1

1.2 Passive Power Divider Analysis……..………...4

Chapter2 Traditional Distributed Amplifier…………...6

Chapter3 DC-20GHz Splitter Amplifier………...….…....9

3.1 Architecture Analysis…………..…...……..………..9

3.2 Loss Compensation Topologies………..……….……….11

3.3 Manufacturing in CMOS Process………..……...13

3.4 The Simulated and Measured Results………..…………...14

3.5 Conclusion………...………...19

Chapter4 DC-40GHz Splitter Amplifier………...20

4.1 Architecture Analysis………..………….…….…20

4.2 Coupling Inductors...………...……….…….…21

4.3 Current-Reuse Termination..….………...….22

4.4 Manufacturing in CMOS Process……...……….……..23

4.5 The Simulated and Measured Results……...……..…….….…24

Chapter5 The Measurement Concerns………..…...26

1

Chapter1 Introduction

1.1

The Motivation and Research Development

Fig. 1

Powerdivider1

2

Fig.1 shows a W-band receiver system configuration. The 78.3-113.1GHz band signal is received and this signal will be down conversion to DC-34.8GHz by a mixer. After being split to two paths by a passive power divider, which has the operating frequency band in DC-34.8GHz, the two signals are amplified relatively and then go through powerdivider2 and 3, which’s operating frequency band are in DC-17.4GHz and 17.4-34.8GHz. After the two signals are divided to four ways, all of them will be amplified once again and encounter low-pass and band-pass filters with different operating frequency band: DC-8.7GHz, 8.7-17.4GHz, 17.4-26.1GHz, 26.1-34.8GHz. The four filters extract four sets of frequency band, and the three higher frequency sets will be down conversion to DC-8.7GHz eventually. Because the received signals has too wide band, the receiver system employs power dividers and filters to split and cut signals for four sets in different frequency band. The ultimate goal is to provide narrow band signal for backward analog-to-digital converter, which can only deal with DC-8.7GHz band presently.

3

Fig. 2

Fig.2 is the entity picture of the receiver system. The photo shows that the three multi-sections Wilkinson power dividers engage quite considerable area. If now we take the replace of passive power dividers by active power dividers, which has only the size as same as ICs, the whole area will be reduced greatly so that we can integrate the system to an IC and further fabricate the receiver array. The receiver array can not only catch weaker signals but also extend the function range. For example, if more receivers are placed in the camera lens, the camera can obtain higher sensitization and wide-angle. As a matter of course, we will receive a natural vivid picture.

4

1.2 Passive Power Divider Analysis

Frequency (GHz)

0

5

10 15 20 25

dB

-30

-20

-10

0

S

₂₁

, S

₃₁

S

₂₃

Z

1

, f

1

1

Z

5

, f

5

Z

1

, f

1

Z

5

, f

5

2

3

R

1

R

5 ˙˙˙ ˙˙˙ ˙˙˙

Fig. 3(a) Fig. 3(b)

The Wilkinson power divider has been widely used for splitting the input power into two output signals of the same magnitude and phase and, with modifications, multiple octave bandwidth can be achieved [1], [2]. For applications that require even wider bandwidth, however, this type of passive circuit will be struggling to deliver the intended performance. As shown in Fig. 3(a), a five-section DC–17GHz Wilkinson power divider using ideal transmission lines. The impedance and frequency of the quarter-wave sections are Z_1~5 = 90, 55, 60, 60, 60Ω, and f_1~5 = 8.5, 8.6, 8.7, 8.8, 8.9GHz. The resistance R_1~5 = 120, 200, 330, 330, and 180Ω. As shown in Fig. 3(b), this Wilkinson power divider exhibits a good 3dB power division (S₂₁, S₃₁ are about -3dB), and small input and output reflection coefficients. Though isolation (S₂₃) between the output ports is below -15dB in the middle of the frequency range, it deteriorates rapidly while approaching DC or 17GHz.

5

In this receiver system, the isolation of power dividers is one of the most important considerations. The main reason is that the following stage is four filters with different operating frequency band. The signal which is not in the band will reflect in quantity and leak to another output port while the isolation of the power divider is not good enough. Due to a phase difference between original signal and leaking signal, the output amplitude has a variation in shape of sine wave. This variation will bring about a problem of dynamic range to the next stage. The input power is very likely saturated so that influences the whole receiver’s efficiency. In order to avoid such circumstance, the original method is to add a distributed amplifier, which has good isolation in itself, following each power divider. However, it’s not a practical solution.

Active power dividers, on the other hand, show promise for meeting the wideband design specifications, and its compactness makes it even more appealing. For instance, a 1–10GHz active power divider using 0.13μm CMOS process for phase array application has been demonstrated [3]. In this paper, by re-examining the constraining factors, we like to further extend the bandwidth of the active power divider while at the same time keep improving the circuit’s performance. Details regarding this DC–20GHz active power divider using the more common 0.18μm CMOS process will be presented in the following section.

6

Chapter2 Traditional Distributed Amplifier

Out

In

Z

d

Z

g

R

g

R

d Fig. 4(a)

Out

In

R

g

R

d

L

_d

/2

L

g

/2

L

d

/2

L

g

/2

C

g

C

d

L

d

/2

L

g

/2

L

d

L

g

L

d

/2

L

g

/2

C

d

C

d

C

g

C

g Fig. 4(b)

Distributed amplification, which was originally invented by Percival in 1936 and further developed by Ginzton et al. in 1948, has been widely used as a circuit topology for broadband amplifier design. Distributed amplifiers are constructed from two transmission lines that connect the drain and gate terminals of several field-effect transistors (FETs), as depicted in Fig. 4(a). The two lines are coupled by transconductances of the FETs. The equivalent gate and drain transmission lines are essentially loaded constant-k lines, where the parasitic resistances of FET’s are considered the dominant loss factors.

7

In CMOS, transmission lines are normally constructed using micro-strip lines or ladder-lumped LC elements, as shown in Fig. 4(b). The distribution of the parasitic capacitors of transistors and series inductors is equivalent to a low-pass filter topology so that to achieve wideband amplification, providing the gain and good input and output matching over a large bandwidth. However, this structure provides a relatively low gain due to its paralleled gain cells and large artificial-line losses at high frequency. The characteristic impedance and cutoff frequency of the artificial transmission lines can be expressed as

out out in in C L C L Z₀   ₍₁₎ out out in in T

C

L

C

L

f





1

1

_



₍₂₎

By properly choosing the transistor sizes and the inductance values, the impedances of input and output transmission lines are able to match 50-Ω, offering low input and output return losses.

An RF signal applied at the input travels down the gate line to the terminated end, where it is absorbed. As the signal goes down the gate line, each transistor is excited by the traveling voltage wave and transfers the signal to the drain line through its transconductance. If the phase velocity on the gate line and drain line add in the forward direction as they arrive at the output. The waves traveling in the reverse direction are not in phase. And any uncancelled signal is absorbed by the drain-line termination. A simplified equivalent circuit of a MOSFET arrived at from typical S-parameter measurements at microwave

8

frequency is shown in Fig. 4(c). r_i is the effective input resistance between the gate and source terminals and C_gs is the gate-to-source capacitance. r_o and C_ds are the drain-to-source resistance and capacitance respectively. C_dg is the drain-to-gate capacitance and g_m the transconductance.

S

C

_dg

C

_gs

r

_i

C

_ds

r

_o

i

_ds

V

_c

G

D

Fig. 4(c)

Theoretically, the artificial-line composed by LC networks will be more and more like the realistic transmission line and the gain should increase by adding more LC-networks which is the gain cell in the mean time. However, there are two principal limitations to gain increasing: the series metal losses from the on-chip inductors as well as the frequency response of the transistors due to the finite input gate resistance and output resistances though the gain-bandwidth product has been superior to other amplification structures. Notice that the distributed architecture consumes higher DC power because of the paralleled gain cells.

9

Chapter3 DC-20GHz splitter amplifier

3.1 Architecture Analysis

V

g

1

2

V

d

L

in

/2

L

out

/2

C

in

C

out

R

d

C

d

L

g

3

V

d

V

d Fig. 5(a)

Fig. 5(a) is the Schematic of the DC–20GHz active power divider where port 1 on the left is for input while ports 2 and 3 on the right are for output. Each gain cell is made of two cascade transistor circuits. Not all the gate biases for the transistors are indicated here.

10

As shown in Fig. 5(a), the splitter amplifier circuit is made of three parts. The first is the input artificial transmission line where L_in is the lumped spiral inductor and C_in is the input capacitance of each gain cell; the second part is the gain cell itself which contains two cascode transistor stages; the third is the output artificial L_outC_out artificial transmission line. For simplicity, the finite series resistance and shunt admittance of all these lines are not included in the circuit schematic. As is well known, the system impedance Z₀ of an infinite-length LC line is          ₂ 0 2 0 1 C L Z ₍₃₎

with the cutoff frequency ω0 defined as 0 2 LC [4]. Therefore, compared

with the conventional single-input single-output distributed amplifier, the adding of the other parallel transistor stage along the input transmission line may require the use of larger lumped inductors so as to maintain the same system impedance, but this halves the available bandwidth from 20GHz to 10GHz. In our circuit design, on the contrary, we opt for the use of smaller transistors to relieve this bandwidth constraint while keep the input impedance to be still 50Ω.

With smaller input transistor, each gain cell is now composed of two cascode stages for providing sufficient amplification [5], [6]. The inductor L_g allows the output resistance of the gain cell to be slightly negative, thus compensates for the loss of the output transmission line at high frequency [7]. Bandwidth of the output transmission line is limited at high frequency by its cutoff frequency ωH = 2πfH = 0 2 LoutCout With Lout = 0.65nH and

11

C_out = 140fF, we have f_H = 33GHz. With the two output lines terminating at a common C_d = 11.4pF, the corresponding low frequency point is ω_L = 2πf_L = 2/R_dC_d. For R_d = 45Ω, the corresponding f_L (now 0.62GHz) can be further reduced through the use of large off-chip bypass capacitor. Position of the loading resistor R_d has been oriented to avoid the use of off-chip inductor.

As shown in Fig. 5(b), this circuit is based on the distributed amplification construction. Therefore, the input and output impedance and cut-off frequency are decided by input and output transmission lines where the splitter amplifier reach wideband purpose. The input and output transmission lines must possess the same phase delay to ensure the signals amplified by different gain stages keeping in construction interference.

3.2 Loss Compensation Topologies

L

d2

L

g

gate line

drain line

Z

out

r

o

r

o

L

d1

C

ds

C

gs Fig. 6

12

As predicted in the chapter of distributed amplifiers analysis, there are two principal limitations to gain increasing: the series metal losses from the on-chip inductors as well as the frequency response of the transistors due to the finite input gate resistance and output resistances. To maintain enough gain in high frequency, the gain stage brings to two loss compensation topologies. First method is cascading two cascode pairs of transistors as shown in Fig. 6. Cascode pair series two paralleled resistances r_o. In the traveling wave point view, the signals leaking through the parasitic resistance path decreases while the shunt impedance is larger, as a result of decreasing loss.

In addition to cascade pair of transistors, it introduces gain peaking inductors (L_d1, L_d2, L_g). L_d1 and parasitic capacitor C_ds produce a short path in a specific frequency to avoid the signal leaking out through the C_ds path and passes through the amplified stage more completely. Similarly L_g and parasitic capacitor Cgs produce a short path in a specific frequency to avoid the signal

leaking out through the C_gs path. Furthermore, L_g operates as negative resistance for it decreasing the real part of the output impedance that causes the loss of the drain artificial line. However, the stability is lost when the real part of Zout becomes negative. Ld2 controls the amount of the negative resistance to

13

3.3 Manufacturing in CMOS Process

Fig. 7

Fig. 7 shows the photograph of the divider circuit, which is fabricated using commercial 0.18μm CMOS process and the chip size is 1.1×1.1mm2. To ensure identical outputs, the circuit layout is arranged to be symmetrical. With supply voltage Vd = 2.5Volt and Id = 64Amp, the total power consumption is

160mWatt; the gate bias voltage V_g is 0.8Volt with negligible current in this case.

14

3.4 The Simulated and Measured Results

(1) Simulated S-parameters: V_DD=2.5 Volt, V_g=0.8 Volt, P_DC=120mW

圖(6)a.

Fig. 8(a)

(2) Measured S-parameters: VDD=2.5 Volt, Vg=0.8 Volt, PDC=160mW

Fig. 8(b) Frequency (GHz) 0 5 10 15 20 25 dB -30 -20 -10 0 10 20

S

21

、S

31

S

22

、S

33

S

11 Frequency (GHz) 0 5 10 15 20 25 dB -30 -20 -10 0 10 20

S

11

S

21

、S

31

S

22

、S

33

15

(3) Isolation (S₂₃)

圖(6)c.

Fig. 8(c) (4) Measured phase of S₂₁ ans S₃₁

Fig. 8(d) The solid curve is ∠S₂₁; dashed curve is ∠S₃₁

Frequency (GHz) 0 5 10 15 20 25 Output -por t iso lati on (dB) -50 -40 -30 -20 -10

1

2

3

Frequency (GHz) 0 5 10 15 20 25 Phase ( Degree ) -180 -90 0 90 180

16

(5) Measured group delay of S₂₁ and S₃₁

Fig. 8(e)

The solid curve is the group delay out of port 2; dashed curve is out of port 3. (6) Noise figure

Fig. 8(f) Solid curve: the simulated result; Dashed curve: the measured result.

Frequency (GHz) 0 5 10 15 20 25 Noi se Fig ur e (dB ) 0 5 10 15 20 Frequency (GHz) 0 5 10 15 20 25 Gr ou p Dela y ( nSe c) 0.0 0.1 0.2 0.3 0.4

17

(7) Measured magnitude imbalance

Fig. 8(g)

(8) Measured phase imbalance

Fig. 8(h) Frequency (GHz) 0 10 20 30 M a g n itu d e Im b a la n ce ( d B) 0 1 2 3 4

Frequency (GHz)

0 10 20 30 Phase Imbalance (D egree ) 0 1 2 3 4

18

Fig. 8(a) shows the simulated results. The flat gain is about 7dB and the input and output return losses are below -10dB in the whole bandwidth. Fig. 8(b) shows the on-wafer measured S-parameters. The flat gain is about 7.5dB and the input and output return losses are below -10dB in the whole bandwidth.

Validity of this circuit’s wideband performance is vindicated by the overlapping S₂₁ and S₃₁ curves in DC–20GHz. The degradation of S₂₃ for frequency below 7GHz is due to the finite impedance of C_d. When a 100pF off-chip bypass capacitor is added, isolation between output ports will be better than 30dB in DC–20GHz as shown in Fig. 8(c). The solid curve #1 is the simulated results, The dashed curve #2 is the measured output port isolation S₂₃ without off-chip capacitor on the drain bias pad; the dotted curve #3 is with 100pF off-chip capacitor.

Fig. 8(d) shows the phase of S₂₁ and S₃₁. Fig. 8(f) is the noise figure, which is around 8dB across the whole bandwidth but is increasing for frequency below 2GHz. If a resistive feedback scheme is used to replace the 50Ω input loading resistor Rg, the low-frequency noise figure can be reduced

[7]. Fig. 8(g) and Fig. 8(h) show the magnitude and phase discrepancy of the two output ports where the magnitude imbalance is defined as the absolute value of 20∙Log(|S21/S31|), and the phase imbalance in degree is defined as the

19

(9) Linearity

Fig. 9

Fig. 9 #1-#4 is the gain relatively, or more exactly, S₂₁, versus the input power at 0.7, 10, 15, and 20GHz, and their input-referred 1dB compression point is -3.7, -6.3, -10, and -10.5dBm, respectively.

3.5 Conclusion

A DC–20GHz active power divider using 0.18μm CMOS process has been designed and measured here. It has two identical outputs with superb isolation in between, and good matching for the input and output ports. The averaged noise figure is 8dB and the input-referred 1dB compression point is -10dBm at 15GHz. A further improvement of its noise performance and linearity will be our design goals in the near future.

Input Power (dBm) -40 -30 -20 -10 0 Ga in (dB) 0 2 4 6 8 10 12

1

2

3

4

20

Chapter4 DC-40GHz Splitter Amplifier

4.1 Architecture Analysis

Fig. 10

The DC-40GHz splitter amplifier has the similar architecture to the DC-20 GHz splitter amplifier based on the distributed amplification. This circuit involves three amplification stages to achieve higher gain. The principle improvements are extending input matching bandwidth by using the coupling inductors and decreasing noise figure at low frequency by current reuse replacing of 50-Ω resistance .

21

4.2 Coupling Inductors

Fig. 11

Begin from the T-networks of L_g and parasitic capacitor C_g , which is shown as Fig. 11., the equivalent circuit would be like the left side of the equal sign while assigning M-value to the coupling magnitude. The equivalent L-value and C-value are

,

Once the M-value is positive (M > 0), the denominator in the frequency formula will decrease and obtain the bigger value. It definitely means that the bandwith has been broad and solve the input bandwidth limitaion caused by twice parasitic capaitors. Moreover, using the coupling inductors can reach the inductance in samller size, minimizing the area.

 

_

 

_{ }

_









C

C

C

g g g

M









2

1

L

g

 



L

g



M



_

₀

_.

₅

 

 

_{ }































g g g g g g

L

M

C

L

C

L

f

2

1

1

1











 

  f_g

22

4.3 Current-Reuse Termination

Fig. 12(a)

The gate termination adopts a current reuse replacing of a simple 50-Ω resistance while current reuse can provide a 50-Ωinput impedance in whole band. Current reuse consist of a PMOS and a NMOS transistors with a feedback resistance. The big resistance value will be plus into the denominator of noise formula so that the noise figure is able to decline.

Fig. 12(b)

Solid curve: simple 50-Ωresistance; dashed curve: current reuse

As shown in Fig. 12(b), noise figure can decrease effectively below 5GHz band. Another advantage of using current reuse is that it can provide gate voltage for transistors without adding another set of voltage so as to promote integrity.

Frequency (GHz) 0 5 10 15 20 Ampl if ier 's N ois e Figur e (dB) 0 2 4 6 8 10

23

4.4 Manufacturing in CMOS Process

Fig. 13

Fig. 13 shows the photograph of the divider circuit, which is fabricated using commercial 90nm CMOS process and the chip size is 0.8×0.98mm2. The layout has differences at coupling inductors and DC-bias metal line. With supply voltage V_d = 2Volt and I_d = 50Amp, the total power consumption is 100mWatt; the gate bias voltage Vg is 0.8Volt with negligible current in this

24

4.5 The Simulated and Measured Results

(1) S-parameters: V_DD=1.5 Volt, V_g=0.65 Volt, P_DC=70mW

Fig. 14(a)

(2) Measured S-parameters: V_DD=2 Volt, V_g=0.8 Volt, P_DC=100mW

Fig. 14(b) Frequency (GHz) 0 10 20 30 40 50 dB -20 -10 0 10 20

S

21

、S

31

S

22

、S

33

S

11

Frequency (GHz)

0 10 20 30 40 50 dB -20 -10 0 10 20

S

21

、S

31

S

22

、S

33

S

11

25

(3)Simulated Isolation (S₂₃):

Fig. 14(c)

(4) Simulated Noise Figure :

Fig. 14(d) Frequency (GHz) 0 10 20 30 40 50 dB -80 -60 -40 -20 0

S

23 Frequency (GHz) 0 10 20 30 40 50 dB 0 5 10 15 20

26

Chapter5 The Measurement Concerns

The measure items include S-parameters, noise figure and P1dB. It needs 4-ports measurement system as shown in Fig. 15(a). The DC-block capacitor between network analyzer and probe has been considered in simulation. The range is 0.1-20GHz with 201points, sampling 128 times. Input power is -20 dBm. The network analyzer type is HP 8510C.

Fig. 15(a)

Fig. 15(b)

As shown in Fig. 15(b), the input port connects the signal generator Agilent E8247C. By sweep the input signals and observe the graph on the network analyzer, we can find out the P1dBs corresponding frequency.

27

Chapter6 References

[1] Y. Zhang, X. Tang. Y. Fan, B. L. Ooi, M. S. Leong, and M. Koen, “A miniaturized wideband Wilkinson power divider,” 2008 Electronics

Packaging Technology Conference, pp. 271-274, December 2008.

[2] S. W. Wang, and L. Zhu, “Ultra-wideband power dividers with good isolation and sharp roll-off skirt,” 2008 Asia-Pacific Microwave Conference, pp. 1-4, December 2008.

[3] A. Safarian, L. Zhou, and P. Heydari, “CMOS distributed active power combiners and splitters for multi-antenna UWB beamforming transceivers,”

IEEE J. Solid-State Circuits, vol. 42, no. 7, pp. 1481-1490, July 2007.

[4] C. S. Aitchison, “The intrinsic noise figure of the MESFET distributed amplifier,” IEEE Trans. Microwave Theory and Tech., vol. MTT-33, no. 6, pp. 460-466, June 1985.

[5] X. Guan, and C. Nguyen, “Low-power-consumption and high-gain CMOS distributed amplifiers using cascade of inductively coupled common-source gain cell for UWB systems,” IEEE Trans. Microwave Theory and Tech., vol. 54, no. 8, pp. 3278-3283, August 2006.

[6] J. C. Chien, and L. H. Lu, “40-Gb/s high-gain distributed amplifiers with cascaded gain stage in 0.18μm CMOS,” IEEE J. Solid-State Circuits, vol. 42, no. 12, pp. 2715-2723, December 2007.

[7] S. Kimura, and Y. Imai, “0–40GHz GaAs MESFET distributed baseband amplifier IC’s for high-speed optical transmission,” IEEE Trans.

Microwave Theory and Tech., vol. 44, no. 11, pp. 2076-2082, November