An output buffer for 3.3-V applications in a 0.13-mu m 1/2.5-V CMOS process

An Output Buffer for 3.3-V Applications in a 0.13-

m

1/2.5-V CMOS Process

Shih-Lun Chen, Student Member, IEEE, and Ming-Dou Ker, Senior Member, IEEE

Abstract—With a 3.3-V interface, such as PCI-X application,

high-voltage overstress on the gate oxide is a serious reliability problem in designing I/O circuits by using only 1/2.5-V low-voltage devices in a 0.13- m CMOS process. Thus, a new output buffer re-alized with low-voltage (1- and 2.5-V) devices to drive high-voltage signals for 3.3-V applications is proposed in this paper. The proposed output buffer has been fabricated in a 0.13- m 1/2.5-V 1P8M CMOS process with Cu interconnects. The experimental results have confirmed that the proposed output buffer can be successfully operated at 133 MHz without suffering high-voltage gate-oxide overstress in the 3.3-V interface. In addition, a new level converter that is realized with only 1- and 2.5-V devices that can convert 0/1-V voltage swing to 1/3.3-V voltage swing is also presented in this paper. The experimental results have also confirmed that the proposed level converter can be operated correctly.

Index Terms—Gate-oxide reliability, level converter,

mixed-voltage I/O, output buffer.

I. INTRODUCTION

A

S the semiconductor process is scaled down, the thick-ness of the gate oxide becomes thinner in order to de-crease the core power supply voltage (VDD) [1]. This results in lower power consumption. However, the board voltage (VCC) is still kept as high as 3.3 V (or 5 V), such as in a PCI-X interface [2]. There are three problems on a MOSFET when the operating voltage is higher than its normal voltage. Higher drain-to-source voltage may cause serious hot-carrier ef-fect, which results in long-term lifetime issue [3]. Drain-to-bulk p-n junction breakdown may occur if the operating voltage is too high. High-voltage overstress across the thinner gate oxide could also destruct the gate oxide [4], [5]. Therefore, I/O cir-cuits must be designed carefully to overcome these problems, especially high-voltage gate-oxide overstress [6]–[10].

Recently, dual-oxide (thin oxide and thick oxide) processes have been supported by some manufacturing companies [11]–[13]. For example, the thin-oxide devices are 1- or 1.2-V devices, and the thick-oxide devices are 1.8-, 2.5-, or 3.3-V devices in a 0.13- m CMOS process [12], [13]. The thin-oxide devices are used to design digital circuits to decrease silicon area and power consumption. The thick-oxide devices are used

Manuscript received February 3, 2005; revised March 3, 2006. This work was supported in part by the National Science Council, Taiwan, R.O.C., under Contract NSC 95-2221-E-009-290. This paper was recommended by Associate Editor R. Puri.

The authors are with the Nanoelectronics and Gigascale Systems Laboratory, Institute of Electronics, National Chiao-Tung University, Hsinchu 300, Taiwan, R.O.C. (e-mail: mdker@ieee.org).

Digital Object Identifier 10.1109/TCSII.2006.883202

Fig. 1. Conventional tristate output buffer codesigned with thin- and thick-oxide devices.

Fig. 2. Conventional level converter codesigned with thin- and thick-oxide de-vices.

to design analog circuits to improve circuit performance or I/O circuits to avoid the gate-oxide reliability issue. Fig. 1 shows a conventional tristate I/O buffer codesigned with thin- and thick-oxide devices. As shown in Fig. 1, transistors P1 and N1 are thick-oxide devices, which can sustain the voltage level of VCC to avoid the gate-oxide reliability issue. Since the core circuits are operated at VDD, the voltage swing of signals IN, EN, and ENB is from GND to VDD. However, the voltage swing of the output signal is from GND to VCC. Thus, the level converter is required to convert the GND-to-VDD signal to a GND-to-VCC signal in order to prevent the high-voltage overstress across the core devices. The conventional level converter codesigned with thin- and thick-oxide devices is shown in Fig. 2, where transistors P1, P2, N1, and N2 are thick-oxide devices, but transistors P3 and N3 are thin-oxide devices. The voltage swing of signals IN and INB is from GND to VDD, whereas the voltage swing of signal OUT is from GND to VCC. If the voltage gap between VDD and VCC is too large, such conventional level converter cannot be operated correctly. Some techniques have been reported to solve this problem [14]–[17]. The use of precharging devices to increase the pull-up capacity was reported in [14]. A boosting technique was reported to pump the input voltage swing of the level con-verter [15], [16]. The zero-Vt (also called native-Vt) n-channel MOS (NMOS) transistor was used to design the level converter for higher driving capability [17].

Fig. 3. New proposed output stages realized in a 0.13-m 1/2.5-V CMOS process with (a) all 2.5-V normal-Vt transistors and (b) 2.5-V native-Vt tran-sistor N2 and 1-V normal-Vt trantran-sistor N1.

Due to the high-integration trend of system-on-chip, a system including digital circuits and analog circuits may be integrated into a single chip. For example, the digital part of a chip is de-signed with 1-V devices to decrease its power dissipation, the analog part is designed with 2.5-V devices to improve the circuit performance, and the chip-to-chip interface is a 3.3-V PCI-X in-terface in a 0.13- m 1/2.5-V CMOS process. In [18], an input buffer in a 0.13- m 1/2.5-V CMOS process is reported to re-ceive 3.3-V input signals. However, how to drive 3.3-V output signals by 1- and 2.5-V devices was not reported yet.

In this brief, a new output buffer is designed in a 0.13- m 1/2.5-V CMOS process to drive 3.3-V output signals without the gate-oxide reliability issue [19]. Besides, a new level converter that can convert 0/1-V signals to 1/3.3-V signals is also pre-sented in this paper. The proposed output buffer and level con-verter have been successfully verified in the 0.13- m 1/2.5-V CMOS process without gate-oxide reliability issue.

II. NEWPROPOSEDOUTPUTBUFFER

A. Output Stage Design

Because the proposed output buffer is designed in a 0.13- m 1/2.5-V CMOS process, the gate-to-source and gate-to-drain voltages of the thin-oxide devices cannot exceed 1 V. The gate-to-source and gate-to-drain voltages of the thick-oxide devices cannot exceed 2.5 V. However, the VCC of the PCI-X specification is 3.3 V [2]. Therefore, the output stage must be stacked, and the gate voltages must be well controlled to prevent high-voltage overstress on their gate oxides. The new proposed output stages are shown in Fig. 3. To avoid body effect, which results in lower driving capacity, the bulks of the transistors in Fig. 3 are connected to their sources individually. In Fig. 3(a), the pull-up and pull-down paths have two stacked 2.5-V p-channel MOS (PMOS) transistors (P1 and P2) and 2.5-V nMOS transistors (N1 and N2), respectively. Since the gate voltages of transistors P2 and N2 are biased at VDD (1 V), the extra bias generator is not required. Because the gate voltages of transistors P2 and N2 are biased at 1 V, the gate-to-source voltages and the gate-to-drain voltages of transistors P2 and N2 do not exceed 2.5 V. The maximum and of transistors P2 and N2 are about 2.3 V .

Transistors P2 and N2 are used to protect transistors P1 and N1 against the high-voltage gate-oxide overstress, respectively. However, the source voltage of transistor P1 is 3.3 V. In this design, the minimum voltage level of signal PU cannot be lower than 0.8 V . The voltage swing of signal PU can be designed between 1 V (VDD) to 3.3 V (VCC) to control the gate of transistor P1. Hence, a level converter that can convert 0/1-V voltage swing to 1/3.3-V voltage swing is demanded for the proposed output buffer.

In Fig. 3(a), transistors N1 and N2 are 2.5-V normal-Vt nMOS transistors with a threshold voltage of 0.6 V, which is still too high for high-speed operation when the of the normal-Vt nMOS transistor is only 1 V. Hence, the driving capability of the pull-down path in Fig. 3(a) needs to be im-proved. Therefore, a modified version of the output stage is shown in Fig. 3(b). Transistor N2 in Fig. 3(b) is a 2.5-V na-tive-Vt nMOS transistor, which has a threshold voltage of 0.1 V [20]. Transistor N1 in Fig. 3(b) is a 1-V nMOS transistor. The native-Vt nMOS transistor is one of the standard devices in a 0.13- m CMOS process without extra process modification [12]. Therefore, the driving capability of the output buffer in Fig. 3(b) can be increased. Because the gate of transistor N2 is biased at 1 V, transistor N1 in Fig. 3(b) can be safely operated without suffering high-voltage gate-oxide overstress. However, since transistor N2 is a native-Vt nMOS transistor, the subthreshold leakage current could be serious. If the voltage on node OUT in Fig. 3(b) is 3.3 V, the subthreshold current of transistor N2 may occur. Thus, the voltage on node A in Fig. 3(b) may exceed 1 V. An extra pMOS transistor P3 is added in Fig. 3(b) to keep the maximum voltage on node A at 1 V. When signals PU and PD are at logic “0” (1 and 0 V), the voltage on node OUT is VCC (3.3 V). Because signal PD is at 0 V, transistor P3 is turned on to keep the voltage on node A at 1 V. Hence, the high-voltage gate-oxide overstress caused by the subthreshold leakage of transistor N2 can be avoided. Because transistor P3 is a weak device that keeps the voltage on node A at 1 V, it can be a 2.5-V normal-Vt pMOS transistor. Fig. 4 shows the simulated waveforms of the output stages in a 0.13- m CMOS process with 1- and 2.5-V devices. In this simulation, the transistor sizes of these two output stages are kept the same. As shown in Fig. 4, the driving speed of the output stage in Fig. 3(b) is better than that of the output stage in Fig. 3(a).

B. Level Converter Design

Fig. 5 shows the new proposed level converter that can con-vert 0/1-V voltage swing to 1/3.3-V voltage swing. In Fig. 5, the bulks of the transistors are connected to their sources, re-spectively, because of the body effect issue. Transistors N1A and N1B are 1-V normal-Vt nMOS transistors, whereas tran-sistors N2A and N2B are 2.5-V native-Vt nMOS trantran-sistors, so the driving capability can be increased. The other transistors are all 2.5-V normal-Vt transistors. Transistors P3A can keep the voltage on node A1 at 1 V when the voltage on node B1 is 3.3 V. Similarly, transistor P3B is used to keep the voltage on node A2 at 1 V when the voltage on node B2 is 3.3 V. The voltage swing of input signals IN and INB is from 0 to 1 V. When signal IN is 1 V and signal INB is 0 V, the voltage on node B1 is pulled

Fig. 4. Simulated waveforms of the output stages.

Fig. 5. New proposed level converter that can convert 0/1-V signal swing to 1/3.3-V signal swing.

down to 0 V, and transistor P5A is turned on. After transistor P5A is turned on, the voltage on node OUTB is pulled down to 1 V, and then, transistors P4B and P1B are turned on. Therefore, the voltages on nodes OUT and B2 are both pulled up to 3.3 V.

When signal IN is 0 V and signal INB is 1 V, the voltage on node B2 is pulled down to 0 V, and transistor P5B is turned on. After transistor P5B is turned on, the voltage on node OUT is pulled down to 1 V, and then, transistors P4A and P1A are turned on. Therefore, the voltages on nodes OUTB and B1 are both pulled up to 3.3 V.

Because using pMOS transistors to pull down nodes OUT and OUTB could be too slow, two cross-coupled nMOS transis-tors N3A and N3B are added to increase the pull-down speed. Fig. 6 shows the simulated waveforms of the new proposed level converter in a 0.13- m 1/2.5-V CMOS process. The pull-down speed of the proposed level converter with transistors N3A and N3B is faster than that of the level converter without N3A and N3B.

C. Whole Output Buffer

Fig. 7 depicts the whole output buffer, which consists of an output stage, a level converter, a tristate control circuit, and two

Fig. 6. Simulated waveforms of the new proposed level converter with or without transistors N3A and N3B.

Fig. 7. Whole output buffer that drives the 3.3-V output signal in the 0.13-m CMOS process with only 1- and 2.5-V devices.

Fig. 8. Circuit implementation to realize the (a) tristate control circuit, (b) INV1, and (c) INV2 in the whole output buffer.

kinds of taper buffers (taper buffer 1 and taper buffer 2). In Fig. 7, a CMOSNANDgate and aNORgate are used to imple-ment the tristate control circuit. When control signal EN is 0 V and control signal ENB is 1 V, the output buffer is in the high-impedance state. When control signal EN is 1 V and con-trol signal ENB is 0 V, the output buffer drives the output pad according to signal IN from the core circuits. Fig. 8(a) shows

Fig. 9. Simulated waveforms of the proposed output buffer operating with a 133-MHz 3.3-V output signal in a 0.13-m CMOS process with only 1- and 2.5-V devices.

another tristate control circuit, which consists of only six tran-sistors [21]. Compared with the traditional tristate control cir-cuit in Fig. 7, the circir-cuit in Fig. 8(a) may have smaller silicon area and input capacitance. Thus, the tristate control circuit in Fig. 8(a) can be used to replace the traditional tristate control circuit in Fig. 7. The output stage of this whole output buffer is the same as that in Fig. 3(b). The level converter that can transfer the signal swing from 0/1 to 1/3.3 V has been shown in Fig. 5. Taper buffer 1 and taper buffer 2 are demanded to drive the output stage because the transistors in the output stage are large-size devices. Because the voltage swing of signal PU is from 1 to 3.3 V, the INV1 in taper buffer 1 is shown in Fig. 8(b). The pMOS and nMOS transistors of INV1 are 2.5-V normal-Vt devices. Because the voltage swing of signal PD is from 0 to 1 V, the INV2 in taper buffer 2 is shown in Fig. 8(c), where the pMOS and nMOS transistors of INV2 are 1-V normal-Vt tran-sistors. In order to keep signals PU and PD in phase, the delay of taper buffer 1 and the level converter must be adjusted equal to that of taper buffer 2. In Fig. 8, the bulks of the transistors are connected to their sources, respectively, because of the body effect.

Fig. 9 shows the simulated waveforms on nodes IN, OUT, PU, and PD in the proposed output buffer operating with a 133-MHz 3.3-V output signal in a 0.13- m 1/2.5-V CMOS process. The output load is 10 pF in this simulation. Because the parasitic inductance (15 nH) of the bond wire has also been included in this simulation, the overshoot and undershoot of the output waveform can be found in Fig. 9. Table I shows the other sim-ulation results of the proposed output buffer. The delay times are measured from the input signal (IN) of 0.5 VDD (0.5 V) voltage level to the output signal (OUT) of 0.5 VCC (1.65 V) voltage level. As shown in Table I, the simulated rising delay time and falling delay time are 1.15 and 1.08 ns, respectively. The output rising time and falling time are defined from 0.1 VCC (0.33 V) to 0.9 VCC (2.97 V) and from 0.9 VCC (2.97 V) to 0.1

TABLE I

SIMULATIONRESULTS OF THEPROPOSEDOUTPUTBUFFER

Fig. 10. Layout of the whole output buffer in a 0.13-m 1/2.5-V CMOS process with Cu interconnects.

Fig. 11. Measured waveforms of the new proposed level converter, which con-vert the 0/1-V signal to a 1/3.3-V signal.

VCC (0.33 V), respectively. As shown in Table I, the simulated and are 0.85 and 0.73 ns, respectively. The output low current is defined when the output voltage is at 0.1 VCC (0.33 V). The output high current is defined when the output voltage is at 0.9 VCC (2.97 V). As shown in Table I, the simulated and are 59.3 and 39.4 mA, respectively. The simulated power consumption is 29.77 mW when the proposed output buffer is operated at 133 MHz with a 10-pF capacitive load at the pad. In this simulation, the proposed output buffer successfully drives the pad according to the input signal IN.

III. EXPERIMENTALRESULTS

The proposed output buffer has been fabricated in a 0.13- m 1/2.5-V 1P8M CMOS process with Cu interconnects. Fig. 10 shows the layout of the proposed output buffer. The layout area of the proposed output buffer is around m m. Be-sides, the test chip also includes the stand-alone level converter to verify its logic functions and voltage levels. Fig. 11 shows the measured waveforms of the new proposed level converter. As

Fig. 12. Measured waveforms of the proposed whole output buffer operating with a 133-MHz 3.3-V output signal in a 0.13-m CMOS process with only 1-and 2.5-V devices.

shown in Fig. 11, the proposed level converter can successfully transfer the voltage swing from 0/1 to 1/3.3 V. Fig. 12 shows the measured waveforms of the proposed whole output buffer oper-ating with a 133-MHz 3.3-V output signal. As shown in Fig. 12, the proposed output buffer can successfully drive the output pad without gate-oxide overstress. Besides, the measured and of the proposed output buffer are 69.2 and 44.1 mA, re-spectively. Due to process variation, the measured and are slightly different from the simulated and .

IV. DISCUSSION

The hot-carrier degradation and drain-to-bulk breakdown issues are the other reliability issues in the high-voltage-tol-erant circuits. To avoid the hot-carrier degradation, the drain-to-source voltage of the device operated in the saturation region cannot be higher than the normal operating voltage [3]. For example, the of the 1-V (2.5-V) device cannot be higher than 1 V (2.5 V). The maximum of 1- and 2.5-V devices in the proposed output buffer are about 1 and 2.3 V, respectively. Thus, the proposed output buffer not only considers the gate-oxide reliability issue but also the hot-carrier degradation issue. In general, the drain-to-bulk breakdown voltage is at least twice the normal operating voltage in the standard CMOS process [12], [13]. Hence, the drain-to-bulk breakdown issue can be ignored in the proposed output buffer.

V. CONCLUSION

An output buffer realized with low-voltage devices to drive high-voltage output signals is presented in this paper. The proposed output buffer has been fabricated in a 0.13- m 1/2.5-V CMOS process to drive 3.3-V signals without suffering high-voltage gate-oxide overstress. The experimental results have shown that the proposed output buffer can be successfully operated with a 133-MHz 3.3-V output signal. Moreover, a new level converter that can convert 0/1-V signal swing to 1/3.3-V

signal swing, has also been verified in this paper. The proposed output buffer and level converter are suitable for mixed-voltage interface applications in the nanometer CMOS processes.

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