Performance and reliability evaluations of P-channel flash memories with different programming schemes

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Performance and Reliability Evaluations of P-Channel Flash Memories

with Different Programming Schemes

Steve

S. Chung,

S.

N. Kuo,

C. M. Yih, and T.,

S. Chao*

Department of Electronic Engineering. National Chiao Tung University, Taiwan,

R.O.C.

*

National Nan0 Device Lab., Hsinchu. Taiwan, R.O.C. Abstract

In this paper, a complete study

of

the cell reliability

based on a unique oxide damage characterization for two different programming schemes of p-channel flash cell will be

presented. These two programming schemes are Channel Hot Electron (CHE) injection or Band-to-Band (BTB) tunneling induced hot electron injection. Degradation of memory cells after PIE cycles due to the above oxide damages has been identified. It was found that both Nit and Qox will dominate the device degradation during programming. Although p-flash cell has high speed performance by comparing with n-flash cell, extra efforts are needed for designing reliable p-channel flash cell by appropriate drain engineering or related device optimization.

1. Introduction

Owing to its low voltage, low power and high speed programming features, p-channel flash memories [ 1-21 have been evolved as a promising cell for real applications in the future. In a certain design of p-channel flash cells, programming of the cell can be achieved either by channel-hot-hole impact ionization induced channel-hot-electron injection (CHE) or by band-to-band (BTB) tunneling induced hot-electron injection at the drain side. Erasing of the cell can be ac-

complished by electron channel Fowler-Nordheim (F-N) ejec- tion from the floating gate. Here, both programming schemes, CHE and BTB, will generate the so-called oxide damages, which include the interface state Nit and the oxide trap charge Qox. These damages will give rise to serious reliability problems such as programming time delay, operation window closure, and data retention etc. for p-channel flash memories. In the past, the correlation of these program induced damages with device performance and reliability has been reported [3-41 and completely studied

[5]

for n-channel flash memory cells. However, thus far, it has never been reported for p-channel flash memories with different program schemes and so it is still not clear which programming scheme has better performance and reliability.

In this paper, for the first time, a comparative study of p-channel flash memory performance and reliability will be presented in details for two different programming schemes. The understanding of programming characteristics degradation mechanism for these two different programming methods will be made based a unique oxide damage characterization tech-

nique that we developed in

[SI.

Moreover, the comparison of

reliability between 11- and p-channel flash memory cells after

long term

P/E

(program/erase) cycles will also be discussed.

2. Measurement

and

Characterization

Conventional double-polysilicon stacked-gate p-channel flash cells were uset3 in this study. The tunnel oxide thickness is 70A. The effective interpoly dielectric thickness with ONO structure is about

21MA.

The measured gate coupling ratio of flash cell is about 0.6. In addition, the p-MOSFET dummy cell for oxide dama,ge characterization has same tunnel oxide thickness, drawn channel length 0.55 pm, and width 100 pm.

Performance and reliability of two different program schemes shown in Fig. 1

are

evaluated. The hot carrier stress conditions were performed for the p-MOSFET dummy cells, i.e., the channel-halt-electron (CHE) stress at the maximum gate current (IGSnax) bias and the BTB stress at the bias with maximum injection efficiency.

The gate cuments and injection efficiencies ( I d s m for CHE and IG/ID for BTB) of two programming schemes are shown in Figs. '2 and 3, for comparison. For CHE programming, the maximum gate current and the maximum injection efficiency are obtained at a gate voltage around the device threshold voltage. On the other hand, for BTB scheme, the gate current increases with increasing VGD and the maximum injection efficiency is located at VD= -6V and VG= 4V. Here, we see that BTB scheme shows one order higher gate current and injection efficiency as compared to that of CHE. In Fig. 4, comparison of the transient characteristics of p-channel flash cellls for CHE and BTB schemes is shown. It reveals that BTB scheme exihibits higher programming speed at the same drain bias than that of CHE. Fig. 5 gives a comparison

of

the measured gate current degradation with

stress time for CHt and BTB schemes. It was found that BTB scheme degrades faster than the CHE one. This is consistent with the transient characteristics shown in Fig. 4. In short, BTB scheme has the advantage of high speed performance but with the drawback of a poorer reliability since BTB will generate larger oxide damages described as follows.

3. Results and Discussions A . Characterization of Oxide Damages Ni, and

Q,,

The oxide damage characterization method that we developed in

[5]

as also illustrated in Fig. 6 is used. The gated diode currents in combination with a special detrapping tech-

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nique is used for the determination of oxide damage lateral distributions. Once we have the oxide damages, memory cell performance and the

cell

degradation mechanisms can be fully explored. It is known that when the gated-diode measurement technique

was

first developed, it can only be used to character- ize Nit. However, the localized damages of Nit and

Q,,

exist simultaneously for both stressed conditions at BTB and CHE stress biases. Also the measured IGD will be affected significantly by the created oxide charge as illustrated in Fig. 6(b). Therefore, we use the measured

ED

before and after the stress

and develop a method to separate Q, from Nit as the follow- ing steps: (1) Measure the gated-diode (IGD) current for a fresh p-MOSFET dummy cell (curve (1)). (2) After hot-electron

stress, we have IGD (curve (2)), which includes both Nit and Q,. (3)

Use

a neutralization step (or detrapping step) (@VD= 2.5V, VG= -3V for 50 sec in this study for CHE stress) to eliminate the effects of hot-electron injection induced Q,,, (curve (3)). The difference between curves (1) and (3) gives

Nit, while the difference between curves (2) and (3) gives Qox. Not only the experimental procedure as above, but also simulation are required to accurately determine the spatial distributions of Nit and Qox. Profiling of Nit and Q,, can be obtained from equations listed in Table 1. In Fig. 6(a) for gated-diode current measurement configuration, a small drain bias is applied to forward bias the drain-substrate junction. It makes sure that the measured IGD contributes to the electron and hole recombination process. The parameters @e and

ah

represent the quasi-Fermi levels for electron and hole respec- tively which coincide with the intrinsic level Ei. Ax between the locations of 0, and

ah

is the overlap region where electron-hole recombination occurs and can be obtained from simulation. Fig.

7.

gives the measured device gated-diode and GIDL currents for fresh, after CHE stress, and after the detrapping. Here, it should be noted that in the measurement as above, GIDL currents are used as a monitor of the detrapping procedure to make sure that Q, is eliminated in step (3) such that the detrapping step will not generate additional oxide damages.

For the cell after long term CHE programming in Fig. l(a), the extracted lateral distributions of both Nit(x) and Qox(x) are illustrated in Fig. 8 (stressed @VGS=l,lv and V D ~ = - ~ V for 3000s). It was found that both Nit(x) and Qo,(x) are localized inside the gate-drain overlap region. By taking the extracted oxide damages into account, the simulated programming characteristics of p-channel flash cells with and without oxide damages can be obtained as given in Fig. 9.

Retardation of programming time is observed at a constant threshold voltage level. Moreover, the individual contribution of generated Nit and Q,, to the programming characteristics is also shown in Fig. 9. With the same programming pulse, we see that the stress generated Nit will dominate the program window closure after long term CHE programming. For the cell after long term BTB programming, the extracted distributions

of

Nit(x) and Qo,(x) are shown in Fig. 10 (stress @VG= 4V and VD=-6V for 3000s). From Fig. 10, we see that the oxide damages are much larger than those generated using CHE scheme shown in Fig. 8. It further shows in Fig. 11

that the induced oxide trap charges and interface states significantly and seriously affect the programming speed. The contribution of Nit to programmed threshold voltage variation is larger than that of Q,, although the generated

Q,,

is greater

than

Nit. However,

the

BTB scheme has one advantage of larger operation window when comparing Figs. 9 and 11.

B . Comparison of the Cell Reliabilities for CHE and BTB Programming Schemes

To compare the performance of a p-channel flash cell with different programming schemes, several results are given as follows. Although BTB scheme has poor gate current degradation characteristics, optimization of this degradation can be achieved by varying the BTB biases as shown in Fig. 12 with fixed V ~ p 1 0 V . In Fig. 12,

we

see that the smaller the drain bias, the lower the device gate current degradation. This implies that better reliability can be achieved by lower- ing the BTB drain bias. Further results given in Fig. 13 man- ifests that device with lower drain bias for BTB has better reliability. In other words, the programming speed depends largely either on interface states or on oxide trap charges. Therefore, a trade-off between programming speed and reliability for p-channel flash cells with BTB program should

be considered. Furthermore, the cell programming time as a function of P/E cycles are compared in Fig. 14 among

n-

and p-channel flash cells with different programming schemes. It shows that BTB has the fastest programming speed before cy- cling but has the worst time delay as a result of the largest oxide damages, while the delay is moderate for a

CHE

scheme in p-channel flash cell. Also, one interesting result is that n-

channel flash cell is much more reliable in this comparison. Initially, p-channel cell operates with faster speed but its speed will slow down due to the oxide damages after long term P/E cycles. Therefore, we conclude that the oxide damages, in particular Nit, which are the dominant degradation factor, should be suppressed either by drain-engineering or device optimization. A summary for the comparison of the p- flash cell performance is listed in Table 2.

4. Conclusions

In summary, several new issues have been addressed in this study: (1) Degradation of p-channel flash memory cells after P/E cycles due to oxide damages has been demonstrated. (2) It was found that both Nit and Q,, will dominate the device degradation during programming. (3) By comparing with n-channel flash cell, extra efforts are needed for improving p- channel flash cell design by drain-engineering or related device optimization, and (4) We provide a methodology for evaluat- ing cell reliability of either p-channel or n-channel flash memory. This provides us useful information for designing high performance and reliable flash memories.

Acknowledgments The authors would like to appreciate the financial support from the National Science Council, Taiwan, R.O.C. under grant NSC85-2215- E009-053.

11.7.2

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References

[l] C. C.-H. Hsu et al., Exf. A h . SSDM, Tsukuba, p. 140.1992.

[2] T. Ohnakado et al., in IEDM Tech. Dig., p. 279.1995. [3] Jack Z. Peng et al., Proceedings ofIRPS, p. 154.1994. [4] S. Yamada et al., in IEDM Tech. Digesf, p. 23, 1993. [5] S. S. Chung et al., in Tech. Dig. Symp. VLSI Technology,

June 6-12. Kyoto, Japan, p. 111,1997.

Table 1 Gated-diode current model for profiling Nit and Qr

v m < o

v m > o

P

0

t

Fig. 1 The schematic illustration of two different programming schemes

E

-4

5 $

-2

3

-1

t

v) -3 0 m

>

c C O i

Pro'gramming Time (sec)

Fig. 4 Comparison of the transient characteristics for CHE programming and BTB, programming.

100 I

1

i

o3

1

60- ' " " "

1 o2

Stress Time (sec)

of a pchannel flash cell. Channel hot Electron (CHE) programming and Fig. 5 The measured gate current degradation with stress time for Band-to-band (BTB) tunneling induced hot electron programming. CHE programming and1 BTB programming.

n

5

I O " 1 I 3 IO'* II) m U 1 0 . ~

i o 4

2 e,

1 0 . ~

L

5 i o '

6

IO"

8'

t

3

10"O

g

i0.12 L 3 I O S n d 0 0 1 2 30 1 2 3 I 0.O

Gate Voltage, V, (V) Gate Voltage, V, (V)

Fig. 2 The gate and substrate currents at %= -6V and the calculated injection efficiency for CHE programming.

8

U

s

0 g

a

(I) Fresh

-

---

(2) stressed

----

(3) Dehlpped

t

-

Gate Voltage,

V,

Fig. 6 (a) Schematic diagram for gated-diode measurement. (b) The currents used for the calculation of Nit and Qx.

-Drain Voltage, V, (V) Drain Volatge, V, 01)

Fig. 3 The gate and drain currents at a fixed gate bias and the calculated injection efficiency for BTB programming.

Gate Vomage, V, (V) Drain Voltage, V, (V)

Fig. 7 The measured device gated-diode (left) and GIDL currents (right) for fresh, after 1 G , stress (CHE, Hot-Electron stress) ~ ~ and after the detrapping.

(4)

5 8

c

z

8

6 s

-5

-0 E;3 4 f A A 2

!*

0

s

0 2

.-

g l

6 0

0.52 0.54 0.56 0.58

Fig. 8 Extracted lateral distributions of Yt and Qx for devices with CHE stress at Qmaxfor 3000sec.

0.50 Position (pm)

Operation Window

AIG/IG

Programming Speed

Speed Retardation

Programming Time (sec)

Fig. 9 The simulated writing characteristics of a flash cell during the fresh, after the stress and after detrapping steps, in which Nit dominates the device degradation.

Large

Small

Serious

Moderate

Fast

Slow

Serious Moderate 1.50 0.52 0.54 0.56 Position (pm)

Fig. 10 Extracted lateral distributions of Nit and QX for devices with

BTB stress at the maximum injection bias for 3000 sec. in Fig. 3.

2

204

.

'

" . " "

.

' " " " ' ' , ' s * c u J

10 100 lo00 10000

Stress Time (sec)

Fig. 12 Comparison of gate current degradations for BTB stress

with different drain-gate bias programming.

Fig. 13 Comparison of the transient characteristics for the various

BTB stress conditions given in Fig. 12.

F

H CHE (0-Flash)

p

io.6 1

l l l l l " d * t l " ' d "'''''.! " " " ' d """"'

ioo

IO'

io2 io3

io4

io5

IO' IO'

P/E Cycles

Fig. 14 Programming speed after P/E cycles for p-channel cell with

BTB and CHE schemes, and for n-channel cell with CHE schemes.

1

CHE

Fig. 11 The simulated writing characteristics of a flash cell during the fresh, after the stress and after detrapping steps, in which Nit dominates the device degradation.

11.7.4

298-IEDM 97

Table 2 Comparison of the performance for p-channel flash cells with different programming schemes.