Cardiovascular events and methylphenidate use in Taiwan

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Quasi-static capacitance–voltage characterizations

of carrier accumulation and depletion phenomena

in pentacene thin ﬁlm transistors

Yi-Ming Chen, Chi-Feng Lin, Jiun-Haw Lee, JianJang Huang

*

Graduate Institute of Electro-Optical Engineering and Department of Electrical Engineering, National Taiwan University, 1 Roosevelt Road, Sec. 4, Taipei 106, Taiwan

Received 16 April 2007; received in revised form 24 July 2007; accepted 30 August 2007 Available online 23 October 2007

The review of this paper was arranged by Prof. E. Calleja

Abstract

We analyze charge accumulation and depletion behaviors from C–V curves at various gate voltages, ramp rates and sweep directions in pentacene OTFTs. The polycrystalline property of the pentacene layer has lead to carrier charge and discharge processes in the channel layer by a trap-controlled transport mechanism. We apply such processes to describe C–V profiles at various ramp rates. Hysteresis can be observed from C–V curves at faster ramp rates. The phenomenon can be attributed to the difference of the relaxation time of carrier trap and detrap processes. As the ramp rate becomes slower, hysteresis disappears since most carriers are able to interact with the gate stress. And beyond this ramp rate, the corresponding threshold voltages are then kept at constant values, despite the existence of traps. Furthermore, low-mobility carriers (mobile ions or impurities) participate in the charge accumulation and depletion when the ramp rate is even slower, which results in a skew of C–V profiles. Finally, we extend the C–V measurement to devices with different channel lengths.

Keywords: Organic semiconductor; Thin ﬁlm transistors; C–V measurement

1. Introduction

Over the past several years, organic thin ﬁlm transistors (OTFTs) have become popular due to their unique proper-ties compared with other semiconductor electronic devices

[1–3]. The fabrication of OTFT devices and circuits on large-area substrates is one of the cost advantages that typ-ical semiconductor cannot compete. In addition, low-tem-perature process of OTFTs on substrates with structural ﬂexibility makes all previous impractical semiconductor applications become real. For example, OTFT circuits can be applied to ﬂexible circuit boards for mobile phones,

digital cameras, and identiﬁcation tags, opening up a new arena for ﬂexible electronics in the consumer market.

Traditional device physics and formulas originally developed for conventional metal–oxide–semiconductor field effect transistors (MOSFETs) have found their diffi-culties in describing the electrical properties of OTFTs, especially in defining important parameters, such as thresh-old voltages, mobilities and contact resistivities, of these devices[4–6]. For example, the presence of trapping centers in the channel of an OTFT causes the trap-filling transition as the gate voltage is applied. This effect has resulted in a significant variation of the effective mobility and threshold voltage with gate signals. Thus, traditional physical inter-pretation of the capacitance–voltage (C–V) profiles of MOSFETs using a simple resistance–capacitance (RC) circuit model can not be applied to those of OTFTs.

*

Corresponding author. Tel.: +886 2 2366 3665; fax: +886 2 2367 7467. E-mail address:[email protected](J. Huang).

www.elsevier.com/locate/sse Solid-State Electronics 52 (2008) 269–274

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Typically, MOSFETs experience accumulation, depletion and inversion stages as the gate voltage swings at a low fre-quency [7]. However, the low-intrinsic-density organic material has prohibited the appearance of an inversion layer in most, if not all of them, OTFT capacitors[8]. As a result, the deﬁnition of the threshold voltage in an OTFT depends on the charge carriers injected from the contacts, not on the formation of an inversion layer in the channel

[9]. C–V measurements have been conducted by some groups to understand the carrier transport behavior in the channel layer of an OTFT[8–11]. For example, Schein-ert et. al. concluded that the measured C–V proﬁles of an OTFT depend on the direction of gate voltage swing [9]. The eﬀect of the hysteresis is related to the mobile ions, the kinetics of incomplete ionization and chemical reac-tions in the organic channel layer. Fujisaki et. al. also dem-onstrated a hysteresis in the C–V measurement [10]. They inferred that this phenomenon is caused by mobile ions in the insulators or by charge injections. Furthermore, Ryu et. al. calculated carrier mobilities based on quasi-sta-tic C–V (QSCV) and current–voltage measurements[11].

As for the carrier transport in the pentacene OTFTs, the polycrystalline property of the pentacene layer has lead to the development of the concept of the grain-boundary bar-rier with an energy distribution of the interfacial traps to describe the carrier transport [12]. The carrier density in the pentacene channel layer is related to the injection of carriers from source and drain electrodes, gate bias volt-ages and relaxation time of trap and detrap processes. In an accumulation mode TFT, since carriers interact with the trap and detrap processes, carrier mobilities vary over a wide range depending on the applied electric ﬁeld and stress duration.

In this paper, we conduct a full analysis of charge accu-mulation and depletion behaviors from the C–V curves at various gate voltages, ramp rates and sweep directions in pentacene OTFTs. We first describe the carrier charge and discharge processes in the channel layer using a trap-con-trolled transport mechanism. The carrier/mobile ion charge and discharge processes are then applied to describe C–V profiles at various ramp rates. Hysteresis can be observed from C–V curves at most ramp rates investigated. We next compare extracted threshold voltages at various ramp rates. And finally, we extend the C–V measurement to devices with different channel lengths for comparisons.

2. Device fabrication

Fig. 1 schematically shows the structure of a bottom gate OTFT. First, a 1500 A˚ metal layer of ITO (indium tin oxide) was sputtered on a glass substrate and patterned by photolithography as the gate electrode. Subsequently, the SiO2 dielectric layer was coated by PECVD (plasma

enhanced chemical vapor deposition) and the ITO source-drain electrodes were deposited on the surface of the pentacene ﬁlm with a shadow mask. We next deposited the channel layer with a 1000 A˚ thickness of pentacene. We

have designed OTFT devices with diﬀerent channel lengths (57 lm, 37 lm, 17 lm, respectively) but all with a ﬁxed channel width at 10,000 lm.

Once the samples were fabricated, we used an HP4155C precision semiconductor parameter analyzer to measure the electrical characteristics of OTFTs. To obtain a consis-tent performance of C–V proﬁles, the devices were placed in a box purged with dry air for several weeks. We moni-tored the IDS–VDS curves every 24 h until the day-to-day

variation is less than 5%. For the samples that C–V mea-surement was conducted later, they were sitting in the dry box longer than 80 days. Also, the variation of IDS–VDS

curves before and after the C–V measurement has to be less than 2% to be counted as a reliable OTFT device (see

Fig. 2). Even though the discussion of stability is not the main topic of this paper, the purpose of the test is to min-imize the potential variations of C–V proﬁles incurred from the device instability.

3. C–V measurement

Quasi-stable C–V (QSCV) measurement was also per-formed with an HP4155C semiconductor parametric

ana-Fig. 1. Schematic cross section of a pentacene OTFT.

Fig. 2. IDS–VDScurves of an OTFT before (solid lines) and after (stars) C–V measurement.

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lyzer. The voltage ramp proﬁle is illustrated inFig. 3. In this measurement, we set the step voltage to 3 V and vary TCint, the integration time for the capacitance

measure-ment. For instance, 3 V/33 ms indicates that the capaci-tance is extracted every 33 ms (TCint) with a step voltage

increase (or decrease) of 3 V. The capacitance is calculated from the diﬀerential charge required to change the capaci-tor voltage over TCintand is carried out automatically by

the machine. Detailed calculations of QSCV measurement can be referred from[13].

4. Results and discussions

We start from a faster gate signal swept in both direc-tions. As shown inFig. 4, at a ramp rate 3 V/33 ms, when the gate voltage is swept from negative to positive, holes and positive carriers will be ﬁrst induced and accumulated in the channel layer. On the other hand, while the gate bias is scanned from positive, the channel starts from the deple-tion region. Therefore, the capacitance of the device at an accumulation stage (VGS from 50 V to +49 V) is clearly

higher than that of the depletion stage (VGS from +50 V

to 49 V). Interestingly, the capacitance is kept at a

con-stant value for both cases, indicating carriers cannot accu-mulate (or deplete) in the channel as the gate voltage swings from positive (or negative). The phenomenon is attributed to a much longer relaxation time of the carriers in the polycrystalline pentacene channel layer than the duration of the scan. In other words, most carriers in the channel are not able to respond to the gate signal at 3 V/ 33 ms.

As the ramp rate decreases to 3 V/250 ms, the eﬀect of charge accumulation begins to take place for the case that the gate voltage sweeps from positive to negative, which means carriers can be accumulated during the measure-ment. FromFig. 4, the threshold voltage, VT, deﬁned from

the onset gate voltage of accumulation of carriers from depletion mode, is around 33 V at 3 V/250 ms from posi-tive to negaposi-tive direction. Such a ramp rate can not only recover carriers from depletion, but also allows positive carriers to accumulate if the attracting voltage is high enough. On the contrary, as the gate voltage is scanned in the reversed direction at 3 V/250 ms, the transition from the accumulation to depletion is not observed. In either sweep direction, the capacitance is higher at 3 V/250 ms than that at 3 V/33 ms, indicating that more carriers are able to respond to the slower gate signals.

We then further slow down the gate sweeping signals. Both sweep directions simultaneously show accumulation and depletion modes in Fig. 5, but the threshold voltages in both directions do not match each other as they should in typical MOSFETs. To understand the hysteresis of the C–V curves, we first look at the charge and discharge pro-cess in an OTFT channel. The transition from an accumu-lation to a depletion stage or vise versa is determined by the duration and strength of the gate voltages to stress and interact with carriers. The relationship of ramp rates and threshold voltages can be verified from QSCV profiles in

Figs. 4 and 5. When the device is scanned at 3 V/33 ms from the negative direction, the depletion can’t be seen in

step voltage 1st step 2nd step TCint start voltage last step stop voltage

Fig. 3. QSCV measurement sequence. In this measurement, capacitance is extracted by considering the additional charges at each step interval (TCint) and leakage currents before and after each step.

Fig. 4. QSCV curves for ramp rates between 3 V/33 ms and 3 V/250 ms.

Fig. 5. QSCV curves for ramp rates between 3 V/550 ms and 3 V/883 ms. Inlet: At 3 V/866 ms, QSCV curves at both sweep directions coincide and possess the same threshold voltage.

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Fig. 4since VGhas to be larger than +50 V to initiate the

transition from accumulation to depletion. As the ramp rate becomes slower, more and more carriers are able to respond to the gate voltages. Thus, less bias is required to deplete the channel and VT becomes smaller. On the

other hand, for the gate voltages scanned from positive to negative, the channel is initially at a depletion stage. VG has to be either (negatively) large enough or slow

enough to attract holes (or positive carriers) for the OTFT to be at an accumulation mode. Therefore, again, the tran-sition can’t be seen in the QSCV profiles until the scanning rate is slower. When we decrease the ramp rate to 3 V/ 866 ms, both scanning directions share the same threshold voltage (see the inlet of Fig. 5) even though the capaci-tances at depletion are slightly off. We believe 3 V/886 ms is the scanning rate that all of the carriers in the channel can respond to the gate signals. That is, even though the mobility of the carriers in the channel is strongly correlated to the trap and detrap processes during the stress of the gate signal, the scanning rate 3 V/886 ms scanning rate, is slower than the relaxation time of both processes and thus the carrier transition–depletion process of OTFTs behaves similar to that of conventional FETs. FromFigs. 4and5, for the QSCV curves with ramp rates between 3 V/33 ms and 3 V/886 ms, hysteresis behaves similar to that illus-trated in Fig. 6. At first, large hysteresis between both sweep directions can be observed for QSCV curves at a fast ramp rate. As the ramp rate decreases, the hysteresis becomes smaller until it disappears at 3 V/886 ms. The hys-teresis of the QSCV profiles can be attributed to the differ-ence of the relaxation time of the trap and detrap process in the polycrystalline pentacene layer.

As we decrease the ramp rate beyond 3 V/886 ms, both proﬁles at 3 V/3 s and 3 V/5 s inFig. 7demonstrate a skew in QSCV curves that are diﬀerent from those inFigs. 4and

5. Such phenomena can also be seen in[9]for OTFTs and in[14]for MOSFETs. In the MOSFET structure, the skew of the QSCV profiles suggests a shunt path from the leaky oxide layer or the alternative carrier flow starts to occur when the stress is strong enough [14]. However, in our OTFTs, the dependence of the slope of the QSCV profile

on the sweep direction implies that both positive and neg-ative carriers participate in the gate stress process. We believe that at such low ramp rates low-mobility carriers such as mobile ions or impurities start to interact with gate signals. For both sweep directions, in addition to the accu-mulation–depletion mode proﬁles in QSCV curves, low-mobility positive carriers are induced in the negative gate voltage range while low-mobility negative carriers are accu-mulated in the positive sweep range. Thus, as the gate volt-age is applied in either direction, an increase of capacitance can be seen in both 3 V/3 s and 3 V/5 s ramp rates.

We next plot VT as a function of QSCV ramp rates for

both sweep directions (seeFig. 8). In this ﬁgure, threshold voltages at 3 V/3 s and 3 V/5 s are discarded to avoid dis-tortion of the trend of VTwith ramp rates. Threshold

volt-ages are cramped at a constant value for ramp rates slower than 3 V/1000 ms, a little bit longer than the crossing point of 3 V/866 ms. The saturation of threshold voltages sup-ports the explanation that almost all the carriers are able to interact with gate signals beyond 3 V/886 ms 3 V/

Fig. 6. Schematic diagram that shows the trend of QSCV curves with the decrease of ramp rates at both sweep directions. Small arrows: gate signal sweep directions, and large arrow bars: direction of decrease of ramp rates.

Fig. 7. QSCV curves for ramp rates at 3 V/3 s and 3 V/5 s.

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1000 ms, despite the existence of trap and detrap processes. The transition between accumulation and depletion modes of OTFTs is similar to that of MOSFETs in this range since all of the carriers can be modulated by field effects. Furthermore, the offset of the saturated voltage between different sweep directions is attributed to the leaky shunt path from mobile ions or impurities.

We further extend our C–V measurement to OTFT devices with longer channel lengths. Since the thickness of the OTFT channel layer is unchanged, the proﬁle behaves similarly.Fig. 9a shows VT as a function of ramp

rates for a device with a channel length 37 lm andFig. 9b demonstrates that for the 57 lm case. From the ﬁgure, the threshold voltage becomes constant for ramp rates slower than 3 V/933 ms and 3 V/816 ms for devices with channel lengths 37 lm and 57 lm, respectively.

5. Conclusion

We analyze carrier charge and discharge behaviors from QSCV proﬁles at various gate voltages, ramp rates and

sweep directions in pentacene OTFTs. In an accumulation mode TFT, since carriers interact with trap and detrap pro-cesses, carrier mobilities vary over a wide range depending on the applied electric field and stress duration. During the stress, hysteresis can be found when most carriers in the channel are not able to respond to the scanning gate sig-nals. The hysteresis is attributed to the difference of the relaxation time between the trap and detrap process in the polycrystalline pentacene layer. For OTFTs with a channel length 17 lm, the threshold voltages of both sweep directions coincide at 3 V/886 ms. The threshold voltages are then kept at constant values, indicating that all of the carriers in the channel can respond to the gate signals, despite the existence of traps. Furthermore, low-mobility carriers (mobile ions or impurities) participate in the charge accumulation and depletion processes when the ramp rate is even slower, which results in a skew of C–V profiles. We also compare threshold voltages of several ramp rates. Finally, we extend the C–V measurement to devices with 37 lm and 57 lm channel lengths. Since the pentacene layer thickness is the same as that of the 17 lm case, the QSCV profiles behave similarly.

Acknowledgement

The authors would like to appreciate Industrial Tech-nology Research Institute (ITRI) in Taiwan for supporting the work.

References

[1] Nomoto K, Hirai N, Yoneya N, Kawashima N, Noda M, Wada M, Kasahara J. A high-performance short-channel bottom-contact OTFT and its application to AM-TN-LCD. IEEE Trans Elect Devices 2005;52:1519–26.

[2] Cao Q, Zhu ZT, Lemaitre MG, Xia MG, Shim M, Rogers JA. Transparent ﬂexible organic thin-ﬁlm transistors that use printed single-walled carbon nanotube electrodes. Appl Phys Lett 2006;88:113511–4.

[3] Alam MA, Dodabalapur A, Pinto M. A two-dimensional simulation of organic transistors. IEEE Trans Elect Devices 1997;44:1332–7. [4] Horowitz G, Lang P, Mottaghi M, Aubin H. Extracting parameters

from the current–voltage characteristics of organic ﬁeld eﬀect transistors. Adv Funct Mater 2004;14:1069–74.

[5] Street RA, Salleo A. Contact eﬀects in polymer transistors. Appl Phys Lett 2002;81:2287–9.

[6] Schroeder R, Majewski LA, Grell M. A study of the threshold voltage in pentacene organic ﬁeld eﬀect transistors. Appl Phys Lett 2003;83:3201–4.

[7] Nicoliam EH, Brews JR. Metal Oxide Semiconductor Physics and Technology 1991:71–175.

[8] Scheinert S, Schliefke W. Analyzes of ﬁeld eﬀect devices based on poly(3-octylthiophene). Synthetic Met 2003;139:501–9.

[9] Scheinert S, Paasch G, Pohlmann S, Ho¨rhold HH, Stockmann R. Field eﬀect in organic devices with solution-doped arylamino-poly-(phenylene–vinylene). Solid-State Elect 2000;44:845–53.

[10] Fujisaki Y, Inoue Y, Kurika T, Tokito S, Fujikake H, Kikuchi H. Improvement of characteristics of organic thin-ﬁlm transistor with anodized gate insulator by an electrolyte solution and low-voltage driving of liquid crystal by organic thin-ﬁlm transistors. Jpn J Appl Phys 2004;43:372–7.

Fig. 9. VTvs. ramp rate for a device with a 37 lm channel length (a) and a 57 lm channel length (b).

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[11] Ryu K, Kymissis I, Bulovic’ V, Sodini CG. Direct extraction of mobility in pentacene OFETs using C–V and I–V measurements. IEEE Elect Device Lett 2005;26:716–8.

[12] Verlaak S, Arkhipov V, Heremansa P. Modeling of transport in polycrystalline organic semiconductor ﬁlms. Appl Phys Lett 2003;82:745–7.

[13] Evaluation of gate oxides using a voltage step quasi-static CV method

http://cp.literature.agilent.com/litweb/pdf/5988-1025EN.pdf. [14] Nicoliam EH, Brews JR. Metal Oxide Semiconductor Physics and