IEEE ELECTRON DEVICE LETTERS, VOL. 31, NO. 2, FEBRUARY 2010 165
The Impact of Oxide Traps Induced by SOI
Thickness on Reliability of Fully Silicide
Metal-Gate Strained SOI MOSFET
Cheng-Li Lin, Yu-Ting Chen, Fon-Shan Huang, Wen-Kuan Yeh, and Chien-Ting Lin
Abstract—In this letter, we investigate the effects of oxide traps induced by various silicon-on-insulator (SOI) thicknesses (TSOI) on the performance and reliability of a strained SOI MOSFET with SiN-capped contact etch stop layer (CESL). Compared to the thicker TSOIdevice, the thinner TSOIdevice with high-strain CESL possesses a higher interface trap (Nit) density, leading to degradation in the device performance. On the other hand, how-ever, the thicker TSOIdevice reveals inferior gate oxide reliability. From low-frequency noise analysis, we found that thicker TSOI has a higher bulk oxide trap (NBOT) density, which is induced by larger strain in the gate oxide film and is mainly responsible for the inferior TDDB reliability. Presumably, the gate oxide film is bended up and down for the p- and nMOSFETs, respectively, by the net stress in thicker TSOIdevices in this strain technology.
Index Terms—Gate oxide TDDB, low-frequency noise (LFN), oxide trap, reliability, silicon on insulator (SOI), strained SOI.
I. INTRODUCTION
W
HEN MOSFETs continue scaling toward 45-nm tech-nology node and beyond, silicon on insulator (SOI) combined with strain engineering becomes the most promising technology to realize high-performance ULSI with low power consumption and high carrier mobility [1]–[4]. However, ex-tra process steps are required for the sex-train technology; thus, simpler strained engineering such as using a SiN contact etch stop layer (CESL) that can generate higher strain induced high tensile and high compressive stresses to improve the carrier mobility of an n- and a pMOSFET, respectively, was developed [5], [6]. On the other hand, a fully silicide (FUSI) gate, such as NiSi, has some advantages over other metal gate, including tunable work function and compatible CMOS process [7], [8]. It is believed that SOI technology, including partially depleted SOI and fully depleted SOI with CESL strain engineering and FUSI gate, is one of the most promising candidates for next technology node application. Although some literatureManuscript received September 22, 2009; revised November 10, 2009. First published January 19, 2010; current version published January 27, 2010. This work was supported by the National Science Council under Contract NSC 97-2221-E-035-090. The review of this letter was arranged by Editor B.-G. Park.
C.-L. Lin is with the Department of Electronic Engineering, Feng Chia University, Taichung 40724, Taiwan (e-mail: [email protected]).
Y.-T. Chen and F.-S. Huang are with the Institute of Electronics Engineering, National Tsing Hua University, Hsinchu 300, Taiwan.
W.-K. Yeh is with the Department of Electrical Engineering, National University of Kaohsiung, Kaohsiung 81148, Taiwan.
C.-T. Lin is with the Central R&D Division, United Microelectronics Corpo-ration, Hsinchu 300, Taiwan.
Color versions of one or more of the figures in this letter are available online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/LED.2009.2037900
have investigated the effects of CESL and SOI thicknesses on device performance [1]–[6], very few studies focus on the reliability and oxide trap distribution profile in the gate oxide with CESL strain and various TSOI’s, and they are still not
clearly understood. In this letter, we investigate the impact of SOI thickness on strained SOI MOSFETs, including the device performances, gate oxide reliability, and oxide trap distribution. Moreover, we show that the gate oxide quality is correlated to the SOI thickness.
II. EXPERIMENT
A 90-nm fully Ni-silicide (FUSI) gate MOSFET, with 1.5-nm-thick nitride gate oxide, was formed on a smart-cut SOI substrate with 400-nm-thick buried oxide at three silicon thicknesses (TSOI) of 50, 70, and 90 nm, separately. After
polygate deposition, Ni was deposited and formed to fully Ni silicide using two step rapid thermal processes [3]. Then, three kinds of SiN film with different strain processes were deposited. They are low-strain tensile, high-strain tensile, and high-strain compressive CESLs. In addition, a noise measure-ment at various frequencies was used to identify the location of the oxide trap charge for gate oxide quality analysis [9], [10].
III. RESULTS ANDDISCUSSION
Fig. 1 shows the temperature dependence of drain currents for the FUSI gate SOI nMOSFETs of various TSOI’s with low
and high tensile stresses, and the inset shows the schematic view of the CESL-capped devices. Carrier mobility of both n-and pMOSFETs can be enhanced by tensile n-and compressive stress, respectively. It can be seen from Fig. 1 that the drain current (or mobility) is improved by increasing TSOI,
partic-ularly for the high tensile stress. Device driving capability is related to the channel carrier mobility, which is composed of three components of optical phonon, surface scattering, and Coulomb scattering [11]. For the nMOSFETs, thinner TSOI
devices have lower drain currents, and the low mobility is limited by phonon scattering (μphonon) [11]. In addition, the
parasitic series resistance is another possible factor to slightly limit the drain current. With high-strain CESL capped, surface roughness scattering-limited carrier mobility (μsr) can be
en-hanced [12] for all SOI devices. Thus, electron mobility for the nMOSFETs is enhanced by tensile CESL [2], while different mobility for the different TSOI devices is apparently due to 0741-3106/$26.00 © 2010 IEEE
166 IEEE ELECTRON DEVICE LETTERS, VOL. 31, NO. 2, FEBRUARY 2010
Fig. 1. Temperature dependence of drain currents for FUSI gate SOI nMOSFETs with low- and high-tensile CESLs. The inset shows the schematic view of the SOI MOSFET with capped CESL, leading to create strain-induced
Nit(interface trap) and NBOT(bulk oxide trap).
Fig. 2. S.S. versus SOI thickness with low- and high-tensile CESLs for nMOSFETs. The S.S. can be improved using thinner TSOIat low-tensile CESL
but degraded by high-tensile CESL.
Coulomb-scattering-limited mobility (μcoul) [11]. Similar
re-sults were observed for the pMOSFET SOI devices.
To investigate the interface state at various SOI thicknesses under low- and high-strain tensile CESL, the subthreshold swing (S.S.) is a useful index to verify the variation of the interface state at the SiO2/Si interface of MOSFETs. Fig. 2
shows the S.S. behavior of nMOSFETs with different strain CESL and TSOI. For low-tensile CESL devices, the S.S. was
improved by decreasing TSOI, suggesting that less interface
state charges were formed with a thinner TSOI. On the other
hand, for devices with high-tensile CESL, we found that the S.S. was degraded by CESL, particularly with a thinner TSOI,
suggesting that more interface state charges were formed by high tensile stress with a thinner TSOI. Similar tendency was
observed in pMOSFETs (not shown). Thus, more interface trap charges (Nit) were possibly induced by high-strain CESL,
particularly for the MOSFETs with a thinner TSOI. Larger
CESL stress can also induce larger oxide trap charges, result-ing in threshold voltage shift and reliability degradation. To look into the quality of gate oxide, we employed the TDDB measurement. Fig. 3 shows the TBD Weibull distributions for
n- and pMOSFETs with high tensile and high compressive stresses, respectively, for various SOI thicknesses. Larger TBD
Fig. 3. TBD Weibull distributions of (a) an nMOSFET with high tensile
stress and (b) a pMOSFET with high compressive stress under constant voltage stresses VG= 3 V and VG=−3 V, respectively, for various SOI thicknesses.
Fig. 4. Input-referred voltage noise of LFN measurement for (a) an nMOSFET with high tensile stress and (b) a pMOSFET with high compressive stress for various SOI thicknesses. The insets show the stress nature for the tensile and compressive capped FUSI gate SOI nMOSFETs and pMOSFETs, respectively; σT and σC are designated as net tensile and net compressive
stresses, respectively.
was found for the devices with thinner SOI thickness than those of thicker TSOI regardless of n- or pMOSFET. This indicates
that the gate oxide quality is degraded with increasing TSOI
thickness for the devices with high-strain CESL. Furthermore, it can be seen from Fig. 3(a) and (b) that the extent of gate oxide quality degradation is larger for n-type devices with increasing
TSOIthickness. Increasing TSOIis beneficial to improve carrier
mobility, but it will degrade the gate oxide TDDB reliability. A low-frequency noise (LFN) spectrum analysis was em-ployed to evaluate the distribution of oxide traps in the gate oxide for various TSOIwith high-strain CESL. The oxide traps
(NT) contain two components, namely, interfere trap (Nit) and
bulk oxide trap (NBOT). Fig. 4 shows the input-referred voltage
noise for the n- and pMOSFETs with tensile and high-compressive CESL, respectively. For the nMOSFETs with high tensile stress, it was found that thicker TSOI devices revealed
LIN et al.: IMPACT OF OXIDE TRAPS INDUCED BY SOI THICKNESS 167
this is attributed to higher NT in the thicker TSOI devices.
The slope of the noise spectrum is correlated with the density distribution of Nit and NBOT, and it follows the form of
1/fα [10], [14], where the exponent α can be calculated by
the neglecting generation–recombination noise. If the NBOT
densities in the gate oxide are uniform spatial distribution, α is equal to one because the flicker noise is mainly resulting from Nit. For the high-strain CESL-capped n- and pMOSFETs
studied in this work, the exponent values (α) are all larger than one with large gate overdrive voltage. Moreover, the α values of thicker TSOI(90 nm) devices are larger than those of thinner
TSOI(50 nm) devices for both n- and pMOSFETs (1.43 versus
1.16 and 1.14 versus 1.08, respectively). This implies that the density of NBOT located near the FUSI/oxide region is larger
than that of Nit located at the oxide/Si-substrate interface for
the thicker TSOI devices. Fig. 4(a) and (b) also clearly shows
that thicker TSOI (90 nm) induced higher density of NBOT in
the nMOSFETs than the pMOSFETs. This is consistent with the TDDB behavior, as shown in Fig. 3.
The origin of oxide trap is considered to be due to the stress in the gate oxide film [14]. In addition, due to the fact that the thermal expansion coefficient of Si (αSi) is smaller than that
of oxide (αox) [15], strain will be induced in top and bottom
SOI after gate oxide growth and CESL capping, as shown in the inset in Fig. 4. For the tensile CESL-capped nMOSFET with thinner TSOI (50 nm) [inset in Fig. 4(a)], large tensile
strain and stress (σT) in the SOI film was induced by CESL,
compensating the compressive stress (σC) in the gate oxide
and leading to alleviate down bending of the gate oxide film. With a thicker TSOI(90 nm), less tensile strain and stress (σT)
was induced in the bulk SOI, resulting in larger compressive stress (σC) remaining in the gate oxide, thus leading to larger
down bending of the gate oxide film. Thus, for thicker TSOI
nMOSFETs, there is a larger net compressive stress induced in the top region of the gate oxide near the FUSI gate, which tends to induce more bulk oxide traps (NBOT). For compressive
CESL-capped pMOSFET, similar tendency of NBOTformation
caused by oxide tensile stress leading to up bending of the gate oxide film will occur, as shown in the inset in Fig. 4(b).
IV. CONCLUSION
For FUSI gate SOI CMOSFETs, device performance and gate oxide reliability are affected by interface trap (Nit)
and bulk oxide trap (NBOT) resulting from the CESL and
SOI thickness. For a device with high-strain CESL, we found that the thinner TSOI device has smaller net stress in the gate
oxide film than the thicker ones, and it possesses a smaller
NBOTand reveals superior gate oxide reliability. On the other
hand, the thicker TSOIdevice reveals superior driving capability
due to smaller Nit, but it reveals inferior gate oxide reliability.
Presumably, the gate oxide film is bended up and down for the p- and nMOSFETs, respectively, by the net stress in thicker
TSOI devices in this strain technology. We believe that this is
the main reason for the device reliability degradation, in partic-ular, the nMOSFETs. Therefore, an appropriate SOI thickness
design is the key factor to achieve superior device performance and reliability.
ACKNOWLEDGMENT
The authors would like to thank the United Microelectronics Corporation staff for their helpful support and K.-S. Wang for the assistance for the TDDB reliability measurement.
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