Investigation and Design of On-Chip Power-Rail ESD Clamp Circuits Without Suffering Latchup-Like Failure During System-Level ESD Test

Investigation and Design of On-Chip Power-Rail

ESD Clamp Circuits Without Suffering Latchup-Like

Failure During System-Level ESD Test

Ming-Dou Ker, Fellow, IEEE, and Cheng-Cheng Yen, Student Member, IEEE

Abstract—On-chip power-rail electrostatic discharge (ESD)

protection circuit designed with active ESD detection func-tion is the key role to significantly improve ESD robustness of CMOS integrated circuits (ICs). Four power-rail ESD clamp circuits with different ESD-transient detection circuits were fab-ricated in a 0.18- m CMOS process and tested to compare their system-level ESD susceptibility, which are named as power-rail ESD clamp circuits with typical RC-based detection, PMOS feed-back, NMOS+PMOS feedfeed-back, and cascaded PMOS feedback in this work. During the system-level ESD test, where the ICs in a system have been powered up, the feedback loop used in the power-rail ESD clamp circuits provides the lock function to keep the ESD-clamping NMOS in a “latch-on” state. The latch-on ESD-clamping NMOS, which is often drawn with a larger device dimension to sustain high ESD level, conducts a huge current between the power lines to perform a latchup-like failure after the system-level ESD test. A modified power-rail ESD clamp circuit is proposed to solve this problem. The proposed power-rail ESD clamp circuit can provide high enough chip-level ESD robust-ness, and without suffering the latchup-like failure during the system-level ESD test.

Index Terms—Electromagnetic compatibility (EMC),

elec-trostatic discharge (ESD), ESD protection circuit, latchup, system-level ESD test.

I. INTRODUCTION

E

LECTROSTATIC discharge (ESD) protection has been one of the most important reliability issues in CMOS in-tegrated circuit (IC) products. ESD failures caused by thermal breakdown due to high current transient, or dielectric break-down in gate oxide due to high voltage overstress, often re-sult in immediate malfunction of IC chips. In order to obtain high ESD robustness, CMOS ICs must be designed with on-chip ESD protection circuits at the input/output (I/O) pins and across the power lines [1]. With the reduced breakdown voltage of the thinner gate oxide in advanced deep-submicron CMOS pro-cesses, turn-on-efficient ESD protection circuit is required to clamp the overstress across the gate oxide of internal circuits.

Manuscript received May 23, 2007; revised August 01, 2008. Current version published November 19, 2008. This work was supported by the National Sci-ence Council (NSC), Taiwan, R.O.C., under Contract NSC 97-2221-E-009-170, and partially supported by Himax Technologies Inc., Taiwan, R.O.C.

M.-D. Ker was with the Nanoelectronics and Gigascale Systems Laboratory, Institute of Electronics, National Chiao-Tung University, Hsinchu 300, Taiwan, and is now with the Department of Electronic Engineering, I-Shou University, Kaohsiung, Taiwan (e-mail: [email protected]).

C.-C. Yen is with the Nanoelectronics and Gigascale Systems Laboratory, Institute of Electronics, National Chiao-Tung University, Hsinchu 300, Taiwan.

Digital Object Identifier 10.1109/JSSC.2008.2005451

Since the stored electrostatic charges could be either positive or negative, there are four different ESD-testing modes at input-output (I/O) pins with respect to the grounded or pins [2]. Besides, for a comprehensive ESD verification, two addi-tional pin combinations under ESD test, which are the pin-to-pin ESD stress and the -to- ESD stress, are performed to verify the ESD reliability of IC chip [2]. These two additional ESD testing modes often lead to some unexpected ESD cur-rent through I/O pins and power lines into the internal circuits and result in ESD damage in the internal circuits [3]. Therefore, effective power-rail ESD clamp circuit between and power lines is necessary for whole-chip ESD protection. The typical on-chip ESD protection design with active power-rail ESD clamp circuit in CMOS ICs is shown in Fig. 1[4]. When the input (or output) pin is zapped under the positive-to-(PS-mode) or negative-to- (ND-mode) ESD stresses, the power-rail ESD clamp circuit can provide a low impedance path between and power lines to efficiently discharge ESD current. To avoid unexpected ESD damages in the internal cir-cuits under pin-to-pin and -to- ESD stresses, the power-rail ESD clamp circuit must be designed with high turn-on effi-ciency and fast turn-on speed.

In the active power-rail ESD clamp circuit, the ESD-transient detection circuit is designed to detect ESD event and sends a control voltage to the gate of ESD-clamping NMOS. Since the ESD-clamping NMOS is turned on by a positive gate voltage rather than by snapback breakdown, the ESD-clamping NMOS can be turned on quickly to discharge ESD current before the in-ternal circuits are damaged. Thus, the effective power-rail ESD clamp circuit is necessary for protecting the internal circuits against ESD damage. Some modified designs on the ESD-tran-sient detection circuits had been reported to enhance the perfor-mance of power-rail ESD clamp circuits [5]–[9].

Recently, system-level ESD reliability has attracted more at-tentions than before in microelectronics products. This tendency results from not only the integration of more functional circuits in a single chip, but also the strict requirement of reliability reg-ulation, such as the system-level ESD test for electromagnetic compatibility (EMC) [10]. During the system-level ESD test, the microelectronics products must sustain the ESD stress of 8 kV ( 15 kV) under the contact-discharge (air-discharge) test mode to meet the immunity requirement of “level 4.” During such a high-energy ESD event, some of ESD-induced overshooting/undershooting pulses may be coupled into the microelectronics products to cause damage or malfunction on the CMOS ICs inside the device under test (DUT) [11], [12].

Fig. 1. Typical on-chip ESD protection design with active power-rail ESD clamp circuit.

Some CMOS ICs are very susceptible to system-level ESD stresses, even though they have passed the component-level ESD specifications of human-body model (HBM) of 2 kV, machine-model (MM) of 200 V, and charged-device model

(CDM) of kV [13].

In this work, the malfunction or wrong triggering be-havior among different on-chip power-rail ESD clamp circuits under system-level ESD test are investigated [14]. Some ESD-transient detection circuits designed with feedback loop in the power-rail ESD clamp circuits continually keep the ESD-clamping NMOS in the latch-on state after the system-level ESD test. The latch-on ESD-clamping NMOS between and power lines in the powered-up micro-electronic system causes a serious latchup-like failure in CMOS ICs. The system-level ESD gun [15] and the transient-induced latchup (TLU) measurement method [16] are used to eval-uate the susceptibility among four different power-rail ESD clamp circuits to system-level ESD test. Furthermore, a mod-ified power-rail ESD clamp circuit is proposed to avoid such latchup-like failure. The proposed power-rail ESD clamp circuit can provide high enough chip-level ESD robustness without suffering the latchup-like failure during the system-level ESD test.

II. POWER-RAILESD CLAMPCIRCUITS

To provide effective on-chip ESD protection, four different power-rail ESD clamp circuits had been reported [5]–[9], which are redrawn in Fig. 2(a)–(d) with the names of 1) power-rail ESD clamp circuit with typical RC-based detection, 2) power-rail ESD clamp circuit with PMOS feedback, 3) power-power-rail ESD clamp circuit with NMOS+PMOS feedback, and 4) power-rail ESD clamp circuit with cascaded PMOS feedback, in this work. Those power-rail ESD clamp circuits have been designed and fabricated in a 0.18- m CMOS process to investigate their sus-ceptibility to system-level ESD test.

A. Power-Rail ESD Clamp Circuit With Typical RC-Based Detection

The typical RC-based power-rail ESD clamp circuit is illus-trated in Fig. 2(a) with a three-stage buffer between the RC circuit and the ESD-clamping NMOS [5]. The ESD-clamping NMOS is used to provide a low impedance path between

and to discharge ESD current. The ESD-transient detection circuit detects ESD pulses with the rise time of 10 ns and sends a control voltage to the gate of ESD-clamping NMOS. Under the ESD stress condition, the voltage level at the node is increased much slower than that on power line, because the RC circuit has a time constant in the order of microsecond ( s). Due to the delay of the voltage increase at the node, the three-stage buffer is powered by the ESD energy and con-duct a voltage to the node to turn on the ESD-clamping NMOS. The turned-on ESD-clamping NMOS, which provides a low-impedance path between and power lines, clamps the overstress ESD voltage to effectively protect the internal cir-cuits against ESD damage.

The turn-on time of ESD-clamping NMOS during ESD tran-sition can be adjusted by designing the RC time constant in the ESD transient detection circuit. The turn-on time is usually de-signed around 100 ns to meet the half-energy discharging time of HBM ESD current. Under normal circuit operating condi-tions, the power-rail ESD clamp circuit must be kept off to avoid power loss from to . The rise time of powered up is around 1 ms or even longer in the most of microelectronics systems. To meet such a timing requirement, the RC time con-stant in the RC-based ESD-transient detection circuit is typically designed with 0.1–1 s to achieve the design constraints. B. Power-Rail ESD Clamp Circuit With PMOS Feedback

Another design consideration for power-rail ESD clamp cir-cuit is the circir-cuit immunity to false triggering during power-up condition. The power-rail ESD clamp circuit should be turned on when the ESD voltage appears across and power lines, but kept off when the IC is under normal power-on condition. To meet these requirements, the RC time constant was usually designed with 0.1–1 s to achieve the design constraints. However, the large RC time constant used in the power-rail ESD clamp circuit may cause false triggering during a fast power-up condition with a rise time of less than 10 s. The modified power-rail ESD clamp circuit incorporated with PMOS feedback, as shown in Fig. 2(b), was used to mitigate such a mistrigger problem [6]. The transistor MPFB can help to keep the gate voltage of ESD-clamping NMOS below its threshold voltage and further reduce the current drawn during the power-up condition.

Fig. 2. Four different power-rail ESD clamp circuits designed with (a) typ-ical RC-based detection, (b) PMOS feedback, (c) NMOS+PMOS feedback, and (d) cascaded PMOS feedback.

C. Power-Rail ESD Clamp Circuit With NMOS+PMOS Feedback

In the advanced CMOS technology with thinner gate oxide, the power-rail ESD clamp circuit with a large MOS capacitance

in the RC timer was reported to cause significant standby power consumption due to gate oxide leakage current [7]. Thus, the modified power-rail ESD clamp circuits with small MOS ca-pacitance are desired to combat the gate leakage. It was reported that the power-rail ESD clamp circuit incorporated with a regen-erative feedback network can be used to significantly reduce the RC time constant, as illustrated in Fig. 2(c) [8].

The transistors MPFB and MNFB provide a feedback loop, which can latch the ESD-clamping NMOS in the conductive state during ESD-stress condition. When a fast positive going ESD transient across the power rails, the MNFB can further pull the potential of INV2OUT node towards ground to latch the ESD-clamping NMOS in the conductive state until the voltage on drops below the threshold voltage of ESD-clamping NMOS. With this feedback loop in the power-rail ESD clamp circuit, the dynamic currents of , , MPFB, and MNFB determine the critical voltage to trigger on the ESD-clamping NMOS. After the timing out of the RC time constant in ESD transient detection circuit, the transistor begins to conduct and increase the potential of INVOUT2 node. The settling po-tential of INVOUT2 node is set by the current balance between and MNFB. Thus, the device ratios of and MNFB in the power-rail ESD clamp circuit with NMOS+PMOS feedback should be appropriately selected.

D. Power-Rail ESD Clamp Circuit With Cascaded PMOS Feedback

Another RC-based power-rail ESD clamp circuit with cas-caded PMOS feedback has been proposed to reduce the RC time constant and to solve false trigger issue during fast power-up constraints, as shown in Fig. 2(d) [9]. The PMOS transistor MPFB is connected to form the cascaded feedback loop, which is a dynamic feedback design.

During the ESD-stress condition, the transistor MPFB was turned off and the voltage on the INV2OUT node can be remained in a low state. Thus, the turn-on time of the ESD-clamping NMOS can be longer than that of the typical RC-based power-rail ESD clamp circuit. If the ESD-clamping NMOS is mistriggered during fast power-up condition or by an overvoltage under normal operating conditions, the voltage on the INV2OUT node can be charged up toward by the subthreshold current of MPFB. Therefore, the ESD-clamping NMOS will not stay at latch-on state and turn itself off after the fast power-up condition. Compared with the feedback designs with direct PMOS feedback in Fig. 2(b), the power-rail ESD clamp circuit with cascaded PMOS feedback has the advantage of capacitance reduction.

E. Realization in Silicon Chip

For the four power-rail ESD clamp circuits in this work, the ESD-clamping NMOS is designed to turn on under the ESD-stress condition to efficiently discharge the ESD current between and power lines. The turn-on time of the ESD-clamping NMOS is designed to meet the half-energy discharging time of HBM ESD event. In the normal operating condition and power-up condition, the ESD-clamping NMOS is designed to keep off to avoid power loss or false triggering. The four power-rail ESD clamp circuits in this

TABLE I

DEVICEDIMENSIONS(W=LINm)OF THEPOWER-RAILESD CLAMPCIRCUIT

WITHTYPICALRC-BASEDDETECTION

TABLE II

DEVICEDIMENSIONS(W=LINm)OF THEPOWER-RAILESD CLAMP

CIRCUITWITHPMOS FEEDBACK

TABLE III

DEVICEDIMENSIONS(W=LINm)OF THEPOWER-RAILESD CLAMP

CIRCUITWITHNMOS+PMOS FEEDBACK

work are designed with such design concepts to evaluate their susceptibility to system-level ESD tests. The device dimensions of four different power-rail ESD clamp circuits realized in a given 0.18- m CMOS process are summarized in Tables I–IV.

To verify such design, some simulations are provided in the following. In Fig. 3(a), a power-on voltage waveform with a rise time of 0.1 ms and a voltage height of 1.8 V is applied to the line of the power-rail ESD clamp circuits. During such a power-on condition, among the four different power-rail ESD clamp circuits, the voltage waveforms on the node are shown in Fig. 3(b), where the peak voltage during the power-on transition are all below the threshold voltage ( 0.44 V) of the ESD-clamping NMOS. With a very small

TABLE IV

DEVICEDIMENSIONS(W=LINm)OF THEPOWER-RAILESD CLAMPCIRCUIT

WITHCASCADEDPMOS FEEDBACK

Fig. 3. HSPICE simulated voltage waveforms among the four different power-rail ESD clamp circuits under theV power-on condition. (a) A slow ramp voltage waveform with rise time of 0.1 ms is used to simulate the rising edge of theV power-on voltage. (b) The simulated voltage waveforms on the node V when the V power-on voltage is applied toV .

voltage in Fig. 3(b), the ESD-clamping NMOS in the four different power-rail ESD clamp circuits was expected to be always kept off when the IC is in normal operating conditions.

In Fig. 4(a), a fast ramp voltage with a rise time of 10 ns is used to simulate the rising edge of HBM ESD pulse. The pulse height of the fast ramp voltage set as 5 V is used to mon-itor the voltage on the node before the drain breakdown of ESD-clamping NMOS. As shown in Fig. 4(b), among the four different power-rail ESD clamp circuits, the voltage waveforms on the node are simultaneously increased when the fast ramp

Fig. 4. HSPICE simulated voltage waveforms among the four different power-rail ESD clamp circuits under HBM ESD stress condition. (a) A fast ramp voltage waveform with rise time of 10 ns is used to simulate the rising edge of an HBM ESD pulse. (b) The simulated voltage waveforms on the nodeV when the fast ramp voltage is applied toV .

voltage is applied to , whereas the is grounded. The four power-rail ESD clamp circuits are designed to provide a low impedance path between and power lines to ef-ficiently discharge ESD current under ESD stress conditions. Combing with feedback circuit structure in the ESD-transient detection circuits, the turn-on time of the ESD-clamping NMOS can be increased by static or dynamic latches [8], [9]. For the power-rail ESD clamp circuits with NMOS+PMOS feedback and cascaded PMOS feedback, the turn-on time of the ESD-clamping NMOS can be longer than that of power-rail ESD clamp circuits with typical RC-based detection and PMOS feed-back. The turn-on time of power-rail ESD clamp circuits with NMOS+PMOS feedback or cascaded PMOS feedback can be designed around 100 ns, if the RC time constant in the corre-sponding ESD-transient detection circuit is further reduced. To simply the comparison for transient-induced latchup-like failure in this work, the RC values in the ESD-transient detection cir-cuits among four power-rail ESD clamp circir-cuits are set the same of R 50 k and C 2 pF in silicon fabrication.

Fig. 5. Measurement setup for transient-induced latchup (TLU) [16].

III. TRANSIENT-INDUCEDLATCHUP(TLU) TEST

A. Measurement Setup

Transient-induced latchup (TLU) test has been used to inves-tigate the susceptibility of DUT to the noise transient or glitch on the power lines under normal circuit operating condition. The component-level TLU measurement setup with bipolar trigger voltage can accurately simulate the ESD-induced noises on the power lines of CMOS ICs under system-level ESD test [16]. The measurement setup for TLU test is shown in Fig. 5. The charging voltage has two different polarities, which are positive

( ) or negative ( ). The positive

(nega-tive) can generate the positive-going (negative-going) bipolar trigger noises on the power pins of DUT. A 200-pF ca-pacitor used in the machine model (MM) ESD test [17] is em-ployed as the charging capacitor. The power-rail ESD clamp circuits shown in Fig. 2(a)–(d) are placed as DUT. The supply voltage of 1.8 V is used as and the noise trigger source is di-rectly connected to DUT through the relay in the measurement setup. The current waveform is measured by a separated current probe. The current-limiting resistance is used to avoid electrical-over-stress (EOS) damage in DUT under a high-cur-rent latch-up state. The voltage and curhigh-cur-rent waveforms on DUT (at node) after TLU test are monitored by the oscilloscope.

B. Measurement Results

With the TLU measurement setup in Fig. 5, the and transient responses can be recorded by the oscilloscope, which can clearly indicate whether TLU occurs ( significantly in-creases) or not. Fig. 6(a) and (b) show the measured and transient waveforms on the power-rail ESD clamp circuit with NMOS+PMOS feedback under the stresses with of 4 V and 12 V, respectively. After the TLU test with an initial of 4 V, the latchup-like failure occurs in this power-rail ESD clamp circuit, because significantly increases and is pulled down, as shown in Fig. 6(a). After the TLU test with an initial of 12 V, latchup-like failure occurs in Fig. 6(b). All the PMOS and NMOS devices in the ESD-tran-sient detection circuits are surrounded with double guard rings to guarantee no latchup issue in this part [18]. This implies that the feedback loop in the ESD-transient detection circuit is locked after TLU test and continually keeps the ESD-clamping

Fig. 6. MeasuredV andI waveforms on the power-rail ESD clamp cir-cuit with NMOS+PMOS feedback under TLU test withV of (a)04 V and (b)+12 V.

NMOS in the latch-on state. From the observed voltage and cur-rent waveforms, large current is caused by the latch-on state of ESD-clamping NMOS after TLU test.

For the power-rail ESD clamp circuit with cascaded PMOS feedback, the measured and transient responses are shown in Fig. 7(a) and (b) under the TLU test with the ini-tial of 120 V and 700 V, respectively. The similar latchup-like failure also occurs in this power-rail ESD clamp circuit due to the latch-on state of ESD-clamping NMOS after TLU test. The TLU levels (the minimum voltage of to induce the latchup-like failure on ) among the aforemen-tioned four different power-rail ESD clamp circuits are listed in Table V.

IV. SYSTEM-LEVELESD TEST

A. Measurement Setup

In the standard of IEC 61000–4-2 [10], two test modes have been specified, which are air-discharge test mode and contact-discharge test mode. Fig. 8 shows the standard measurement setup of the system-level ESD test with indirect contact-dis-charge test mode [10]. The measurement setup of system-level ESD test consists of a wooden table on the grounded reference plane (GRP). In addition, an insulation plane is used to sepa-rate the equipment under test (EUT) from the horizontal cou-pling plane (HCP). The HCP are connected to the GRP with two

Fig. 7. MeasuredV andI waveforms on the power-rail ESD clamp cir-cuit with cascaded PMOS feedback under TLU test withV of (a)0120 V and (b)+700 V.

TABLE V

COMPARISON ONTLU LEVELSAMONGFOURDIFFERENTPOWER-RAIL

ESD CLAMPCIRCUITSUNDERTLU TEST

470 k resistors in series. When the ESD gun zaps the HCP, the electromagnetic interference (EMI) coming from the ESD will be coupled into all CMOS ICs inside EUT. The power lines of CMOS ICs inside EUT will be disturbed by such high ESD-cou-pled energy.

With such a standard measurement setup, the susceptibility of different power-rail ESD clamp circuits against the system-level ESD stresses can be evaluated. The stand alone power-rail ESD clamp circuit in IC package is powered up with power supply of 1.8 V. Before any ESD zapping, the initial voltage level

Fig. 8. Measurement setup for system-level ESD test with indirect contact-discharge test mode [10] to evaluate the susceptibility of power-rail ESD clamp circuits.

on the IC is measured to make sure the correct bias of 1.8 V. After every ESD zapping, the voltage level on node of IC is measured again to watch whether latchup-like failure occurs after the system-level ESD test, or not. If the latchup-like failure occurs, the potential on node will be pulled down to a much lower level due to the latch-on state of ESD-clamping NMOS in the power-rail ESD clamp circuits, and will be significantly increased.

B. Measurement Results

With the system-level ESD measurement setup in Fig. 8, the and transient responses can be recorded by the os-cilloscope, which can clearly indicate whether the latchup-like failure occurs or not. Fig. 9(a) and (b) show the measured and transient responses on the power-rail ESD clamp circuit with typical RC-based detection when ESD gun with ESD voltage of 10 kV and 10 kV zapping on the HCP, respectively. After the system-level ESD test with an ESD voltage of 10 kV, latchup-like failure is not initiated in this power-rail ESD clamp circuit, because is still kept at zero, as shown in Fig. 9(a). After the system-level ESD test with an ESD voltage of 10 kV, latchup-like failure is not observed in Fig. 9(b). Under system-level ESD test with ESD voltage of 10 kV and 10 kV, the measured and transient waveforms on the power-rail ESD clamp circuit with PMOS feedback are shown in Fig. 10(a) and (b), respec-tively. Under system-level ESD test with an ESD voltage of 10 kV ( 10 kV), acts with the intended bipolar trigger. Meanwhile, latchup-like failure does not occur because is not increased, as shown in Fig. 10(a) (Fig. 10(b)). For the power-rail ESD clamp circuits with typical RC-based detection or PMOS feedback, latchup-like failure does not occur even though the ESD voltage is as high as 10 kV or 10 kV in the system-level ESD test.

Fig. 11(a) and (b) show the measured and tran-sient responses on the power-rail ESD clamp circuit with NMOS+PMOS feedback under the system-level ESD test with

Fig. 9. MeasuredV andI waveforms on the power-rail ESD clamp cir-cuit with typical RC-based detection under system-level ESD test with ESD voltage of (a)010 kV and (b) +10 kV.

ESD voltages of 0.2 kV and 2.5 kV, respectively. After the system-level ESD test with an ESD voltage of 0.2 kV, latchup-like failure can be initiated in this power-rail ESD clamp circuit, because is significantly increased and is pulled down as shown in Fig. 11(a). After the system-level

Fig. 10. MeasuredV andI waveforms on the power-rail ESD clamp circuit with PMOS feedback under system-level ESD test with ESD voltage of (a)010 kV and (b) +10 kV.

ESD test with an ESD voltage of 2.5 kV, the latchup-like failure can be also found in Fig. 11(b).

For the power-rail ESD clamp circuit with cascaded PMOS feedback, the measured and transient responses are shown in Fig. 12(a) and (b) under the system-level ESD test with ESD voltages of 1 kV and 10 kV, respectively. The similar latchup-like failure also occurs in this power-rail ESD clamp circuit due to the latch-on state of ESD-clamping NMOS under the system-level ESD test with an ESD voltage of 1 kV, as shown in Fig. 12(a).

The susceptibility among the aforementioned four different power-rail ESD clamp circuits against system-level ESD test are listed in Table VI. The power-rail ESD clamp circuits with NMOS+PMOS feedback or with cascaded PMOS feedback have lower ESD voltages to cause latchup-like failure after system-level ESD test. Such measured results by ESD gun test are consistent with those of TLU shown in Table V. From the experimental results, the power-rail ESD clamp circuit designed with NMOS+PMOS feedback is highly sensitive to transient-induced latchup-like failure. The typical power-rail ESD clamp circuits with RC-based detection and with PMOS feedback are free to such a latchup-like failure.

The failure location after system-level ESD test has been in-spected, as shown in Fig. 13. The failure location is located at the metal line from the pad to the power-rail ESD clamp circuit, which was drawn with a metal width of 30 m in the test chip.

Fig. 11. MeasuredV andI waveforms on the power-rail ESD clamp circuit with NMOS+PMOS feedback under system-level ESD test with ESD voltage of (a)00.2 kV and (b) +2.5 kV.

V. MODIFIEDPOWER-RAILESD CLAMPCIRCUIT

From the above measurement results, some ESD-transient detection circuits designed with feedback loop in the power-rail ESD clamp circuits continually keep the ESD-clamping NMOS in the latch-on state after the system-level ESD test. The

latch-on ESD-clamping NMOS between and power

lines in the powered-up microelectronic system causes a serious latchup-like failure in CMOS ICs. In order to meet electromag-netic compatibility regulation under system-level ESD test, modified power-rail ESD clamp circuits without suffering the latchup-like failure are highly desirable. It has been reported that the power-rail ESD clamp circuit with conventional rise time detector and a separated on-time control circuit can reduce the RC area and improve the immunity to false trig-gering [19]. The separated on-time control circuit can keep the ESD-clamping NMOS turned on for the expected maximum duration of an ESD event. From the measured results under the system-level ESD test, two ESD-transient detection circuits designed with feedback loop in the power-rail ESD clamp circuits had been found suffering latchup-like failure. In order to avoid such a latchup-like failure, it could be useful to reduce the latch strength of the feedback loop in the ESD-transient de-tection circuit by suitable device dimension sizing. In this work, another modified power-rail ESD clamp circuit is proposed to avoid such latchup-like failure. The proposed power-rail ESD clamp circuit can provide high enough chip-level ESD

Fig. 12. MeasuredV andI waveforms on the power-rail ESD clamp circuit with cascaded PMOS feedback under system-level ESD test with ESD voltage of (a)01 kV and (b) +10 kV.

TABLE VI

COMPARISON ON THESUSCEPTIBILITYAMONGFOURDIFFERENTPOWER-RAIL

ESD CLAMPCIRCUITSUNDERSYSTEM-LEVELESD TEST

robustness without suffering the latchup-like failure during the system-level ESD test.

A. Power-Rail ESD Clamp Circuit With NMOS Reset Function Fig. 14 shows the proposed power-rail ESD clamp circuit with NMOS reset function to overcome the latchup-like failure, which is realized with NMOS+PMOS feedback and an addi-tional NMOS device ( ) to provide the reset function after system-level ESD stresses. When the ESD-clamping NMOS is latched-on, the NMOS device ( ) will be turned on after

Fig. 13. Failure location of power-rail ESD clamp circuit after system-level ESD stress.

Fig. 14. Proposed power-rail ESD clamp circuit with NMOS reset function to overcome latchup-like failure.

the time out of RC time constant. Thus, the gate potential of the ESD-clamping NMOS will be pulled down toward 0 V to re-lease the “latch-on” state.

B. Simulation Results

The NMOS device is used to release the “latch-on” state of the ESD-clamping NMOS. After system-level ESD tests, the potential on the node is charged toward the voltage potential on . When the potential at the node is greater than the threshold voltage of , can be turned on to pull down any potential at . Thus, the “latch-on” state of the ESD-clamping NMOS caused by system-level ESD test can be released. With the NMOS+PMOS feedback in the power-rail ESD clamp circuit, the dynamic currents of , , MPFB, and MNFB determine the critical voltage to trigger on the ESD-clamping NMOS. The dimensions of and should be appropriately designed with consideration of the NMOS+PMOS feedback loop.

Fig. 15 shows the simulated transient responses on volt-ages of the proposed power-rail ESD clamp circuit and the orig-inal power-rail ESD clamp circuit with NMOS+PMOS feed-back, respectively. The voltage on is 1.8 V and the ini-tial voltage on is set to 1.8 V to simulate the “latch-on” state of the ESD-clamping NMOS after system-level ESD tests. With an initial voltage of 1.8 V, the voltage of the power-rail

Fig. 15. SimulatedV voltage waveforms on the proposed power-rail ESD clamp circuit with NMOS reset function and power-rail ESD clamp circuit with NMOS+PMOS feedback with an initialV voltage of 1.8 V.

Fig. 16. SimulatedV voltage waveforms on the proposed power-rail ESD clamp circuit with NMOS reset function and power-rail ESD clamp circuit with NMOS+PMOS feedback under the ESD-like rising edge of HBM ESD stress.

ESD clamp circuit with NMOS+PMOS feedback continues to keep at 1.8 V. As shown in Fig. 15, the voltage of the pro-posed power-rail ESD clamp circuit can be pulled down to 0 V to release the “latch-on” state of ESD-clamping NMOS. By in-creasing the device size of , the latch-on time of ESD-clamping NMOS can be reduced, as shown in Fig. 15. There-fore, the proposed power-rail ESD clamp circuit with NMOS reset function can avoid the latchup-like failure after system-level ESD tests.

For HBM ESD stress simulation, a fast ramp voltage with a rise time of 10 ns shown in Fig. 4(a) is applied to of the proposed power-rail ESD clamp circuit with NMOS reset func-tion and the power-rail ESD clamp circuit with NMOS+PMOS feedback, whereas the is grounded. The pulse height of the fast ramp voltage set as 5 V, before drain breakdown of ESD-clamping NMOS, is used to monitor the voltage on the node and the turn-on time of ESD-clamping NMOS. As shown in Fig. 16, compared with power-rail ESD clamp circuits with NMOS+PMOS feedback, the proposed power-rail ESD clamp circuit with NMOS reset function has a shorter turn-on time of around 380 ns.

C. Experimental Results

The proposed power-rail ESD clamp circuit with NMOS reset function has been designed and fabricated in a 0.18- m CMOS process. Measurements were performed to compare the system-level ESD robustness between this proposed and the original power-rail ESD clamp circuits.

Fig. 17. Measured voltage waveforms on the proposed power-rail ESD clamp circuit with NMOS reset function in (a) ESD-stress condition and (b) power-on condition.

1) Turn-On Verification: To verify the ESD-transient detec-tion funcdetec-tion of the proposed power-rail ESD clamp circuit with NMOS reset function, a voltage pulse generated from a pulse generator is used to simulate the rising edge of HBM ESD pulse, which has a square-type voltage waveform with a rise time about 10 ns. When the voltage pulse is applied to power line with grounded, the sharp-rising edge of the ESD-like voltage pulse will trigger on the ESD-clamping NMOS to provide a low-impedance path between and power lines. Due to the limited driving current of the pulse generator, the voltage on power line will be degraded by the turned-on ESD-clamping NMOS. The voltage waveform on power line of the proposed power-rail ESD clamp circuit with NMOS reset function is shown in Fig. 17(a), where a voltage pulse with a pulse height of 5 V and a pulse width of 1000 ns is applied to power line. The voltage waveform is degraded at the rising edge because the ESD-clamping NMOS is simultane-ously turned-on when the ESD-like voltage pulse is applied to power line. The voltage degradation is dependent on the turned-on resistance of the ESD-clamping NMOS and the output resistance (typically, 50 ) of the pulse generator. A larger device dimension of the ESD-clamping NMOS leads to a more serious degradation on the voltage waveform. When the node is charged up to the threshold voltage of the in-verter1 (formed by and in Fig. 14), the ESD-clamping NMOS will be turned off and the voltage waveform will be re-stored to the original voltage level. In Fig. 17(a), the applied 5-V voltage pulse has a recovery time of about 400 ns, which is cor-responding to the turn-on time of the ESD-clamping NMOS.

Fig. 18. Measured V and I waveforms on the proposed power-rail ESD clamp circuit with NMOS reset function under TLU test withV of (a)01 kV and (b) +1 kV. No latchup-like failure occurs in this TLU test.

To verify the action of the proposed power-rail ESD clamp circuit with NMOS reset function under normal power-on con-ditions, an experimental setup is shown in the inset figure of Fig. 17(b). A ramp voltage with a rise time of 0.1 ms and a mag-nitude of 1.8 V is applied to power line with power line grounded to simulate the power-on condition. The measured voltage waveform on power line is shown in Fig. 17(b), where the voltage waveform is still remained as a ramp voltage without degradation. Thus, the ESD-clamping NMOS in the proposed power-rail ESD clamp circuit with NMOS reset func-tion has been verified to keep off while the IC is in the power-on condition.

2) TLU Immunity: With the TLU measurement setup in Fig. 5, the measured and responses on the proposed

power-rail ESD clamp circuit with of kV and

kV are shown in Fig. 18(a) and (b), respectively. With a

negative (positive) of kV ( kV), latchup-like

failure does not occur in Fig. 18(a) (Fig. 18(b)) because is not significantly increased and is not pulled down.

The TLU level of the proposed power-rail ESD clamp circuit with NMOS reset function and the original power-rail ESD clamp circuit with NMOS+PMOS feedback against system-level ESD test are listed in Table VII. Moreover, latchup-like failure does not occur in the proposed power-rail

TABLE VII

COMPARISON ONTLU LEVELSBETWEENPROPOSEDPOWER-RAILESD CLAMP

CIRCUITWITHNMOS RESETFUNCTION AND THEORIGINALPOWER-RAIL

ESD CLAMPCIRCUITWITHNMOS+PMOS FEEDBACKUNDERTLU TEST

Fig. 19. MeasuredV andI waveforms on the proposed power-rail ESD clamp circuit with NMOS reset function under system-level ESD test with ESD voltage of (a)010 kV and (b) +10 kV. No latchup-like failure occurs in this system-level ESD test.

ESD clamp circuit after TLU tests with ESD voltage of up to

kV and kV.

3) System-Level ESD Susceptibility: The measured and responses on the proposed power-rail ESD clamp circuit under system-level ESD tests with ESD voltages of kV and kV are shown in Fig. 19(a) and (b), respectively. With a negative (positive) ESD voltage of kV ( kV), the latchup-like failure does not occur in Fig. 19(a) (Fig. 19(b)) because the is not significantly increased and is not pulled down.

The susceptibility of the proposed power-rail ESD clamp circuit with NMOS reset function and the original power-rail ESD clamp circuit with NMOS+PMOS feedback against

TABLE VIII

COMPARISON ON THESUSCEPTIBILITYBETWEENPROPOSEDPOWER-RAIL

ESD CLAMPCIRCUITWITHNMOS RESETFUNCTION AND THEORIGINAL

POWER-RAILESD CLAMPCIRCUITWITHNMOS+PMOS FEEDBACKUNDER

SYSTEM-LEVELESD TEST

TABLE IX

COMPARISON OFHBM LEVEL, CDM LEVEL,ANDLAYOUTAREA

AMONGFIVEDIFFERENTPOWER-RAILESD CLAMPCIRCUITS IN A0.18-m CMOS PROCESS

system-level ESD test are compared in Table VIII. For the proposed power-rail ESD clamp circuit, latchup-like failure does not occur.

4) Chip-Level ESD Robustness: The chip-level ESD robust-ness (HBM and CDM) and layout area of the five different power-rail ESD clamp circuits integrated in this work are listed in Table IX. In order to provide a low impedance path between and power lines to efficiently discharge ESD current under chip-level ESD stresses conditions, the ESD-clamping NMOS has been drawn with a large device

dimension ( m m). Therefore, the layout

area of five different power-rail ESD clamp circuits is domi-nated by the ESD-clamping NMOS. ESD-transient detection circuits only occupy smaller part in the whole layout area, as compared with the layout area of ESD-clamping NMOS. The proposed power-rail ESD clamp circuit with NMOS reset function and the aforementioned four different power-rail ESD clamp circuits can pass HBM ESD stress of over 8 kV and CDM ESD stress of over kV.

CDM test in this work was carried out according to ESDA CDM test standard [20] and the package type of test chip is 40-pin side braze package. Five different power-rail ESD clamp circuits are all included in a test chip with separated and pins, where the die size of test chip is 1500 1500 m . During CDM ESD test on the test chip with different power-rail ESD clamp circuits, the direct charging method in the ESDA CDM test standard was used. The kV ESD voltages are directly charged into the pin that is connected with the

p-type substrate of the test chip, and then the corresponding sep-arated pin of the selected power-rail ESD clamp circuit is touched by external ground. After CDM test with ESD voltage of kV, the leakage current of power-rail ESD clamp circuits under 1.8-V bias was rechecked to be within 20% variation of its initial value. CDM ESD characterization is highly dependent on the package type, die size, and the adopted ESD test method [21]. A chip with large parasitic capacitance from the package or from the large die size often has a lower CDM ESD robust-ness.

VI. CONCLUSION

Some of advanced on-chip power-rail ESD clamp circuits with feedback loop have been found to suffer the latchup-like failure after system-level ESD tests. A modified design on the power-rail ESD clamp circuit with NMOS+PMOS feedback, by using NMOS reset function to turn off the ESD-clamping NMOS after system-level ESD tests, has been successfully veri-fied in a 0.18- m CMOS process. The proposed power-rail ESD clamp circuit with NMOS reset function can sustain the system-level ESD stress of over kV without causing latchup-like failure after system-level ESD tests. The proposed power-rail ESD clamp circuit has the advantages of smaller RC area, high ESD robustness, and no latchup-like failure, which is much suit-able for CMOS ICs in system applications.

ACKNOWLEDGMENT

The authors would like to thank Mr. C.-C. Tsai and Dr. T.-Y. Chen for their valuable technical discussions, and acknowledge the project support from Himax Technologies Inc., Taiwan.

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Ming-Dou Ker (S’92–M’94–SM’97–F’08) received

the Ph.D. degree from the Institute of Electronics, National Chiao-Tung University, Hsinchu, Taiwan, in 1993.

He was the Department Manager in the VLSI Design Division of the Computer and Commu-nication Research Laboratories (CCL), Industrial Technology Research Institute (ITRI), Taiwan. Since 2004, he has been a Full Professor in the Department of Electronics Engineering, National Chiao-Tung University, Taiwan. During 2006–2008, he served

as the Director of Master Degree Program in the College of Electrical Engi-neering and Computer Science, National Chiao-Tung University, as well as the Associate Executive Director of National Science and Technology Program on System-on-Chip (NSoC Office), Taiwan. In 2008, he was rotated to I-Shou University, Kaohsiung, Taiwan, as a Chair Professor and Vice President. In the field of reliability and quality design for circuits and systems in CMOS technology, he has published over 300 technical papers in international journals and conferences. He has proposed many inventions to improve reliability and quality of integrated circuits, which have been granted with 135 U.S. patents and 143 ROC (Taiwan) patents. His current research interests include reliability and quality design for nanoelectronics and gigascale systems, high-speed and mixed-voltage I/O interface circuits, on-glass circuits for system-on-panel applications, and biomimetic circuits and systems for intelligent prosthesis. He has been invited to teach and/or to consult on reliability and quality design for integrated circuits by hundreds of design houses and semiconductor companies in the worldwide IC Industry.

Prof. Ker has served as member of the Technical Program Committee and Session Chair of numerous international conferences. He has served as Asso-ciate Editor of IEEE TRANSACTIONS ONVLSI SYSTEMS. He has been selected as the Distinguished Lecturer in IEEE Circuits and Systems Society (for year 2006–2007) and in IEEE Electron Devices Society (since 2008). He was the President of Foundation in Taiwan ESD Association. In 2005, one of his patents on ESD protection design was awarded the National Invention Award in Taiwan. In 2008, he has been elevated as an IEEE Fellow “for contributions to electro-static protection in integrated circuits, and performance optimization of VLSI micro-systems.”

Cheng-Cheng Yen (S’07) received the B.S. degree

from the Department of Electrical and Control Engineering and the M.S. degree from the Institute of Electronics, National Chiao-Tung University, Hsinchu, Taiwan, in 1998 and 2000, respectively. He is currently working toward the Ph.D. degree in the Institute of Electronics, National Chiao-Tung University, Hsinchu, Taiwan.

His current research interests include detection cir-cuits and IC reliability.