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Metal-layer capacitors in the 65 nm CMOS process and the application

for low-leakage power-rail ESD clamp circuit

q

Po-Yen Chiu, Ming-Dou Ker

Department of Electronics Engineering and Institute of Electronics, National Chiao-Tung University, Hsinchu, Taiwan

a r t i c l e

i n f o

Article history: Received 25 March 2013

Received in revised form 7 August 2013 Accepted 15 August 2013

Available online 21 September 2013

a b s t r a c t

Between the metal–insulator–metal (MIM) capacitor and metal–oxide–metal (MOM) capacitor, the MIM capacitor has a better characteristic of stable capacitance. However, the MOM capacitors can be easily realized through the metal interconnections, which does not need additional fabrication masks into the process. Moreover, the capacitance density of the MOM capacitor can exceed the MIM capacitor when more metal layers are used in nanoscale CMOS processes. With advantages of lower fabrication cost and higher capacitance density, the MOM capacitor could replace MIM capacitor gradually in general inte-grated circuit (IC) applications. Besides, the MOM capacitor ideally do not have the leakage issue. Thus, the MOM capacitor can be used instead of MOS capacitor to avoid the gate leakage issue of thin-oxide devices in nanoscale CMOS processes. With the MOM capacitor realized in the power-rail electrostatic discharge (ESD) clamp circuit, the overall leakage is decreased from 828lA to 358 nA at 25 °C, as com-pared to the traditional design with MOS capacitor in the test chip fabricated in a 65 nm CMOS process. Ó 2013 Elsevier Ltd. All rights reserved.

1. Introduction

Capacitor is one of the basic components in integrated circuit (IC) applications. To meet different purposes of circuit applications, various types of capacitors have been developed with their own characteristics. Due to the limitation of capacitance per unit area, capacitors always occupy a considerable chip area in the whole cir-cuit layout. Therefore, saving the chip area is the important consid-eration in capacitor selection of CMOS ICs. Nowadays, three kinds of capacitors are commonly used in IC applications, which are MOS capacitor, metal–insulator–metal (MIM) capacitor, and me-tal–oxide–metal (MOM) capacitor. Among those capacitors, be-cause of thin gate oxide structure, MOS capacitor has the highest capacitance density per unit area. However, due to the disadvan-tages of non-linearity, higher temperature coefficient, lower break-down voltage, and sensitive to process variations, it could not be suitable for all circuit applications. As a result, MIM capacitor and MOM capacitor were created to overcome those disadvantages for circuit applications, which need reliable capacitor characteris-tics[1–6]. However, the capacitance densities of MIM and MOM capacitors are much lower than the MOS capacitor. Consequently, using MIM or MOM capacitors would increase more chip area to IC products.

When the CMOS process shrinks toward nanoscale, the capaci-tance density of the MOS capacitor ideally will be increased when the gate oxide becomes thinner. But, thinner gate oxide makes the gate-tunneling issue more serious to cause obvious gate leakage current in the devices[7,8]. To avoid leakage current, the simple method is using the thick-oxide device to realize the MOS capaci-tor. However, without using the dual oxide devices in some special purposes for circuit applications, the capacitors can only be real-ized by MIM or MOM capacitors. Fortunately, with the dimension shrinkage in advanced CMOS processes, the lateral and vertical intervals between metal interconnects are decreased, and the par-asitic capacitance between metal interconnects are increased. This feature assists the MOM capacitor to extend its capacitance den-sity. Furthermore, with the layout structure near the fractal geom-etries, the MOM capacitor can have the largest capacitance density in advanced CMOS processes[1].

In this paper, the gate-tunneling mechanisms and the impacts of gate leakage current on circuit applications are described in Sec-tion2. Two different metal-layer capacitors of MIM capacitor and MOM capacitor are compared in Section3. Finally, the experimen-tal verifications in silicon chip including the capacitance measure-ment and gate leakage in RC-based power-rail ESD clamp circuits are presented in Section4.

2. Gate-tunneling mechanisms and impacts of gate leakage current on circuit applications in advanced CMOS processes

Three gate-tunneling mechanisms were reported to explain the gate leakage in CMOS technology[7,8]. As shown in Fig. 1, three

0026-2714/$ - see front matter Ó 2013 Elsevier Ltd. All rights reserved.

http://dx.doi.org/10.1016/j.microrel.2013.08.011

q

This work was supported in part by National Science Council (NSC), Taiwan, under Contract of NSC 101-2221-E-009-141 and NSC 101-2220-E-009-020; and in part by ‘‘Aim for the Top University Plan’’ of the National Chiao-Tung University and Ministry of Education, Taiwan.

⇑Corresponding author. Tel.: +886 3 5131573; fax: +886 5 715412. E-mail address:mdker@ieee.org(M.-D. Ker).

Contents lists available atScienceDirect

Microelectronics Reliability

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mechanisms are electron tunneling from the conduction band (ECB), electron tunneling from the valence band (EVB), and hole tunneling from the valence band (HVB). When the gate oxide thick-ness is scaled down, the tunneling carriers across the potential bar-rier are increased with a great proportion to result in the gate leakage current. In nanoscale CMOS processes, the gate oxide thickness of MOS devices was only a few nanometers, which had obvious gate leakage current[7,8]. Since the gate leakage cannot be ignored, the gate-direct-tunneling model had been included in the BSIM4 MOSFET SPICE model for circuit simulation[9]. In the highly integrated digital circuits, the gate leakage current contrib-utes a significant off-state leakage to greatly increase the total power consumption[10–12]. In the analog circuits, the impacts of gate leakage include the limited current gain, mismatch, and noise[13]. Besides, the ESD protection scenarios also suffer the gate leakage issue, which causes large leakage current in the power-rail ESD clamp circuits[14–16].

The typical on-chip ESD protection scheme in a CMOS IC is illus-trated inFig. 2. The power-rail ESD clamp circuit is designed to provide a current discharging path during ESD stresses, and to be kept off under normal power-on conditions. The traditional design of the power-rail ESD clamp circuit is often consisted with an RC-based ESD-detection circuit to detect the ESD event and a huge ESD

clamp device (MNESD) to discharge ESD current. To effectively turn

on the circuit during ESD stresses and to completely turn off the circuit under normal power-on conditions, the RC time constant in the ESD-detection circuit should be designed around microsec-onds (

l

s)[17]. With consideration of area efficiency and fabrica-tion cost, the capacitor (C1) in the ESD-detection circuit was

often realized by the MOS capacitor. If such a traditional design is realized with the thin-oxide devices in nanoscale CMOS pro-cesses, the leaky MOS capacitor will cause serious leakage issue

[14]. For example, due to the gate leakage current in the MOS

Fig. 1. Gate-tunneling mechanisms in a Si/SiO2/Si structure[4,5].

Fig. 2. Typical on-chip ESD protection scheme.

Fig. 3. Simulated transient waveforms of the ESD-detection circuit with (a) ideal capacitor and (b) thin-oxide NMOS capacitor under normal power-on conditions in a 65 nm CMOS process.

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capacitor, the voltage at the node VXcannot be fully charged to VDD

after power-on. Therefore, the PMOS MP3in ESD-detection circuit

cannot be fully turned off, which causes another leakage path through the inverter in the ESD-detection circuit. Consequently, the gate voltage (VG) of MNESDwas not fully biased to VSS. The

par-tially turned-on MNESD(which is usually designed with large device

dimension to discharge ESD current) will conduct extra leakage current from VDDto VSSunder normal circuit operating conditions.

Fig. 3a and b shows the simulated results of ESD-detection circuits in a 65 nm CMOS process to observe the impact of gate leakage issue. The device dimensions used in the simulation are listed in

Table 1. Without the gate leakage of an ideal capacitor in the

Table 1

Device dimensions used in ESD-detection circuits for HSPICE simulation.

Type R1 C1 MP3(W/L) MN3(W/L)

With ideal capacitor 100 kX 2 pF 100lm 0:15lm

20lm 0:15lm With NMOS capacitor 100 kX 2 pF 29lm

28lm   100lm

0:15lm

20lm 0:15lm

Fig. 4. Schematic of MIM capacitor.

Fig. 5. Schematic of MOM capacitor.

Fig. 6. MOM capacitor structure used in this work.

Fig. 7. MOM capacitor structure layout (a) top view and (b) cross-sectional view.

Table 2

Estimated layout area of capacitors with different capacitances in a 65 nm CMOS process.

Type Ceq(pF) MY Area Ceqper unit area (fF/lm2 ) MOM cap. 1 3 27lm  28lm 1.32 4 23lm  24lm 1.81 5 21lm  22lm 2.16 2 3 36lm  37lm 1.50 4 32lm  33lm 1.89 5 29lm  30lm 2.30 5 3 57lm  58lm 1.51 4 50lm  51lm 1.96 5 45lm  46lm 2.42 MIM cap. 1 25lm  25lm 1.60 2 34lm  34lm 1.73 5 52lm  52lm 1.85 MOS cap. (NMOS 1 V) 1 26lm  28lm 1.37 2 34lm  37lm 1.59 5 48lm  55lm 1.89

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ESD-detection circuit, the terminal VXcan be biased to near the

power-supply voltage (VDD) of 1 V, as shown inFig. 3a. The

simu-lated overall leakage current from VDD is only 335 nA at 25 °C.

However, with the gate leakage of a thin-oxide NMOS capacitor in the ESD-detection circuit, the terminal VXcannot be biased to

VDD, as shown inFig. 3b. Thus, the simulated overall leakage

cur-rent is increased up to 586

l

A at 25 °C.

Although some circuit techniques had been reported to de-crease the impact from the gate leakage current of MOS capacitor

[15,16], the effective capacitance was reduced to decrease the trig-ger ability under ESD stress. To keep enough trigtrig-ger ability, more layout area of MOS capacitor will be required. Thus, if the MOS capacitor in the traditional RC-based ESD-detection circuit was re-placed by another capacitor which has no gate leakage issue, the traditional RC-based ESD-detection circuit can be still useful in nanoscale CMOS processes.

3. Metal-layer capacitors

Two metal-layer capacitors, MIM and MOM capacitors, are widely utilized in CMOS processes. With the parallel-plate struc-ture, the MIM capacitor is composed of two metal plates and a dielectric layer between them, as shown inFig. 4. In order to realize the structure with a shorter distance (D) and a different dielectric material (

e

X) to enhance the capacitance density, the fabrication of

MIM capacitor needs additional fabrication masks to define the top and bottom metal plates. Different to the MIM capacitor, the MOM capacitor is realized through the metal interconnections, as shown inFig. 5. Ideally, every pair of two metal lines can form the MOM capacitor. In the early generation of CMOS processes, the lateral and vertical intervals between metal layers were not close enough, the capacitance density of MOM capacitor was very low. However, with the dimension shrinkage in advanced CMOS processes, the parasitic capacitance between metal interconnections is increased significantly. For example, in a 0.25

l

m CMOS technology, the min-imum width (W) and space (S) of metal layers is 0.4

l

m. When the technology shrank to 65 nm, the minimum W and S of metal layers were decreased to 0.1

l

m. Besides, the MOM capacitor can be stacked with several metal layers (MY) to increase the capacitance

density in advanced CMOS technology.

Various types of MOM capacitors have been developed with dif-ferent configurations to increase the horizontal or vertical surface area[18–22]. The structure of MOM capacitor used in this work is shown inFig. 6 [20]. In the same metal layer, the lateral capac-itance (CLY) between the adjacent metal lines is shown inFig. 7a.

In different metal layers, the vertical capacitance (CAY-1) is shown

Fig. 8. RC-based power-rail ESD clamp circuit with (a) thin-oxide NMOS capacitor and (b) MOM capacitor.

Table 3

Device dimensions used in the power-rail ESD clamp circuits.

Type R1 C1 MP3 (W/L) MN3 (W/L) STSCR (W/L) With NMOS capacitor 100 kX 34lm  37lm 100lm 0:15lm 20lm 0:15lm 40lm 7:8lm With MOM capacitor 100 kX 36lm  37lm 100lm 0:15lm 20lm 0:15lm 40lm 7:8lm Table 4

Measured capacitances of MIM and MOM capacitors under the bias voltage of 1 V, 0 V, and 1 V (at reference frequency of 100 kHz).

Type Ceq (pF)

CMeasured MYArea CMeasured per unit area (fF/lm2) VB= 1 V VB= 0 V VB= 1 V MOM cap. 1 1.14 pF 1.14 pF 1.14 pF 3 27lm  28lm 1.51 1.15 pF 1.15 pF 1.15 pF 4 23lm  24lm 2.08 1.17 pF 1.17 pF 1.17 pF 5 21lm  22lm 2.53 2 2.27 pF 2.27 pF 2.27 pF 3 36lm  37lm 1.70 2.30 pF 2.30 pF 2.30 pF 4 32lm  33lm 2.18 2.35 pF 2.35 pF 2.35 pF 5 29lm  30lm 2.70 5 5.71 pF 5.71 pF 5.71 pF 3 57lm  58lm 1.73 5.72 pF 5.72 pF 5.72 pF 4 50lm  51lm 2.24 5.74 pF 5.74 pF 5.74 pF 5 45lm  46lm 2.77 MIM cap. 1 0.997 pF 0.997 pF 0.997 pF 25lm  25lm 1.60 2 1.973 pF 1.973 pF 1.973 pF 34lm  34lm 1.71 5 4.990 pF 4.990 pF 4.990 pF 52lm  52lm 1.85 Fig. 9. Chip micrograph of the fabricated test devices and the power-rail ESD clamp

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inFig. 7b. With this kind of arrangement, the MOM capacitor takes the advantage of both the lateral and vertical fields to extend the capacitance density. The capacitance could be estimated as:

CLateral¼ L  ðFX 1Þ  CLY;

CVertical¼ L  FX CAY1; and

CTotal¼ CLateralþ CVertical: ð1Þ

The FX is finger numbers. L is metal length. CLY is coupling

capacitance per unit length between the metal lines in the same metal layer. The CAY-1is area capacitance per unit length between

metal layers.Table 2shows the estimated results of device layout area with different capacitors. With more metal layers stacked, the MOM capacitor can have the smallest area to achieve the same de-sired capacitance.

4. Experimental results

To investigate the capacitance of different metal-layer capaci-tors, the test devices of MIM and MOM capacitors had been fabri-cated in the silicon chip with a 65 nm CMOS process. In addition, for investigating gate leakage issue of thin-oxide MOS capacitor, the test devices of stand-alone PMOS and NMOS capacitors were also included in the test chip. Moreover, to investigate the impact of gate leakage issue in RC-based ESD-detection circuit, power-rail ESD clamp circuits with different capacitors were implemented in the test chip. With the same capacitance of MIM and MOM capac-itor realized in power-rail ESD clamp circuit, circuit behaviors would be almost identical under the same RC time constant. For emphasizing the impact of gate leakage issue, only MOM capacitor was composed in the power-rail ESD clamp circuit to observe the gate leakage issue as compared to the thin-oxide MOS capacitor. Thus, two power-rail ESD clamp circuits with thin-oxide NMOS capacitor and MOM capacitor were fabricated in the test chip as shown inFig. 8a and b, respectively.

All device dimensions used in the power-rail ESD clamp circuits are listed inTable 3. With a capacitance of 2 pF, the layout area of MOM capacitor realized with 3 metal layers is 36

l

m  37

l

m. The thin-oxide NMOS capacitor was implemented with a similar layout area of 34

l

m  37

l

m (channel width WC= 29

l

m and channel

length LC= 28

l

m). Except the capacitor, all devices used in these

two circuits have the identical device dimensions. Instead of large NMOS device (MNESD), the substrate-triggered silicon-controlled

rectifier (STSCR) was used as the ESD clamp device, because SCR had been proven to have the highest ESD robustness under the smallest silicon area[23]. Without the thin gate oxide in the P– N–P–N structure of SCR, SCR is free from the gate leakage issue.

The chip micrograph of test devices and the fabricated power-rail ESD clamp circuits is shown inFig. 9.

4.1. Measured capacitance of metal-layer capacitors

Table 4 shows the measured capacitance of two metal-layer capacitors under the bias voltage (VB) at 1 V, 0 V, and 1 V (at a

ref-erence frequency of 100 kHz and temperature of 25 °C). Even the temperature was heated to 125 °C, each capacitor has the stable

Table 5

Measured capacitances of MIM and MOM capacitors under different reference frequencies.

Type Ceq(pF) CMeasured MY Area CMeasuredper unit area

@100 kHz @500 kHz Variation (%) @100 kHz (fF/lm2 ) @500 kHz (fF/lm2 ) MOM cap. 1 1.14 pF 1.13 pF 0.88 3 27lm  28lm 1.51 1.49 1.15 pF 1.14 pF 0.87 4 23lm  24lm 2.08 2.07 1.17 pF 1.16 pF 0.85 5 21lm  22lm 2.53 2.51 2 2.27 pF 2.25 pF 0.85 3 36lm  37lm 1.70 1.69 2.30 pF 2.28 pF 0.87 4 32lm  33lm 2.18 2.16 2.35 pF 2.33 pF 0.85 5 29lm  30lm 2.70 2.68 5 5.71 pF 5.67 pF 0.70 3 57lm  58lm 1.73 1.72 5.72 pF 5.68 pF 0.70 4 50lm  51lm 2.24 2.23 5.74 pF 5.69 pF 0.85 5 45lm  46lm 2.77 2.75 MIM cap. 1 0.997 pF 0.996 pF 0.10 25lm  25lm 1.60 1.59 2 1.973 pF 1.972 pF 0.05 34lm  34lm 1.71 1.71 5 4.990 pF 4.986 pF 0.08 52lm  52lm 1.85 1.84

Fig. 10. Measured gate leakage current of the thin-oxide (a) PMOS and (b) NMOS capacitor in a 65 nm CMOS process under different temperatures.

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capacitance as shown inTable 4. However, with the different refer-ence frequencies in the measurement, the capacitance variations of two capacitors are quite different. The measured capacitances un-der the reference frequencies of 100 kHz and 500 kHz at 0 V bias are summarized inTable 5. As shown inTable 5, more capacitance variation is observed in MOM capacitors when the frequency is in-creased. The maximum variation in MOM capacitor is 0.88%, but the variation in MIM capacitor is only 0.1%. In addition to the capacitor’s structure, the most difference is the dielectric layer within two capacitors. Due to the MOM capacitor is realized from the metal interconnects, the dielectric layers are mainly formed by SiO2 and low-k materials [24]. But, in the MIM capacitor, the

dielectric layer was often implemented with the high-k materials to increase the capacitance density [25]. Some relative studies had been reported that the frequency dependencies were various with different materials to cause the capacitance loss[2,26]. How-ever, the characteristics of different materials were not further analyzed in this work.

Besides, compared to the evaluated capacitances, more capaci-tances are measured in MOM capacitors. Thus, the accuracy of capacitance estimation (1) in MOM capacitor should be further im-proved. However, the occupied area of MOM capacitor actually can be the smallest when more metal layers are used.

4.2. Leakage current

Fig. 10a and b shows the measured gate leakage currents of the

stand-alone thin-oxide (1 V) PMOS and NMOS capacitors

(WC= 29

l

m and LC= 28

l

m) with the gate oxide thickness of

20 Å in a 65 nm CMOS process. Under 1 V bias across the MOS

capacitor, the gate leakage currents of PMOS and NMOS capacitors at 25 °C are 21.2

l

A and 50.9

l

A, respectively. The leakage currents among the fabricated capacitors under 1 V bias and different tem-peratures are summarized inTable 6. With such huge leakage cur-rent through the MOS capacitor, the thin-oxide MOS capacitor is no longer suitable for circuit applications in the 65 nm CMOS process. On the contrary, without the thin-oxide structure in MIM and MOM capacitors, these two capacitors’ leakage currents are quite low (<20 pA). The leakage currents between two power-rail ESD clamp circuits under different temperatures with VDDof 1 V are

compared inFig. 11. The leakage currents are also summarized in

Table 7. Comparing with the leakage current of the stand-alone thin-oxide NMOS capacitor, much higher leakage current (828

l

A at 25 °C) is observed in the power-rail ESD clamp circuit with NMOS capacitor, which indicates that the leaky MOS capacitor cer-tainly causes extra leakage paths in the ESD-detection circuit. On the contrary, with almost no leakage current in MOM capacitor, the power-rail ESD clamp circuit with MOM capacitor has the low-est leakage current of only 358 nA. The total leakage current of the power-rail ESD clamp circuit with MOM capacitor is three orders smaller than that with NMOS capacitor from low temperature to high temperature.

4.3. ESD robustness

To investigate the turn-on behavior of the ESD clamp device with ESD-detection circuit during ESD event, the transmission line pulse (TLP) with 100 ns pulse width and 10 ns rise time was used to measure the second breakdown current (It2) of ESD protection

circuits. The TLP-measured I–V characteristics of the STSCR with

Table 6

Measured leakage currents amount fabricated capacitors under different temperatures.

Leakage current at VG= 1 V 25 °C 50 °C 75 °C 100 °C 125 °C

NMOS cap. (2 pF) (layout area of 34lm  37lm) 50.9lA 51.3lA 53.3lA 55.5lA 57.6lA PMOS cap. (2 pF) (layout area of 34lm  37lm) 21.2lA 22.0lA 22.2lA 22.9lA 23.6lA MIM cap. (2 pF) (layout area of 34lm  34lm) <20 pA <20 pA <20 pA <20 pA <20 pA MOM cap. (2 pF) (layout area of 36lm  37lm) <20 pA <20 pA <20 pA <20 pA <20 pA

Fig. 11. Measured leakage currents between two fabricated power-rail ESD clamp circuits under different temperatures.

Table 7

Measured leakage currents and ESD robustness of the power-rail ESD clamp circuits.

Circuit type Leakage current at VDD= 1 V ESD robustness

25 °C 50 °C 75 °C 100 °C 125 °C HBM MM

With NMOS capacitor 828lA 1.01 mA 1.13 mA 1.36 mA 1.51 mA 4 kV 350 V

With MOM capacitor 358 nA 441 nA 633 nA 1.12lA 1.91lA 4 kV 350 V

Fig. 12. TLP-measured I–V characteristics of the STSCR with and without the ESD-detection circuit.

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and without the ESD-detection circuit are shown inFig. 12. With-out any trigger signal, the original trigger voltage (Vt1) of

stand-alone STSCR (width = 40

l

m) device is 10.7 V, and the It2is 2.3 A.

With the trigger signal from ESD-detection circuit, the Vt1of the

STSCR device is significantly reduced to 3 V and the It2is 2.5 A.

The lower Vt1of the power-rail ESD clamp circuit ensures its

effec-tive ESD protection capability. In addition, the holding voltage of STSCR shown inFig. 12is 2.5 V, so the proposed power-rail ESD clamp circuit is free from latchup issue in the CMOS ICs with VDD

of 1 V. The human-body-model (HBM) and machine-model (MM) ESD levels of these two power-rail ESD clamp circuits are evaluated by the ESD simulator. Measured ESD levels are listed inTable 7. The failure criterion is defined as 30% shift in the leakage current under 1 V VDDbias. The power-rail ESD clamp circuit with STSCR

of only 40

l

m width can achieve ESD robustness of 4 kV in HBM and 350 V in MM, respectively.

5. Discussion

Comparing the evaluated results of MOM capacitor, more capacitance is observed in the measured results (as listed in Ta-ble 4). In (1), each finger’s edge capacitance was ignored. To obtain more accurate capacitance in this structure, the capacitance esti-mation of MOM capacitor should be fixed in the following equa-tions, where CFEis the capacitance from all finger’s edge. Thus,

the maximum capacitance variation is decreased from 14.9% to 5.8%, as shown inTable 8.

CLateral¼ L  ðFX 1Þ  CLY;

CVertical¼ L  FX CAY1;

CFE¼ FX MY CEdge; and

CTotal¼ CLateralþ CVerticalþ CFE: ð2Þ

6. Conclusion

Two metal-layer capacitors, MIM and MOM capacitors, have been investigated in this work with a 65 nm CMOS process. With more metal layers utilized, the occupied silicon area of MOM capacitor can be smaller than MIM capacitor under the same capacitance. Although the MIM capacitor was reported to have the best characteristics in some CMOS processes, it increases the fabrication cost due to the additional masks. Different from the structure of MIM capacitor, the MOM capacitor can be easily real-ized by the metal interconnections. Without additional mask, the integration complexity and fabrication cost for MOM capacitor are not increased. With the advantages of higher capacitance den-sity and lower fabrication cost, the MOM capacitor is more suitable than the MIM capacitor for general circuit applications in the nano-scale CMOS processes.

Acknowledgments

The authors would like to express their thanks for the TLP equipment supported from Hanwa Electronic Ind. Co., Ltd., Japan.

The test chips of this work were fabricated under the support of TSMC University Shuttle Program.

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[26]Chen S-B, Lai C-H, Chin A, Hsieh J-C, Liu J. High-density MIM capacitors using Al2O3and AlTiOxdielectrics. IEEE Electr Dev Lett 2002;23(4):185–7. Table 8

The percentage of capacitance variation within the estimations.

MY 3 4 5 3 4 5 3 4 5

CMeasured 1.14 pF 1.15 pF 1.17 pF 2.27 pF 2.30 pF 2.35 pF 5.71 pF 5.72 pF 5.74 pF

Capacitance variation In (1) 12.3% 13% 14.5% 11.9% 13% 14.9% 12.4% 12.6% 12.9%

數據

Fig. 2. Typical on-chip ESD protection scheme.
Fig. 8. RC-based power-rail ESD clamp circuit with (a) thin-oxide NMOS capacitor and (b) MOM capacitor.
Table 4 shows the measured capacitance of two metal-layer capacitors under the bias voltage (V B ) at 1 V, 0 V, and 1 V (at a
Fig. 10 a and b shows the measured gate leakage currents of the

參考文獻

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