the improvement of transient response. In conventional design, low bandwidth of less than 20 Hz that rejects ac source of 60/120 Hz cou-pling deteriorates system reliability in case of output load variation. Contrarily, the proposed TLM can automatically adjust bandwidth to rapidly increase or decrease inductor current to shorten tran-sient response time. Besides, in the steady state, system stability can be guaranteed by low-frequency compensation pole without being affected by the TLM. The test circuit fabricated in a VIS 500 V UHV laterally diffused metal–oxide–semiconductor transis-tor process demonstrates that the highly integrated PFC controller with the proposed TLM has high power factor of 99%, high effi-ciency of 95%, and high power driving capability of about 90 W. The improvement in transient response is twofold faster than in conventional PFC design with output load variation from 90 to 20 W and vice versa.
Index Terms—Fast transient response, power factor correction (PFC), triple loop modulation (TLM).
I. INTRODUCTION
D
UE to the lack of energy, high reliability and efficiency become the focus of current green power systems. Power factor correction (PFC) can shape the input current of offline power supplies in phase with the input ac voltage in order to increase the real power available from the ac source [1]. Gen-erally speaking, active PFC with constant on-time control tech-nique is used to improve the power factor (PF) value to about 0.99 [2]–[12]. The conventional PFC architecture uses a con-stant on-time control technique in boundary conduction mode (BCM), as shown in Fig. 1(a). In the conventional constant on-time control architecture, the error amplifier (EA) is used to set up the output power level through the error signal VEAO. The comparator compares the saw-tooth signal with the VEAO to determine the on-time period. On the other hand, the off-time period is determined by the detection of the zero inductor cur-rent. Thus, the off time varies with the line voltage level andManuscript received July 17, 2012; revised September 24, 2012; accepted October 29, 2012. Date of current version December 24, 2012. This work was supported by the National Science Council, Taiwan, under Grant NSC 100-2220-E-009-050 and Grant NSC 100-2220-E-009-055. Recommended for publication by Associate Editor K. Ngo.
The authors are with Institute of Electrical Control Engineering, National Chiao Tung University, Hsinchu 300, Taiwan (e-mail: khchen@cn.nctu.edu.tw). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TPEL.2012.2227506
Fig. 1. (a) Conventional PFC architecture uses constant on-time control tech-nique in BCM. (b) Small-signal analysis reveals low bandwidth contributed by the large compensation capacitor CE A.
the output power. It results in the switching frequency of the constant on-time control that is variable. There are many differ-ent variable switching frequency control methods as shown in Table I. These control methods are usually used to improve PF and total harmonic distortion (THD) but the transient response time is not improved obviously.
Here, system bandwidth of the active PFC controller needs to be low enough to filter out noise from the ac line revealed by small-signal analysis, as shown in Fig. 1(b). Therefore, a large compensation capacitor CEA is connected to the output EA [13]–[16]. Resulting large over-/under-voltage may seri-ously affect the reliability of the next stage or the application system (see Fig. 2). The overshoot problem will cause two se-rious issues throughout the duration of the next IC stage: 1) hot carrier injection and 2) high voltage stress on core gate oxide. Hot carrier injection will be affected by drain-to-source volt-age, shortening lifetime and affecting external power MOSFET. Higher output voltage will increase response internal power volt-age, while higher power supply voltage will shorten the lifetime of core gate oxide. As shown in (1), lifetime is inversely related to power supply voltage, which is provided by the output of the
TABLE I
COMPARISONTABLEWITHDIFFERENTVARIABLESWITCHINGFREQUENCYCONTROL
Fig. 2. (a) Large transient over-/under-voltage reduces system reliability. (b) TLM prevents over-/under-voltage. (c) Output power variation.
PFC system
Time to failure ∝ (VC C)−n ∗ exp (Ea/(KT ))∗ (AOX)−1/β (1) where AOX is the total gate oxide area on silicon, T is the absolute junction temperature, VC C is the gate voltage, n is the
power law exponent for core thin gate oxide, Eais the thermal
activation energy, k is Boltzmann’s constant, and b is Weibull shape factor.
On the other hand, the undershoot problem may cause shut-down and deteriorate system stability of the next stage. There-fore, the proposed PFC architecture needs to carefully consider the reliability and the transient response time in order to improve lifetime of electronics. To improve reliability and transient re-sponse time, the PFC with the triple loop modulation (TLM) technique is proposed. The comparison waveform of modified ripple is shown in Fig. 2. The output ripple will be detected to trigger the TLM technique. With the hysteresis window de-fined by the lower bond voltage VLand the upper bond voltage
VH, the TLM technique will restrain output ripple in the design
specifications. Once output ripple is restrained, extension of reli-ability follows naturally. The TLM technique not only prolongs reliability, but also promotes stability in the steady state. The operating frequency needs to be larger than 35 kHz for avoiding audio noise. Owing to the usage of electromagnetic interference (EMI) filter, the upper limit of the operating frequency is around 217 kHz at 220 Vac.
The organization of this paper is as follows. Section II in-troduces the circuit implementation of the TLM technique. The small-signal analysis of the proposed PFC technique with the TLM is shown in Section III. Section IV introduces the
de-sign of the components for the controller. Experimental results are presented in Section V. Finally, conclusions are made in Section VI.
II. CIRCUITIMPLEMENTATION
As shown in Fig. 1(b), the EA is compensated by a very low frequency pole, which is generated by a large compensation capacitor CEA. The CEA can remove noise from the ac power line but may deteriorate the transient response in case of large output load step variation. To facilitate immediate reaction to load transient response, the TLM was introduced and triggered during the load transient period in order to rapidly settle the out-put of EA even under low bandwidth. Fig. 3 shows the proposed PFC architecture with the TLM, which involves two additional feedbacks from the output node Vout.
The flow diagram of the TLM technique is shown in Fig. 4. Normally, the steady-state operation controlled by the primary modulator is similar to that of original PFC controller. The al-lowable output variation is in the range of 10% of the nominal output voltage, 400 V. That is to say, the output voltage is limited within the range from 360 to 440 V. Thus, VHand VLare selected
as 2.75 and 2.25 V, respectively, because the feedback factor is 2.5 V/400 V, which is determined by the ratio of feedback re-sistors. When the output power has a light-to-heavy load step and simultaneously the feedback voltage VFBis smaller than the threshold voltage VL, the secondary modulation is triggered to
help transient response. That is, the slowly increased VEAby the primary modulator will be modulated by the secondary modu-lator to speed up the response time, and thus, the undershoot voltage can be reduced. Once the VFB voltage is pulled back to be larger than the VL, the system will automatically switch to
the primary modulation.
On the other hand, when the output power has a heavy-to-light load step and the feedback voltage VFB is larger than the threshold voltage VH at the same time, the third modulation
starts to help transient response. The third modulator can rapidly pull low the VEAO not the VEAso as to decrease the overshoot voltage without decreasing the system stability since the VEA is still controlled by the primary modulator. The TLM circuit can effectively reduce overshoot and undershoot voltages to decrease power loss and increase system reliability. That is, in case of load variation, the variation of the Vout is kept within the allowable transient voltage variation range, as depicted in Fig. 2.
Fig. 3. Proposed PFC architecture with the TLM.
Fig. 4. Flowchart of the TLM system.
A. Primary Modulator
As shown in Fig. 5(a), the primary loop modulation circuit contains the EA, which is shown in Fig. 5(b). The differential in-puts of the EA are composed of two high-voltage (HV) devices
Mp5 and Mp6 to avoid a high voltage stress that may damage
the input devices from the feedback node. The EA works as a transconductance amplifier to convert the voltage difference between Vref and VFB to a difference current with an output conductance of 120 μA/V. Thus, the bandwidth will be around 20 Hz determined by the compensation capacitor of 1 μF. Mean-while, the inverting input of the EA is connected to the VFB. The EA’s output is compensated by a large compensation capacitor
CEA and filtered by a unity-gain buffer OP2, which is com-posed of a two-stage operational amplifier, to yield the signal
VEAO. The value of VEAOcan determine on-time value through the peak current control method. The on-time value is nearly constant to guarantee that the PF is sufficiently high to satisfy the requirements of the European Norm EN61000-3-2. In case of light-to-heavy load changes, rapid increase at the VEA can effectively improve the transient response due to the instant ex-tension of bandwidth. On the other hand, rapid decrease at the
VEA will cause the ringing effect as shown in Fig. 5(c) when the load changes from heavy to light or the system in the startup
Fig. 5. (a) Primary modulator. (b) Schematic of the EA circuit (c) Ringing effect due to the fast pulling down at the VE A when load changes from heavy
to light. (d) Fast settling owing to the adequate pulling down at the VE A Owhen
Fig. 6. TLM technique comprises of secondary and third modulators to im-prove transient response for high reliability.
period. Therefore, the suitable control node locates at the VEAO, which is the buffer output of the EA. As shown in Fig. 5(d), the system can be smoothly and rapidly settled down to its regulated voltage.
B. Secondary and Third Modulators
TLM (see Fig. 6) can improve transient response and reduce over-/under-shoot voltage due to the two additional insertion loops. Bandwidth will be instantly increased for a while to re-duce transient response time.
In case of a large increasing load step, the scaled signal VFB, which is feedback from the output, is filtered by a unity-gain buffer OP1 to remove large switching noise. The circuit diagram of the OP1 is depicted in Fig. 7(a). The differential input pairs
Mp4 and Mp5 are HV N-MOSFET devices to endure a 30 V
high voltage across its gate–source voltage Vgs. The decrease in VFB with a large step will reveal output power. VFB is com-pared with VL, which defines allowable undershoot voltage at
the output, to determine current injection to VEA, which is con-nected to a large compensation capacitor. In other words, there is an extra current to speed up the response time at the VEA. As a result, bandwidth will be extended to improve transient response and decrease undershoot voltage. Once VFB is higher than VL, current injection will cease. Meanwhile, the system
bandwidth is recovered to less than 20 Hz, as defined by the primary modulator.
On the other hand, if output power is suddenly decreased, the low bandwidth in conventional design does not have the ability to suppress overshoot voltage. Thus, the third modulation loop is inserted to pull down the value of VEAO through a unity-gain buffer OP5. The circuit of amplifier OP5, a two-stage op-amp and as shown in Fig. 7(b), only provides current sinking capability to rapidly pull down the voltage level at the
VEAO. Here, the current sinking capability is determined by the transistor Mn 3.
Lower values of VEAO result in smaller on-time values to effectively clamp input power, thereby suppressing overshoot voltage. The third modulator will release domination of VEAO
due to suppression of output voltage although VEAvalue has not been settled because of low bandwidth. Thus, the controller is reverted to heavy-to-light conditions and the third modulation loop is triggered again. After several switching cycles, VEAwill be successfully settled and the third modulator will no longer be activated. In other words, the control authority is changed between the primary modulator and the third modulator for small overshoot voltage during the recovery time of the output voltage. Importantly, the third modulator is not connected to
VEA, since the instant pull-down will trigger the ringing effect as shown in Fig. 5(c), which depicts that the system experiences oscillation between the secondary and the third modulators. The third modulator that connects to the VEAO can effectively improve the stability. Finally, the third modulator is turned off and control authority is returned to the primary modulator in the steady state.
C. On-Time and Off-Time Controlling Circuits
The on-time period is determined by the comparison of the saw-tooth signal Vsaw and the VEAO. Fig. 8 shows the saw-tooth generator circuit, which uses a constant current to charge the capacitor to get a ramp-up signal. Besides, the max-on-time limiter is also implemented to limit the maximum on-max-on-time value for avoiding the overloading and audio noise through the comparison of a higher voltage of 3 V.
On the other hand, the off-time period is determined by the zero current detection (ZCD) circuit in Fig. 9. In other words, the ZCD circuit decides the begging of the next switching. The
Zd pin is used to detect the zero inductor current through the
auxiliary winding in the BCM operation. The signal VZC Dvaries within the expression shown as
− Naux Nb VIN ≤ VZC D ≤ Naux Nb · (Vout− VIN) . (2) A negative voltage is not allowable for the integrated circuit fabricated in a standard CMOS process due to the latch-up problem. Thus, the ZCD circuit can protect the PFC controller from being damaged by latch-up caused by the negative voltage. If the voltage at the Zd pin is gradually smaller than zero, the
transistor M2will form a negative feedback to clamp the voltage still higher than 0 V. The operational amplifier OP1 can force the VZR 1 to be approximately equal to the VR EF2. As a result, the voltage of the VZR 1is expressed as
VZR 1 = VR EF2+ (VG S4− VG S3) . (3) When the pulsewidth modulation (PWM) signal is equal to zero, the stored energy in the inductor starts to release to the output. The VZC D starts to decrease since the energy in the in-ductor dries out. Once the signal Zdvoltage is lower than VR EF,
the GD signal will be set high, again. The power MOSFET will be turned ON to trigger one new switching cycle.
As we know, the switching noise will degrade the stabil-ity. The spike-free circuit in Fig. 10 is utilized to avoid high switching noise when the power MOSFET is turned ON. Si-multaneously, the current limiting mechanism will be disabled during the operation of the spike-free circuit in order not to shut
Fig. 7. Operational amplifiers. (a) OP1 circuit is a two-stage architecture with two HV differential input devices. (b) OP5 circuit simply provides the current sinking capability.
Fig. 8. Schematic of the saw-tooth circuit.
Fig. 9. Schematic of the ZCD circuit.
Fig. 10. Schematic of the spike-free circuit.
down the overall operation. The spike-free circuit gets rid of the switching noise without any external low-pass filters. Besides, the spike-free time varies according to the loading condition, indicated by the signal VEAO in Fig. 3. That is, the voltage
Fig. 11. Schematic of the minimum off-time circuit.
across the resistor R1 defines the current flowing through the transistor M3 in Fig. 10. Lower VEAO leads to higher current flowing through M3.
The power MOSFET can be turned OFF to deliver energy to the output; the minimum off-time circuit is shown in Fig. 11. The minimum off-time also needs to be adjusted according to the loading indication signal VEAO, which is generated by the EA in Fig. 3. In Fig. 11, the voltage across the resistor R1 defines the current flowing through the transistor M4. Lower
VEAO leads to higher current flowing through M4. As a result, the charging current as expressed in (4) for the capacitor C1 is drastically decreased to generate a longer minimum off-time
IC 1 = Ibias− k1· k2·
VR EF− VEAO
R1
. (4)
D. Preregulator and Driver
Two circuits in the PFC controllers that need to face high voltage are the preregulator and the driver. The preregulator that supplies internal voltage for the PFC controller is depicted in Fig. 12. The feedback is composed of diode-connected low-voltage (LV) P-type MOSFETs. The HV devices including N-type and P-type can endure a 20 V high voltage across their drain–source voltage. Furthermore, the preregulator is stabilized by an MOSFET capacitance Mn c1. Besides, the Zener diodes
are used to clamp the maximum supply voltage to protect inter-nal devices from being damaged by high voltage.
The HV driver circuit in Fig. 13 can be used to drive external power MOSFETs for minimizing conduction loss. The driver
Fig. 12. Schematic of the preregulator circuit.
Fig. 13. Schematic of the driver circuit.
Fig. 14. Small-signal model of the TLM technique when the secondary loop modulation is activated.
circuit is composed of level shifter and nonoverlap circuit. The level shifter, composed of M1, M2, M3, M4, and INV1, can boost the internal reference voltage to a high input voltage Hv dd.
The nonoverlap circuit can avoid the shoot-through current from
M5 to M6. Besides, the output voltage will be clamped by internal Zener diodes Zd1, Zd2, and Zd3, and the source follower
M5.
III. SMALL-SIGNALANALYSIS OF THETLM
These two additional feedbacks can help in the recovery of EA output under different load conditions. Small-signal model of the proposed TLM can be represented as in Figs. 14 and 15 if output load has light-to-heavy and heavy-to-light changes, re-spectively. The output-to-duty transfer function is formed by the combination of three feedback transfer functions under different load conditions.
The primary modulator resembles conventional design with the characteristic low bandwidth. The secondary modulator can adapt to load variation in order to adjust bandwidth for fast transient response when the output has an instantly increasing power. On the other hand, the third modulator can prevent over-shooting of the output in case of rapidly decreasing power.
A. Analysis of Primary Loop Modulation
The primary modulator consists of an EA with a large com-pensation capacitor CEA, as shown in Fig. 1(b). The transfer function of the primary modulator can be derived as
ˆ vEA ˆ vFB =−Gm PR IRo 1 1 + s ωP ( d o m i n a n t )
where ωP (dom inant) =
1 RoCEA (5) BW = Gm PR IRo· 1 RoCEA =Gm PR I CEA . (6)
DC gain is the product of EA’s transconductance (Gm PR I)
and output resistance Ro. The low-frequency pole ωP (dom inant)
produced by the primary modulator significantly decreases bandwidth (BW) as shown in (6) due to the large CEA.
B. Analysis of Secondary Loop Modulation
In case of increasing output power, the TLM will activate the secondary modulator to extend bandwidth if the VFB is lower than the low threshold voltage VL. In other words, the secondary
modulator can avoid undervoltage and get high reliability. As illustrated in Fig. 14, the secondary modulator contributes an-other transconductance (Gm SEC) so that the transfer function
from VFB to VEAcan be modified as
ˆ vEA ˆ vFB =−(Gm PR I+ Gm SEC)(RoRo SEC)· 1 1 +ω s P ( d o m i n a n t )
where ωP (dom inant) =
1 ( Ro Ro SEC)CEA (7) BW = (Gm PR I+ Gm SEC) ( Ro Ro SEC) · 1 ( Ro Ro SEC)CEA =Gm PR I+ Gm SEC CEA . (8)
Due to the insertion of Gm SEC, the combination of
pri-mary modulator and secondary modulator in (7) can enhance the equivalent transconductance from Gm PR I to the sum of
Gm PR I and Gm SEC. The equivalent resistance changes from
Ro to a parallel resistance Roin parallel with Ro SEC. The
re-duced equivalent resistance pushes the dominant pole to higher frequencies. As a result, bandwidth as shown in (8) becomes higher than that in the steady state. Higher bandwidth means transient response can be greatly improved. Fig. 15(a) shows the Bode plot of the primary modulation only. As the load steps from light to heavy, the Bode plot of the secondary modulation is shown in Fig. 15(b). Obviously, the bandwidth is effectively extended and the gain is also improved.
Fig. 15. Bode plot (a) with the primary modulation or (b) with the secondary modulation.
Fig. 16. Small-signal model of the TLM technique when the third loop mod-ulation is activated.
C. Third Loop Modulation Technique
In case of output power change from heavy to light, the third modulator CT H I(s), as shown in Fig. 16, will be activated once
the VFB is higher than the higher threshold voltage VH. The
transfer function is derived as (9). Therefore, the transfer func-tion from VFB to VEAis modified to (10)
CT H I(s) = Av 0· 1 1 +ωs T H I (9) ˆ vEAO ˆ vFB = (−Gm PR IRO)· 1 1 + s ωE A · 1 1 + s ωT H I + Av 0· 1 1 + ωs T H I = (−Gm PR IRO+ Av 0)· 1 + s ωZ 1 + s ωE A ·1 + s ωT H I
Fig. 17. Bode plot with and without the third modulator.
and Av 0 =− R2 R1 ; ωEA= 1 ROCEA ; ωT H I = 1 REAO· CEAO ωZ = Gm PR IRO − Av 0 Av 0 · 1 ROCEA . (10)
Two poles and one zero appear in (10). The first pole ωEA composed of RO and CEA is the low-frequency pole of the
primary modulator. The second pole ωT H I composed of the equivalent resistance REAO and capacitor CEAO at the VEAO is a high-frequency pole. The zero ωZ produced by the parallel
path can almost cancel the effect of ωEA, as shown in Fig. 17. The whole system can be seen as a one-pole system with an extended bandwidth
Fig. 18. (a) Chip micrograph. (b) Prototype of the PFC converter with the TLM technique.
Fig. 19. Waveforms of a conventional PFC controller when (a) output load changes from 20 to 90 W and (b) from 90 to 20 W.
Av 0is the low-frequency gain of the transfer function of the
third modulator, which can provide high-bandwidth response to rapidly pull down the VEAO level through the OP5, as shown in Fig. 6. As VFB exceeds VH, CT H I(s) will provide a high-bandwidth path to reflect the variation of output voltage. How-ever, this rapidly pulling-down operation disappears if VFB is lower than VH, again. In the meanwhile, CT H I(s) will be
by-passed and the system automatically returns to the control of primary modulator. In the steady state, the primary modulator takes over control authority.
IV. DESIGN OF THECOMPONENTS FOR THECONTROLLER
Some design values of the components are described in this section to show the design specifications.
Fig. 20. Waveforms of the proposed PFC with TLM when (a) output load changes from 20 to 90 W and (b) from 90 to 20 W.
A. Design of Inductor Value
To avoid the switching frequency below the audio frequency, the minimum switching frequency fs,m in, which happens at
maximum ac line input voltage, is needed to be defined as 35 kHz. According to the law of energy conservation, the ap-propriate inductor value of the proposed PFC controller can be designed by
Lb =
Vac,p eak2 × (Vout− VAC ,p eak)× η
4× Pout× Vout× fs,m in
(11)
where Vac,p eakis the peak value of the input ac voltage, Poutis the output power, and η is the conversion efficiency.
Fig. 22. Zoom-in waveforms of the conventional PFC controller when the output load step changes from 90 to 20 W in (a) and vice versa in (b). B. Design of Primary Winding
The peak inductor current IL ,p eak may affect the primary
winding design. Thus, according to Faraday’s law, the turns of primary winding can be obtained by
Nb = Lb× IL ,p eak Bm ax× Ae where IL ,p eak = 2 √ 2 Pout VAC ,rm s× η (12) where Ae is the effective area of the core section and Bm ax is
the saturation magnetic flux density.
C. Design of Auxiliary Winding
The ZCD needs to sense the voltage information of the aux-iliary winding. When Zd is lower than the threshold voltage in
the ZCD circuit, the signal PWM is set high again to initiate a new switching cycle. Nevertheless, there is a prerequisite. Zd
must exceed VR EFto ensure the ZCD function when the power MOSFET is turned OFF. Therefore, the turns of auxiliary wind-ing can be design by
Naux= Ksafe× VR EF Vout− √ 2VAC ,rm s(m ax) × Nb (13)
where Ksafe is a constant to ensure that the system contains a safe operation margin.
D. Design of Output Capacitor
The output capacitor Cout is used to guarantee the output voltage well-regulated voltage for the next stage. Cout is de-termined by the requirement of sufficient hold-up time thold,
TABLE II DESIGNSPECIFICATIONS
which is the measured time from the general output voltage to the minimum operating voltage of following stage. The output capacitor can be derived as
Cout= 2× Pout× thold (V2 out− Vout,m in2 ) . (14) V. EXPERIMENTRESULTS
The PFC controller with the TLM control technique was fabricated in the VIS 0.5 μm 500 V laterally diffused metal– oxide–semiconductor transistor (LDMOS) process. The chip micrograph and the prototype are shown in Fig. 18(a) and (b), respectively. The design specifications are shown in Table II. The operating voltages of the controller and the driver are 5 and 20 V, respectively. The off-chip input transformer and the output
Fig. 23. Zoom-in waveforms of the proposed PFC controller with the TLM technique when the output load step changes from 90 to 20 W in (a) and vice versa in (b).
Fig. 24. Measured efficiency results at Va c= 110 V and Va c= 220 V.
cap are 400 μH and 68 μF, respectively. Output voltage of the PFC controller is 400 V for the next-stage PWM converter.
Input ac voltage is 90 Vac. Experimental results of conven-tional design show that load power consumption changes from 20 to 90 W [see Fig. 19(a)] or vice versa [see Fig. 19(b)]. Over-shoot and underOver-shoot voltages are 42 and 40 V, respectively. Recovery times are 320 and 170 ms when load current changes from heavy to light and vice versa. Bandwidth is limited by the large compensation capacitor, so that low-bandwidth transient response of conventional design cannot be sped up.
Fig. 20 illustrates the experimental waveforms of the pro-posed PFC controller with the TLM. Overshoot and undershoot voltages are kept smaller than 24 V. Recovery times are 150 and 130 ms when load changes from heavy to light and vice versa. Transient response in the proposed PFC controller with the TLM is twofold faster than that of conventional design when output power is changed from heavy to light or vice versa. The improved overshoot and undershoot voltages can effectively en-hance the reliability of the power system. Fig. 21(a) and (b) shows the measurement results in the steady state when the load changes from 20 to 90 W and vice versa, respectively. Further-more, Figs. 22 and 23 show the zoom-in transient waveforms without and with the TLM technique, respectively.
Fig. 24 shows the measured efficiency with the proposed TLM at Vac= 110 V and Vac= 220 V. The output power varies from 10 to 90 W. As the input voltage is equal to 220 V, the input current is smaller than that with the input voltage of 110 V. Thus, the conduction loss can be decreased so that the efficiency can
Fig. 25. Spectrum of the input current.
be increased effectively. The efficiency still can be kept larger than 93% at output power of 10 W without being affected by the power consumption of the TLM since the TLM only consumes 2.65 mW. Besides, Fig. 25 illustrates the spectrum of the input current, which fits the requirements of EN61000-3-2 Class D. The comparison with the prior arts is shown in Table III. The TLM technique can have fast transient response and low under-shoot/overshoot voltage. Simultaneously, high PF and low THD also are guaranteed because the TLM only works during the du-ration of load variation. Furthermore, the operating frequency needs to be larger than 35 kHz to avoid audio noise. Based on the EMI filter, the upper limit of the operating frequency is around 217 kHz at 220 Vac. Moreover, the input ac current Iac as shown in Fig. 26 is shaped to be a sinusoidal waveform and in-phase with the input ac voltage Vac. Thus, PF is improved by the proposed PFC controller.
Fig. 26. Measured waveforms of the output voltage and the input ac current at the input ac voltage of 90 V.
VI. CONCLUSION
The PFC controller with the TLM technique can ensure high reliability and high efficiency of 95% at output power of 90 W. In addition, the PFC controller has low THD of 10% and high PF of 0.99 when the TLM technique is adopted. Furthermore, the proposed TLM can effectively clamp overshoot and undershoot voltages to be less than 24 V. The test circuit fabricated in the VIS 500 V UHV LDMOS process demonstrates the performance of the highly integrated PFC controller.
ACKNOWLEDGMENT
The authors would like to thank Energy Pass Inc., for their help.
REFERENCES
[1] R. W. Erickson and D. Maksimovic, Fundamentals of Power Electronics, 2nd ed. Norwell, MA: Kluwer, 2001.
[2] A. Fernandez, J. Sebastian, M. M. Hernando, P. Villegas, and J. Garcia, “Helpful hints to select a power-factor-correction solution for low-and
medium-power single-phase power supply,” IEEE Trans. Ind. Electron., vol. 52, no. 1, pp. 46–55, Feb. 2005.
[3] K. H. Liu and Y. L. Lin, “Current waveform distortion in power factor correction circuits employing discontinuous-mode boost converters,” in
Proc. IEEE Power Electron. Spec. Conf., Jun. 1989, pp. 825–829.
[4] J. Zhang, J. Shao, F. C. Lee, and M. M. Jovanovi´c, “Evaluation of input current in the critical mode boost PFC converter for distributed power systems,” in Proc. IEEE Appl. Power Electron. Conf., Feb. 2001, pp. 130– 136.
[5] H. Wei and I. Batarseh, “Comparison of basic converter topologies for power factor correction,” in Proc. IEEE Int. Conf. Southeastcon, Apr. 1998, pp. 348–353.
[6] J.-S. Lai and D. Chen, “Design consideration for power factor correction boost converter operating at the boundary of continuous conduction mode and discontinuous conduction mode,” in Proc. IEEE Appl. Power Electron.
Conf., Mar. 1993, pp. 267–273.
[7] J. Sebastian, J. A. Cobos, J. M. Lopera, and J. Uceda, “The determination of the boundaries between continuous and discontinuous modes in PWM DC-to-DC converters used as power factor pre regulators,” IEEE Trans.
Power Electron., vol. 10, no. 5, pp. 574–582, Sep. 1995.
[8] A. Abramovitz, “Effect of the ripple current on power factor of CRM boost APFC,” in Proc. CES/IEEE Int. Power Electron. Motion Control
Conf., Aug. 2006, pp. 1412–1415.
[9] M.-H.-L. Chow, K. W. Siu, C. K. Tse, and Y.-S. Lee, “A novel method for elimination of line-current harmonics in single-stage PFC switching regulators,” IEEE Trans. Power Electron., vol. 13, no. 1, pp. 75–83, Jan. 1998.
[10] K. De Gusseme, D. M. Van de Sype, A. P. M. Van Den Bossche, and J. A. Melkebeek, “Input-current distortion of CCM boost PFC converters operated in DCM,” IEEE Trans. Ind. Electron., vol. 54, no. 2, pp. 858–865, Apr. 2007.
[11] M. Gotfryd, “Limits in boost power factor corrector operating in border-line mode,” IEEE Trans. Power Electron., vol. 18, no. 6, pp. 1330–1335, Nov. 2003.
[12] B. Akın and H. Bodur, “A new single-phase soft-switching power fac-tor correction converter,” IEEE Trans. Power Electron., vol. 26, no. 2, pp. 436–443, Feb. 2011.
[13] J. W. Kim, S. M. Choi, and K. T. Kim, “Variable on-time control of the critical conduction mode boost power factor correction converter to im-prove zero-crossing distortion,” in Proc. Power Electron. Drives Syst., Nov. 2005, vol. 2, pp. 1542–1546.
[14] K. Yao, X. Ruan, X. Mao, and Z. Ye, “Variable-duty-cycle control to achieve high input power factor for DCM boost PFC converter,” IEEE
Trans. Ind. Electron., vol. 58, no. 5, pp. 1856–1865, May 2011.
[15] J.-S. Lai and D. Chen, “Design consideration for power factor correction boost converter operating at the boundary of continuous conduction mode and discontinuous conduction mode,” in Proc. IEEE Appl. Power Electron.
[16] L. Huber, B. T. Irving, and M. M. Jovanovic, “Effect of valley switch-ing and switchswitch-ing-frequency limitation on line-current distortions of DCM/CCM boundary boost PFC converters,” IEEE Trans. Power
Elec-tron., vol. 24, no. 2, pp. 339–347, Feb. 2009.
[17] D. S. L. Simonetti, J. L. F. Viera, and G. C. D. Sousa, “Modeling of the high-power-factor discontinuous boost rectifiers,” IEEE Trans. Ind.
Elec-tron., vol. 46, no. 4, pp. 788–795, Aug. 1999.
[18] M.-H. Chan, Y.-T. Lin, and Y.-Y. Tzou, “Development of a mixed-signal PFC control IC with fast dynamic response,” in Proc. IEEE Int. Power
Electron. Motion Control Conf., May 2009, pp. 1708–1712.
[19] L. Huber, B. T. Irving, and M. M. Jovanovic, “Simple controller for single-phase power factor correction rectifier,” IET Power Electron., vol. 3, no. 4, pp. 590–600, Jul. 2010.
[20] M. A. Ebrahimzadeh and A. R. Rahmati, “Adaptive and fast-response con-troller for Boost PFC converter with wide range of operating conditions,” in Proc. Power Electron. Drive Syst. Technol. Conf., Feb. 2010, pp. 157– 162.
Jen-Chieh Tsai received the B.S. degree from the Department of Electrical Engineering, National Yunlin University of Science and Technology, Yunlin, Taiwan, in 2003, and the M.S. degree from the De-partment of Electrical Engineering, Tamkang Univer-sity, Taipei, Taiwan, in 2005. He is currently working toward the Ph.D. degree at the Institute of Electrical Control Engineering, National Chiao Tung Univer-sity, Hsinchu, Taiwan.
He is a Faculty Member in the Mixed-Signal and Power Management IC Laboratory, Institute of Elec-trical Control Engineering, National Chiao Tung University, where his research area contains many projects on high-resolution ADC, low-power DAC, and power management ICs. His research interests include power management cir-cuit designs, power factor correction ICs, and analog IC designs.
Chia-Lung Ni was born in Keelung, Taiwan. He re-ceived the B.S. degree from the Department of Elec-trical Engineering, National Chung Hsing University, Taichung, Taiwan. He is currently working toward the M.S. degree at the Institute of Electrical and Con-trol Engineering, National Chiao Tung University, Hsinchu, Taiwan.
He is a Faculty Member in the Mixed-Signal and Power Management IC Laboratory, Institute of Elec-trical Control Engineering, National Chiao Tung Uni-versity. His research interests include power factor correction IC design, power management IC design, and analog ICs.
Chi-Lin Chen received the B.S. degree from the De-partment of Electrical Engineering, Yuan Ze Uni-versity, Taoyuan, Taiwan, in 1995, and the M.S. de-gree from the Department of Electrical Engineering, National Central University, Taoyuan, in 1998. He is currently working toward the Ph.D. degree at the Institute of Electrical Control Engineering, National Chiao Tung University, Hsinchu, Taiwan.
He is a Faculty Member in the Mixed-Signal and Power Management IC Laboratory, Institute of Elec-trical Control Engineering, National Chiao Tung Uni-versity. His interests include switching power circuit, mixed-signal circuit de-signs, and analog IC designs.
Yi-Ting Chen was born in Taipei, Taiwan. She re-ceived the B.S. degree from the Department of Elec-trical Engineering, Chang Gung University, Taoyuan, Taiwan. She is currently working toward the M.S. degree at the Institute of Electrical and Control En-gineering, National Chiao Tung University, Hsinchu, Taiwan.
She is a Faculty Member in the Mixed-Signal and Power Management IC Laboratory, Institute of Electrical Control Engineering, National Chiao Tung University. Her research interests include power fac-tor correction IC design, power management IC design, and analog ICs.
Chun-Yen Chen was born in Keelung, Taiwan. He received the B.S. degree from the Electrical Engi-neering and Computer Science Undergraduate Hon-ors Program, National Taipei University of Technol-ogy, Taipei, Taiwan. He is currently working toward the M.S. degree at the Institute of Electrical and Con-trol Engineering, National Chiao Tung University, Hsinchu, Taiwan.
He is a Faculty Member in the Mixed-Signal and Power Management IC Laboratory, Institute of Elec-trical Control Engineering, National Chiao Tung Uni-versity. His research interests include power factor correction IC design, power management IC design, and analog ICs.
Ke-Horng Chen (M’04–SM’09) received the B.S., M.S., and Ph.D. degrees in electrical engineering from National Taiwan University, Taipei, Taiwan, in 1994, 1996, and 2003, respectively.
From 1996 to 1998, he was a part-time IC Designer at Philips, Taipei. From 1998 to 2000, he was an Ap-plication Engineer at Avanti, Ltd., Taipei. From 2000 to 2003, he was a Project Manager at ACARD, Ltd., where he was involved in the design of power man-agement ICs. He is currently a Professor in the De-partment of Electrical Engineering, National Chiao Tung University, Hsinchu, Taiwan, where he organized a Mixed-Signal and Power Management IC Laboratory. He is the author or coauthor of more than 100 papers published in journals and conferences, and also holds several patents. His current research interests include power management ICs, mixed-signal cir-cuit designs, display algorithm and driver designs of liquid crystal display TV, and RGB color sequential backlight designs.
Dr. Chen was an Associate Editor of the IEEE TRANSACTIONS ONPOWER
ELECTRONICSand the IEEE TRANSACTIONS ONCIRCUITS ANDSYSTEMS—PART
II: EXPRESSBRIEFS. He is currently serving on the IEEE Circuits and Systems (CAS) VLSI Systems and Applications Technical Committee, and the IEEE CAS Power and Energy Circuits and Systems Technical Committee.
