350 IEEE ELECTRON DEVICE LETTERS, VOL. 21, NO. 7, JULY 2000
High Temperature Formed SiGe P-MOSFET’s with
Good Device Characteristics
Y. H. Wu and Albert Chin, Senior Member, IEEE
Abstract—We have used a simple process to fabricate
Si0 3Ge0 7/Si p-MOSFET’s. The Si0 3Ge0 7 is formed using deposited Ge followed by 950 C rapid thermal annealing and solid phase epitaxy that is process compatible with existing VLSI. Hole mobility of 250 cm2/Vs is obtained from Si0 3Ge0 7 p-MOSFET that is two times higher than Si control devices and results in a consequent substantially higher current drive. The 228Å Si0 3Ge0 7thermal oxide grown at 1000 C has a high breakdown field of 15 MV/cm, low interface trap density ( ) of1 5 1011eV 1cm 2, and low oxide charge of7 2 1010 cm 2. The source-drain junction leakage after implantation and 950 C RTA is also comparable with Si counterpart.
Index Terms—Hole mobility, P-MOSFET, reliability, SiGe.
I. INTRODUCTION
S
iGe p-MOSFET’s have attracted much attention [1]–[10] because of the improved mobility and current drive capa-bility. However, one difficult technology barrier to integrate SiGe into CMOS process is the required low temperature ( 800 C) to avoid strain relaxation and defect generation. This is because rough surface and pinholes may form during strain relaxation that degrades the device performance [8]–[10]. Unfortunately, the limited low temperature processing may also degrade both gate oxide integrity and source-drain junc-tions [11], and high dopant activation and low p n junction leakage after source-drain implantation can only be obtained at a reasonable high annealing temperature. Furthermore, the required low temperature processing for SiGe p-MOSFET is not compatible to current Si n-MOSFET technology and modern high-K gate dielectrics [12], [13]. In this letter, we provide a simple approach to fabricate SiGe/Si p-MOSFET with good device characteristics that is fully compatible to the existing ULSI technology without the constraint of low temperature processing. Further, selectively formed SiGe can be easily achieved only in p-MOSFET without alternating the performance of Si n-MOSFET.II. EXPERIMENTAL
Standard 4-in (100) Si wafers with concentrations of cm were used in this study. In addition to SiGe p-MOSFET’s, Si control devices were also fabricated as references. After device isolation, amorphous Ge layer
Manuscript received November 9, 1999. This work was supported by the Na-tional Science Council of Taiwan under Contract 88-2215-E-009-032. The re-view of this letter was arranged by Editor E. Sangiorgi.
The authors are with the Department of Electronics Engineering, National Chiao Tung University, Hsinchu, Taiwan, R.O.C. (e-mail: u8511553@cc.nctu.edu.tw).
Publisher Item Identifier S 0741-3106(00)05449-5.
Fig. 1. Room-temperatureI –V characteristics of 3-m Si Ge and standard Si p-MOSFET’s.
is selectively deposited. An HF-vapor passivation is used to suppress the native oxide formation before Ge deposition [12], [14]–[15]. A 50-nm thick Si Ge was then formed in the active region by rapid thermal annealing (RTA) at 950 C, as measured by TEM and SIMS. X-ray diffraction (XRD) was used to determine the Ge composition and a sharp peak comparable to Si substrate was measured that indicates good crystalline quality of Si Ge . More detailed material characterization can be found in our previous study [16]. Gate oxide was then grown by dry O at 1000 C to a thickness of 228 Å and 212 Å on Si Ge and Si, respectively. The oxide thickness was carefully measured by ellipsometer and TEM, and the near identical thickness of Si and Si Ge oxides is due to the same oxidation rate by dry O [1]. After a 3000 Å poly-Si deposition and patterning, source, drain, and gate were implanted by B at 15 KeV with a dose of cm and subsequently annealed at 950 . Besides MOSFET’s, source-drain p -n diodes and MOS capacitors were also fabricated on the same wafer to characterize the junction leakage and gate oxide quality.
III. RESULTS ANDDISCUSSION
Fig. 1 shows the room-temperature output characteristics of 3- m Si Ge and standard Si p-MOSFET’s. To eliminate the effect of threshold voltage ( ) difference in both devices, we have plotted – instead of as a function of current. As shown in Fig. 1, Si Ge p-MOSFET possesses substantially higher current output than that of conventional Si device.
To further study this current drive improvement, we have plotted the – curve and room-temperature effective mo-bility ( ) in Fig. 2 for wide channel MOSFET’s. In addition to the higher saturation currents, the Si Ge MOSFET’s
WU AND CHIN: SiGe p-MOSFET’s WITH GOOD DEVICE CHARACTERISTICS 351
Fig. 2. Room-temperature effective mobility for Si Ge and Si p-MOSFET’s derived from the insertI –V curves.
Fig. 3. Gate oxide breakdown field distribution for thermal oxide grown on Si Ge and Si. The interface trap density is also shown in the inset figure.
maintain the same subthreshold swing as Si counterpart. The Si Ge -channel devices has a peak hole mobility of 250 cm /Vs that is two times higher than Si control sample [17]. Because of the near identical measured capacitance for Si and Si Ge , the improved current drive capability is due to the higher hole mobility in Si Ge MOSFET’s rather than a higher-K [12]. In contrast to previous low temperature processed and strained p-MOSFET’s [1]–[9], the achieved good Si Ge mobility and device performance may be due to the high temperature formed and strain-relaxed Si Ge that results in a more stable material during thermal cycle [11],[18]–[19]. This is confirmed by the very sharp XRD linewidth after oxidation and post implantation RTA with near identical peak position and linewidth to as formed Si Ge . The higher mobility may be due to the smaller effective mass of Ge than Si even without strain [20]–[21].
We have also characterized the gate oxide integrity of high temperature formed Si Ge p-MOSFET’s. Fig. 3 shows the breakdown field distribution and the interface trap density of Si Ge gate oxide. The high breakdown electrical field of 15 MV/cm, low interface trap density ( ) of eV cm , and low oxide charge of cm indicate excel-lent oxide integrity can be achieved on high temperature formed Si Ge . The slightly higher in Si Ge may be due to Ge pile-up at oxide–SiGe interface, but it is still one order of magnitude lower than previous works [1] and has limited
ef-Fig. 4. Source-drain p n junction leakage distribution of Si Ge and Si measured at 3.3 V reverse bias.
fect on mobility. The reason why this work enjoys much im-proved hole mobility could be attributed to extremely flat inter-face which is evidenced by TEM observation.
Source-drain junction leakage is another important param-eter for practical process integration. We have also measured the junction leakage and is shown in Fig. 4. Although the junc-tion leakage of Si Ge is comparable with Si, the slightly higher value may be due to either lower bandgap or dislocation formation in Si Ge . This low junction leakage can be also explained by the high RTA annealing temperature for dopant activation and defect annihilation on high temperature formed Si Ge .
IV. CONCLUSION
We have demonstrated a simple method to fabricated SiGe p-MOSFET with good mobility, gate oxide integrity and junc-tion leakage. Furthermore, this method is fully compatible to the existing VLSI technology. The good device performance is related to the high forming temperature of SiGe.
ACKNOWLEDGMENT
The authors would like to thank Prof. K. C. Hsieh, Depart-ment of Electrical Engineering, University of Illinois.
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