This content has been downloaded from IOPscience. Please scroll down to see the full text.
Download details:
IP Address: 140.113.38.11
This content was downloaded on 28/04/2014 at 02:38
Please note that terms and conditions apply.
Improved Annealing Process for Electroless Pd Plating Induced Crystallization of Amorphous
Silicon
View the table of contents for this issue, or go to the journal homepage for more 2003 Jpn. J. Appl. Phys. 42 L895
(http://iopscience.iop.org/1347-4065/42/8A/L895)
Improved Annealing Process for Electroless Pd Plating Induced Crystallization
of Amorphous Silicon
Guo-Ren HU, Tian Jiun HUANGand YewChung Sermon WU
Department of Materials Science and Engineering, National Chiao Tung University, Hsinchu 300, Taiwan, R.O.C. (Received March 27, 2003; revised manuscript received April 25, 2003; accepted for publication June 2, 2003)
Electroless Pd plating induced crystallization of amorphous silicon (a-Si) thin films has been proposed for fabricating low-temperature polycrystalline silicon thin film transistors (LTPS TFTs). However, the current crystallization process often leads to poor device performance due to the large amount of Pd-silicide residues in the poly-Si thin films. It was found that the amount of Pd silicide increased with annealing time and temperature. In this study, a two-step annealing process was developed to obtain the appropriate amount of Pd silicide for inducing the crystallization of a-Si. The device characteristics were significantly improved by this two-step process. [DOI: 10.1143/JJAP.42.L895]
KEYWORDS: thin-film transistor, amorphous silicon, polycrystalline silicon, metal-induced crystallization, electroless plating and physical vapor deposition
Low-temperature polycrystalline silicon thin film transis-tors have attracted considerable attention for active matrix liquid crystal display (AMLCD) application due to their good electrical properties and capability of integrating peripheral circuits into inexpensive glass substrates.1,2) Since poly-Si thin film transistors (poly-Si TFTs) should be fabricated on glass substrates to reduce the fabrication cost, intensive studies have been carried out to reduce the fabrication temperature of polycrystalline silicon (poly-Si) thin films. Metal-induced crystallization (MIC) of a-Si has been one of these efforts. In MIC, a metal thin film (Ni,3–6) Pd7)or Al8)) is deposited on top of an as-deposited a-Si film and this is followed by crystallization at a temperature lower than 600C. Nevertheless, metal films are generally
depos-ited by the physical vapor deposition (PVD) method, which is still very time-consuming and expensive in terms of equipment cost.
To reduce the process time and cost, in previous studies, we proposed an electroless Pd plating method to induce crystallization of a-Si thin films.9,10) After sample was annealed at 530 and 550C, two kinds of needlelike grains were found. The direction of the primary grain was along h211i and the growth of the secondary grain occurred along the h011i direction, which was normal to the primary grain growth direction. However, the leakage current increased significantly due to the Pd-silicide residues in the channel of the poly-Si TFTs. In this study, a two-step annealing process was used to reduce Pd-silicide contamination and thus improve the TFT performance.
Si wafers were used in this study. After a wet oxide layer was grown, silane-based a-Si films of 100 nm thickness were deposited by a low-pressure chemical vapor deposition (LPCVD) system. The wafers were cleaned in a diluted HF solution, and then immediately dipped into a plating solution of PdCl2 (1 g/‘) and HCl (100 ml/‘) for 10 min.9) The
following two methods were employed to induce the crystallization of a-Si films.
(a) conventional furnace annealing (CFA): Samples were annealed in nitrogen atmosphere at 550C for 18 h to
crystallize the Si films. After annealing, the unreacted Pd clusters were removed by chemical etching.
(b) Two-step annealing: Samples were preannealed to
form the appropriate amount of Pd silicide. The unreacted Pd clusters were removed by chemical etching, then the samples were annealed in nitrogen atmosphere at 550C for 18 h.
A post rapid thermal annealing (RTA) treatment at 850C for 75 s was used to improve the crystallinity and uniformity of both Si films. The TFT devices were then fabricated by defining the active areas on the poly-Si films. A 100-nm-thick SiO2 film for gate oxide was deposited by
plasma-enhanced chemical vapor deposition (PECVD). Subsequent-ly, a 200-nm-thick SiH4-based a-Si film was deposited at
550C by the LPCVD system and lithographically patterned
as the gates. The gate electrode and source/drain were doped by self-aligned phosphorus implantation at a dose of 5 1015ions/cm2. Then dopant activation and crystallization of
a-Si gate electrodes were performed at 850C for 30 min in
N2 atmosphere. After the 200-nm-thick
tetraethylorthosili-cate (TEOS) oxide deposition, contact holes were formed for gate, source and drain electrodes. Electrode pads were formed after the Al film deposition. Sintering was performed at 400C for 30 min. Then the 4 h NH3plasma treatment was
adopted to passivate the devices.
Figure 1(a) shows the typical characteristics of CFA-TFT devices. Their performance was very poor. Scanning electron microscopy (SEM) was used to study their poor performance of CFA poly-Si. Figure 2 shows the SEM images of Secco-etched CFA poly-Si annealed at 550C for
18 h. There were two kinds of needlelike grains on the Si films as shown in Fig. 2(a). The direction of the primary grain was along h211i and the growth of the secondary grain occurred along the h011i direction, which was normal to the primary grain direction.9,10)Nevertheless, not all of the a-Si film was transformed to c-Si. As shown in Fig. 2(a), between neighboring needlelike Si grains, there still remained some gaps, which were uncrystallized a-Si regions that had been etched away by Secco solution. However, in addition to these a-Si regions, there were numerous holes on the CFA poly-Si film as shown in Fig. 2(b). The high-resolution micrograph of these holes in Fig. 2(c) shows some Pd clusters around the holes. Therefore, we believe that the holes in Fig. 2(b) were Pd silicide that had been etched away by Secco solution.
To improve the device performance, Pd-silicide contam-ination must be reduced since it traps charge carriers and builds up potential barriers to the flow of the carriers.
Corresponding author. E-mail address: [email protected]
Jpn. J. Appl. Phys. Vol. 42 (2003) pp.L 895–L 897 Part 2, No. 8A, 1 August 2003
#2003 The Japan Society of Applied Physics
Furthermore, the presence of these potential barriers and additional scattering at the boundaries degrade the TFT performance.
The studies of the CFA Si surface morphologies and device characteristics described above clearly showed that Pd could lead to the formation of poly-Si at lower temper-ature, but it also caused the formation of Pd silicide, which degraded the device characteristics. For this reason, a two-step annealing process was developed to obtain the appro-priate amount of Pd silicide to induce the crystallization of a-Si.
In the two-step annealing process, two annealing steps were carried out after the electroless Pd plating. The first annealing step was performed in nitrogen atmosphere to form silicides either in a RTA furnace (pre-RTA) or a CFA furnace (pre-CFA). Then, the unreacted Pd clusters were removed by chemical etching. The second annealing step was carried out in a conventional furnace at 550C for 18 h
to crystallize a-Si.
The pre-RTA process was used as the first annealing step because it can control the annealing time precisely. It was performed at 400–700C for 15 s. After the second CFA
annealing step, SEM was used to examine the surface of the Secco-etched poly-Si films. As shown in Figs. 3(a)–3(c), the number and area of the silicide holes decreased with decreasing pre-RTA temperature, which is consistent with the observation that the formation of Pd silicide decreases with decreasing temperature. However, even with the lowest pre-RTA temperature (400C), there was still a high amount
of Pd silicide. Thus, the device characteristics were still poor.
To reduce the annealing temperature, a CFA furnace was used for the first annealing step because the lowest operating temperature of our RTA furnace is 400C. Samples were annealed at 200C for 30 min. After the second CFA annealing step, the surface of the Secco-etched poly-Si films was examined by SEM. As shown in Fig. 3(d), silicide holes were difficult to find on the Si surface. The poly-Si grains were still needlelike, such as those shown in Fig. 2(a), but with a lower number of silicide holes. Therefore, 200C pre-CFA was selected as the first annealing step for
the two-step annealing process.
The device characteristics of two-step annealing poly-Si films are shown in Fig. 1(b). Compared with CFA poly-Si
1x10-6 1x10-7 1x10-8 1x10-9 1x10-10 1x10-11 1x10-12 Dr ain Current(A) -10 -5 0 5 10 15 20 Gate Voltage(V) Vd =5V Vd =0.1V CFA-TFT 1x10-5 1x10-6 1x10-7 1x10-8 1x10-9 1x10-10 1x10-11 1x10-12 Dr ain Current(A) -10 -5 0 5 10 15 20 Gate Voltage(V) Vd =5V Vd =0.1V Two-step TFT (a) (b)
Fig. 1. The IdVgcharacteristics of (a) CFA poly-Si TFTs and (b)
two-step poly-Si TFTs. 600nm silicide hole 500nm silicide hole Pd cluster (a) (b) (c)
Fig. 2. SEM images of Secco-etched CFA poly-Si annealed at 550C for
18 h. (a) the image of two kinds of needlelike grains. The direction of the primary grain was along h211i and the growth of the secondary grain occurred along the h011i direction. (b) the holes on the CFA poly-Si films. (c) the high-resolution micrograph of the holes showing Pd clusters around the holes.
TFTs (Fig. 1(a)), the performance of two-step poly-Si TFTs was significantly improved. The two-step TFTs had a higher mobility (12.88 cm2/Vs), a smaller subthreshold slope
(1.95 V/dec) and a smaller leakage current/channel width (6.10 pA/mm).
After investigating the relationship between annealing conditions (temperature and time) and the amount of Pd silicide in poly-Si films, this study has led to the develop-ment of an effective process for preparing poly-Si films. It was found that poor device performance caused by Pd-silicide residues could be minimized by a two-step annealing process. In the two-step annealing process, two annealing steps were carried out after electroless Pd plating. The first annealing step was performed in nitrogen atmosphere to form the appropriate amount of Pd silicide at 200C for
30 min. After unreacted Pd clusters were removed by chemical etching, the second annealing step was carried out in a conventional furnace at 550C for 18 h to crystallize
a-Si. Then, a post-RTA treatment was used to improve the crystallinity and uniformity of Si films at 850C for 75 s.
This research was supported in part by the National Science Council (NSC) of the Republic of China under grant no. NSC 91-2216-E009-026. Technical support from the National Nano Device Laboratory of NSC and the Semi-conductor Research Center of National Chiao Tung Uni-versity is also acknowledged.
1) T. Serikawa, S. Shirai, A. Okamoto and S. Suyama: IEEE Trans. Electron Devices 36 (1989) 1929.
2) J.-I. Ohwada, M. Takabatake, Y. A. Ono, A. Mimura, K. Ono and N. Konisji: IEEE Trans. Electron Devices 36 (1989) 1923.
3) T. Aoyama, G. Kawachi, N. Konishi, T. Suzuki, Y. Okajima and K. Miyata: J. Electrochem. Soc. 136 (1989) 1169.
4) Z. Jin, G. A. Bhat, M. Yeung, H. S. Kwok and M. Wong: J. Appl. Phys. 84 (1998) 194.
5) T. Hempel and O. Schoefeld: Solid State Commun. 85 (1993) 921. 6) S. K. Lee, T. H. Ihn and S. K. Joo: IEEE Electron Device Lett. 17
(1996) 407.
7) S. W. Lee, B. Lee, T. K. Kim and S. K. Joo: J. Appl. Phys. 85 (1999) 7180.
8) S. F. Gong, H. T. G. Hentzell, A. E. Robertsson, L. Hultman, S. E. Hornstrom and G. Radnoczi: J. Appl. Phys. 62 (1987) 3726. 9) C. W. Chao, G. R. Hu, Y. S. Wu, Y. C. Chen and M.-S. Feng:
Electrochem. Solid-State Lett. 5 (2002) C31-2.
10) G. R. Hu, Y. S. Wu, C. W. Chao and T. J. Huang: Jpn. J. Appl. Phys. 41(2002) 6356. silicide hole silicide hole (a) (b) (c) (d)
Fig. 3. SEM images of Secco-etched poly-Si annealed at 550C for 18 h
with various preannealing temperatures and times: (a) pre-RTA 400C for
15 s, (b) pre-RTA 500C for 15 s, (c) pre-RTA 600C for 15 s and (d)
pre-CFA 200C for 30 min.
