12 IEEE ELECTRON DEVICE LETTERS, VOL. 35, NO. 1, JANUARY 2014
Body-Tied Germanium Tri-Gate Junctionless
PMOSFET With In-Situ Boron Doped Channel
Che-Wei Chen, Cheng-Ting Chung, Ju-Yuan Tzeng, Pang-Sheng Chang,
Guang-Li Luo, and Chao-Hsin Chien
Abstract— In this letter, we demonstrate body-tied Ge tri-gate
junctionless (JL) p-channel MOSFETs directly on Si. Our tri-gate JL-PFET exhibits higher current than the conventional inversion-mode transistor through in-situ heavily doped technique and trimming down Ge fin width. We show that the JL-PFET with tri-gate structure has excellent ION/IOFF ratio and good short channel effect control on the channel potential. The current ratio is of ∼6 × 103(ID) at VDS= −0.1 V, VGS= −3, and 0 V. The
relatively low OFF-current is of 6 nA/ µm at VDS = −0.1 V
and VGS = 0 V. The subthreshold swing of 203 mV/decade and
drain induced barrier lowering of 220 mV/V are reported at
LG= 120 nm.
Index Terms— Junctionless, tri-gate, germanium, body-tied,
in-situ heavily doped.
I. INTRODUCTION
G
ERMANIUM has been reported to be one of the candi-dates for replacing Si to continuously enhance the circuit performance [1]. A higher permittivity of Ge than that of Si leads to more severe SCE. To meet the pressing requirement of the channel potential control, non-planar structures have been suggested to the fabrication of Ge MOSFETs. Germa-nium FinFETs have been fabricated successfully on the Si substrate [2]–[3]. However, the degradation in current ratio for the short channel devices was observed. Junctionless device possesses the same doping type of channel and S/D, which is essentially an accumulation-mode device. It is like a resistor and the amount of mobile majority carriers can be modulated by the bias on the gate electrode. The ON state current comes from the majority carrier conduction already existing in the channel; while the OFF state is achieved by depleting the majority carriers through the work function difference between the gate electrode and semiconductor. Recently, theManuscript received October 21, 2013; revised November 4, 2013; accepted November 6, 2013. Date of current version December 20, 2013. This work was supported in part by the National Science Council of Taiwan under Grant NSC 101-2628-E-009-011-MY3 and in part by the NCTU-UCB I-RiCE Program under Grant NSC-102-2911-I-009-302. The review of this letter was arranged by Editor M. Östling. (Corresponding author: G.-L. Luo and C.-H. Chien.)
C.-W. Chen, C.-T. Chung, J.-Y. Tzeng, and P.-S. Chang are with the Department of Electronics Engineering and the Institute of Electronics, National Chiao Tung University, Hsinchu 30010, Taiwan.
G.-L. Luo is with the National Nano Device Laboratories, Hsinchu 30078, Taiwan (e-mail: glluo@ndl.narl.org.tw).
C.-H. Chien is with the Department of Electronics Engineering and the Institute of Electronics, National Chiao Tung University, Hsinchu 30010, Taiwan, and also with National Nano Device Laboratories, Hsinchu 30078, Taiwan (e-mail: chchien@faculty.nctu.edu.tw).
Color versions of one or more of the figures in this letter are available online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/LED.2013.2291394
long channel planar Ge junctionless PMOSFET using double-gate structure on GeOI (Germanium on insulator) substrate has been reported [4]–[5]. Obviously, the driving current and subthreshold characteristics of their device were poor and needed to be further improved. In addition, the non-planar Ge junctionless nanowire transistors fabricated on GeOI wafers have been reported [6]–[7]. As known, the non-planar structure is very attractive from the viewpoint of gate control.
In this letter, we fabricate the Ge multi-fin junctionless PMOSFET with tri-gate structure integrated on the bulk Si platform. The device illustrates a low off current (IOFF) of 6
nA/μm at VGS = 0 V and VDS = −0.1 V. Furthermore, an
excellent ION/IOFF drain current ratio of ∼6×103 at VDS =
−0.1 V,VGS = −3 and 0 V. The good subthreshold
character-istics (S.S.= 203 mV/dec, DIBL = 220 mV/V) are obtained. II. DEVICEFABRICATION
An in-situ heavily boron doped Ge film via B2H6 source
was epitaxially grown on the bulk n (2∼7 ohm-cm)-Si(100) substrate using an rapid thermal chemical vapor deposition (RTCVD) system after a standard cleaning. Threading disloca-tion density was improved by the post Ge deposidisloca-tion annealing of 825 °C for 10 minutes in a high vacuum ambient. The multi-fin structure was formed by using reactive ion etching (RIE) after the pattern was defined by e-beam lithography. We performed a wet trimming process with a chemical solution of H2O2: H2O = 1 : 10 at room temperature for 45 s to
eliminate thin amorphized Ge residual layer without causing additional plasma damage and shrink down fin width to be 15∼20 nm. This is a key process for scaling down of device dimension. Spin on glass (SOG) as the device isolation was coated and etched back by the dilute buffered oxide etch (BOE). A GeO2 (at 520°C for 30s) surface passivation
using rapid thermal oxidation (RTO) and then a 5 nm ALD Al2O3 dielectric deposition were carried out. A metal gate Ti
(5 nm)/Pt (100 nm) was deposited by sputtering. NiGe contacts were accomplished by post metal annealing (PMA) at 200 °C for 1 min. Finally, forming gas annealing (FGA) at 300 °C 30 min was performed. In this way, the simple and Si process compatible body-tied Ge tri-gate JL MOSFET devices were fabricated.
III. RESULTS ANDDISCUSSION
Fig. 1(a) shows the schematic diagram of the structure of tri-gate Ge JL-PFET with ISHD channel. Majority carriers (holes) can be effectively depleted by the voltage on the multiple gates
CHEN et al.: BODY-TIED GERMANIUM TRI-GATE JL PMOSFET 13
Fig. 1. (a) Schematic diagram of tri-gate Ge junctionless p-channel MOSFET device on bulk Si. (b) Cross-sectional TEM image of p+-Ge film on n-Si using in-situ heavily doped epitaxy. The dislocation density is quite low. (c) XRD pattern of p+-Ge film on n-Si. (d) SIMS depth profile of boron dopant and the red line indicates the thickness of epi-Ge layer.
for achieving the off-state. Fig. 1(b) shows the cross-sectional TEM image of uniformly epitaxial p+-Ge (∼80 nm) film on the n-Si substrate. The dislocation density is estimated to be 5× 106∼107 cm−2 as measured on the thicker Ge sample. The single crystalline p+-Ge thin film was confirmed through XRD pattern (or rocking curve), as shown in Fig. 1(c). More-over, the ISHD technique can reduce the thermal budget and result in shallower dopant distribution as compared with the implantation process. Fig. 1(d) shows the secondary ion mass spectrometry (SIMS) profile of p+-Ge on n-Si using ISHD and boron concentration is observed to be ∼1× 1020cm−3.
More importantly, the significant suppression of boron doping tail and the resultant deep dopant distribution, observed in the conventional implantation scheme [8], is demonstrated. In other words, the ISHD prevails in the formation of shallow junction.
Fig. 2(a) shows the transfer characteristic of Ge multi-fin JL device with LG of 120 nm and the inset is the
output characteristic. The device shows a high ION/IOFF ratio of ∼6×103(ID) at VDS = −0.1 V,VGS = −3 and 0 V.
The S.S. is of 203 mV/dec and the DIBL of 220 mV/V. The total effective channel width WEff = 5 ×(2× HFin+
WFin) of multi-fin device is equal to ∼900 nm. Drain
cur-rent (IDS) and transconductance (gm) are normalized by the
effective total channel width. Recently, the reported current ratio was only a little bit more than 104 at V
DS = −50 mV
(LG = 230 nm) in a study of IM-PFET using the -gate
structure with NiGe metal source/drain on the GOI substrate [9]. The minimum off-state leakage current was∼1nA/μm at
VG= 1 V, which is obviously worse than ours (∼450 pA/μm
at VG = 0.5 V). A Ge IM p-channel FinFET using
aspect-ratio-trap scheme has been published last year [10], showing a ratio of∼ 104at VDS = −50 mV (LG = 110 nm). Another
IM device with strained Ge nanowire and metal S/D structure has been published last year [11], exhibiting a ratio of <103
Fig. 2. (a) Transfer characteristic of Ge JL-PFET with a LGof 120 nm and the ION/IOFFratio is∼ 6×103(ID) at VDS= −0.1 V,VGS = −3 and 0 V. ID
-VDSoutput characteristic (inset). (b) gmversus VGScharacteristics at VDS=
−0.1 V, VDS= −0.55 V, and VDS= −1 V. Fabrication process flow of Ge JL-PFET (inset).
(LG = 65 nm) and a parasitic resistance of ∼1.3 k×μm at
VDS = −50 mV. Moreover, for our Ge multi-fin IM-PFET
on the Si substrate, a poor current ratio of ∼ 2×103 has been reported based on the standard gate-last process [3]. The value of threshold voltage VT >0 needed to be adjusted
for the CMOS inverter application. Clearly, the present JL device depicts much higher current ratio and more appropriate
VTvalue (-0.6 V) than our former IM device [3]. The relatively
low off-state leakage current is attributed to the effectively depleted channel because the fins in the structure are suffi-ciently narrow. For the planar JL device [4]–[5], the stringent requirement of ultra thin channel brings out the difficulty of process control as well as the surface roughness issue. Theoretically [12], the fin width (WFin) should be smaller
than twice the depletion width (Wdep), that is WFin<2Wdep, to
effectively turn off the current at off-state in a tri-gate structure. In other words, the non-planar JL device with multiple gates is more suitable than the planar JL device; the resultant driving current of the non-planar JL device is supposed to be larger due to the larger effective channel width at the current level. The output characteristic exhibits a relatively high saturation current of 100 μA/μm at VGS-VT = −1 V and VDS =
−1 V. Our JL device shows much higher saturation current
than IM device [3]. The transconductance (gm) characteristics
are shown in Fig. 2(b) and process flow (inset); the peak value of gm at VDS = −1 V is much larger than that of the
IM device at VDS = −0.95 V in the early report [13] using
in-situ doped raised S/D technique on GOI substrate. We can see that the gm value increases significantly as the high drain
voltage increases, indicating a relatively low S/D resistance in our device. Fig. 3(a) shows the output characteristics of JL and IM devices with longer channel length (LG = 1 μm) in order
to compare the channel resistance between two devices, espe-cially in the linear region. The cross-sectional TEM image of Ge tri-gate PMOSFET device is shown in the inset of Fig. 3(a). It is clear that there is around two times in output current of JL device at VDS = −1 V and overdrive voltage equal to
−1 V. Total resistances RTotal of JL and IM device as a
function of gate voltage at VDS = −0.1 V are shown in
Fig. 3(b). The width of Ge single fin is around 18.4 nm, as shown in the inset of Fig. 3(b). The relationship between
14 IEEE ELECTRON DEVICE LETTERS, VOL. 35, NO. 1, JANUARY 2014
Fig. 3. (a) ID-VDSoutput characteristics of JL and IM devices with LG = 1
μm and cross-sectional TEM of Ge tri-gate PMOSFET (inset). JL shows better
output current is around two times higher than that IM. (b) Total resistance of JL and IM devices as a function of gate voltage, showing around 3.6 times reduction than IM. Inset is top-view SEM picture after wet trimming process (Ge fin width∼18.4 nm).
Fig. 4. Total resistance versus width before (left) and after (right) PMA for JL-PFET. Inset is I− V plot.
the S/D series resistance (RSD) and the RTotal is described
by [14] RT ot al= Rch+ RS D= LG We f fμe f fCO X(VG S− VT)+ R S D (1) where Rch is the channel resistance, Weff is the effective
channel width, μeff is the effective mobility, and COX is the
oxide capacitance. The RSDof JL device is around 870×μm
using ISHD technique, which is around 3.6 times reduction as compared to that of the IM device at VGS= −3 V. Moreover,
the RSDvalue of our JL device is around 2.8 times lower than
IM device in the work with in-situ boron doped S/D [13]. The transfer length method (TLM) was applied to extract the values of contact resistance (RC) and sheet resistance (Rsh).
The total resistances of Ni/p+-Ge are plotted versus contact width before PMA (left) and after PMA (right); the I -V curves are shown in the inset of Fig. 4. The contact resistance is of 33 with 30 % reduction and the sheet resistance is of 27 after PMA treatment. We think this reduction arises from the formation of NiGe. According to our experimental results, we suggest that the Ge non-planar JL-PFETs directly on the bulk
Si is very attractive from the viewpoint of process complexity and low cost for the future high performance circuits.
IV. CONCLUSION
Body-tied Ge multi-fin tri-gate JL-PFETs of LG down to
120 nm directly on the bulk Si substrate have been demon-strated. Trimming down the fin width to 15∼20 nm is sufficient to turn off the JL device which possesses excellent current ratio and good subthreshold characteristics. Our JL-PFETs show higher driving current than the IM-PFETs and depicts much better performance than the planar JL-PFET [4]. We think our work demonstrates the potential of easily fabricated non-planar Ge JL MOSFET on the Si substrate for the future high performance low power logic applications.
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