Li-Han Hsu, Student Member, IEEE, Wei-Cheng Wu, Edward Yi Chang, Senior Member, IEEE,
Herbert Zirath, Senior Member, IEEE, Yin-Chu Hu, Chin-Te Wang, Yun-Chi Wu, and Szu-Ping Tsai
Abstract—This study demonstrates a flip-chip interconnect with epoxy-based underfill ( = 3 5 and tan = 0 02 at 10 MHz) for packaging applications up to -band frequencies. To achieve the best interconnect performance, both the matching designs on GaAs chip and Al2O3 substrate were adopted with the underfill effects taken into consideration. The optimized flip-chip intercon-nect showed excellent performance from dc to 67 GHz with return loss below 20 dB and insertion loss less than 0.6 dB. Further-more, the dielectric loss induced by the underfill was extracted from measurement and compared with the simulation results. The reliability tests including 85 C 85% relative humidity test, thermal cycling test, and shear force test were performed. For the first time, the -parameters measurement was performed to check the flip-chip reliability, and no performance decay was observed after 1000 thermal cycles. Moreover, the mechanical strength was improved about 12 times after the underfill was applied. The results show that the proposed flip-chip architecture has excellent reliability and can be applied for commercial applications.
Index Terms—Design, epoxy resin, flip-chip, interconnect, mil-limeter wave (MMW), packaging, reliability, underfill, -band.
I. INTRODUCTION
I
N RECENT years, with the demands for wireless commu-nication systems increases rapidly, the operating frequency for the portable wireless is moving toward millimeter waves (MMWs). To meet the demands for commercial applications,Manuscript received May 14, 2009; revised January 09, 2010; accepted March 22, 2010. Date of publication July 08, 2010; date of current version August 13, 2010. This work was supported by the National Science Council of Taiwan and the Ministry of Economic Affairs, Taiwan under Contract NSC 96-2752-E-009-001-PAE and Contract 95-EC-17-A-05-S1-020.
L.-H. Hsu and W.-C. Wu are with the Department of Materials Science and Engineering, National Chiao Tung University, Hsinchu 300, Taiwan, and also with the Microwave Electronics Laboratory, Department of Microtechnology and Nanoscience, MC2, Chalmers University of Technology, Göteborg SE-412 96, Sweden (e-mail: jones2.mse94g@nctu.edu.tw; williamwu.mse90g@nctu. edu.tw; lihan@chalmers.se).
E. Y. Chang, C.-T. Wang, Y.-C. Wu, and S.-P. Tsai are with the Department of Materials Science and Engineering, National Chiao Tung University, Hsinchu 300, Taiwan (e-mail: edc@mail.nctu.edu.tw; rinexoper.mse95g@nctu.edu.tw; mai.mse96g@nctu.edu.tw; waterboyz@pchome.com.tw).
H. Zirath is with the Microwave Electronics Laboratory, Department of Microtechnology and Nanoscience, MC2, Chalmers University of Technology, Göteborg SE-412 96, Sweden (e-mail: herbert.zirath@chalmers.se).
Y.-C. Hu was with the Department of Materials Science and Engineering, National Chiao Tung University, Hsinchu 300, Taiwan. He is now with Everlight Electronics, Taipei 236, Taiwan.
Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TMTT.2010.2052960
package with low power consumption, low cost, small size, and light weight becomes indispensable. In this respect, the flip-chip interconnect has been regarded as a promising packaging tech-nology for cost-effective module assembly in MMW systems due to its shorter interconnect length, higher throughput for pro-duction, and smaller package size [1]–[9]. The flip-chip relia-bility, however, needs to be carefully considered since it relies only on several metallic connections between chip and carrier. One promising solution is using underfill to improve the relia-bility by enhancing the joint strength, protecting the intercon-nect from mechanical shock, and helping the heat dissipation [10]–[13]. However, underfill may result in performance degra-dation due to its higher dielectric constant and loss tangent compared to the air [14]–[16], which limits the usage of the flip-chip interconnect for high-frequency applications. This is one of the reasons why bond-wire is still the favorite pack-aging technology in microwave industry.
The RF characteristics of the flip-chip assembly with epoxy-based underfill have been investigated up to 40 GHz [15], demonstrating an additional insertion loss of 0.5 dB at 30 GHz. Kusamitsu et al. reported the RF characteristics of the flip-chip assembled 30-, 60-, and 77-GHz low-noise amplifier (LNA) monolithic microwave integrated circuits (MMICs) [16]. Due to the underfill effect, the frequency response of the MMICs shifted to lower frequency bands. The 30-GHz LNA was shifted by 3 GHz; the 60- and 77-GHz LNAs were shifted by 9 GHz.
In a flip-chip interconnect, the RF degradation due to under-fill is induced by three major factors: chip impedance change, parasitic capacitance, and material dielectric loss. The high di-electric constant of the underfill ( typically) tends to reduce the chip line impedance, resulting in impedance mis-match and reflection at the transitions [14]. By using low- un-derfill or designing in advance with the unun-derfill effects taken into account can ease this problem. Regarding to the parasitic effect, the flip-chip interconnect generally shows an overall ca-pacitive effects [1], [2], which could degenerate the interconnect performance at MMW frequencies. Due to the underfill injec-tion, the parasitic capacitance at the interconnect increases, indi-cating that a more inductive counterpart is needed for compensa-tion. Furthermore, a dielectric loss is induced as an epoxy-based
underfill is applied. The loss can
be reduced by introducing low-loss materials such as benzocy-clobutene (BCB) or other porous low- materials.
Moreover, for most commercial applications, reliability in-vestigations are generally required. The adhesion and coefficient
of thermal expansion (CTE) mismatch between chip and car-rier are very important factors for the flip-chip reliability. For MMW flip-chips, the adhesion relies only on a few bump inter-connections, which is deficient and very fragile at mechanical vibration. Besides, the CTE mismatch between chip and car-rier could lead to joint fatigue during temperature variation. By using underfill as a buffer layer, the adhesion can be improved and the thermal stress can be reduced significantly. Some in-vestigations about the MMW flip-chip reliability with epoxy underfill have been reported previously [15]–[17]. The fatigue life of the flip-chip assembly with underfill was investigated using finite-element analysis (FEA) simulation [15]. The sim-ulation results indicated that the joint fatigue life improved sig-nificantly after underfill was applied. Schmückle et al. demon-strated that using an Al O carrier ppm/K for a GaAs ppm/K flipped-chip has negligible thermal effect due to their small CTE mismatch [17]. However, the ad-hesion between chip and carrier should be taken into account before commercial applications can be realized.
In this study, the flip-chip assembly with epoxy-based under-fill was designed, fabricated, and characterized up to 67 GHz. The reliability tests including a 85 C 85 relative humidity (RH) test, thermal cycling test, and shear force test were per-formed to evaluate the feasibility of such packages for practical applications.
II. TESTSTRUCTURE ANDFABRICATION
Fig. 1 shows the schematic of the flip-chip interconnect struc-ture with underfill in this study (without any matching strucstruc-ture adopted). The GaAs chip and Al O substrate with the thick-ness of 100 and 254 m, respectively, were employed. The met-allization was 3 m Au (gold). The characteristic impedances of the coplanar waveguide (CPW) transmission lines on the chip and substrate were both 50 . The total length of the back-to-back flip-chip interconnect structure was 3000 m, in-cluding 1000 m on the chip and 2000 m on the substrate. The dimensions of the bump were fixed due to the fabrication con-cern. The diameter of the bump was 50 m; the bump height was 20 m.
The CPW transmission lines were first patterned and elec-troplated on the GaAs chip. The chip was then upside-down mounted on a sapphire carrier for thinning down to 100 m. After de-mounting from the sapphire carrier, the chip was diced into individual dies. The substrate with an Au CPW circuit and a bump was fabricated by an in-house bumping process, as re-ported in [18]. The Au-to-Au thermo-compression process was
Fig. 3. Measured and simulatedS-parameters of the flip-chip interconnect with and without underfill.
performed to bond the flip-chip interconnect structure. Fig. 2(a) shows the scanning electron microscope (SEM) image of the fabricated flip-chip interconnect structure.
After flip-chip bonding, the epoxy-based underfill (
and at 10 MHz) was injected into the gap between the chip and substrate by a capillary underfill process and cured at 150 C for 2 h. Fig. 2(b) shows the cross-sectional SEM image at the Au bump region. As shown in the micrograph, the under-fill was successfully under-filled into the gap without any voids.
III. DESIGN ANDOPTIMIZATION
The fabricated flip-chip samples were measured using on-wafer probing measurement with a short-open-load-thru (SOLT) calibration technique. During the measurement, a 10-mm-thick layer of Rohacell 31 ( at 26.5 GHz) was placed between the sample and the metal chuck of the probe station to avoid the grounded backside under the substrate. Fig. 3 shows the measured and simulated -parameters of the flip-chip interconnect with and without underfill from dc to 40 GHz. It is shown that both the return loss ( ) and insertion loss ( ) became worse after the underfill was applied. The was increased about 5 10 dB from dc to 40 GHz and the resonance frequency with lowest reflection shifted from 33 to 28 GHz. The reason is that the effective dielectric constant changed due to the insertion of the underfill. This effect will be further discussed in the following Section III-A. Fur-thermore, the underfill also induced significant dielectric loss
Fig. 4. (a) Simulation structures and CPW parameters for Case I (bare CPW line on GaAs chip), Case II(CPW + Al O ), Case III (CPW + Al O + Underfill), and Case IV (CPW+Al O +Underfill with Z matching). (b) Sim-ulatedS-parameters. (The CPW line length is 1000 m; the gap between the GaAs chip and Al O substrate is 20m; the thickness of the GaAs is 100 m; the thickness of the Al O is 254m.)
to the overall loss. The degraded about 0.2 0.4 dB from dc to 40 GHz.
In Sections III-A–C, both matching designs on the GaAs chip and Al O substrate were performed, targeting on a broadband interconnect performance with low return loss and low insertion loss. Moreover, the dielectric loss induced by underfill was ex-tracted from the measurement and simulation for comparison.
A. Matching Design on GaAs Chip
An underfill with acts to lower the of the transmis-sion line, leading to the performance deviation of the MMIC chip [14]. To solve this issue, the most effective method is to design in advance by taking the underfill effects into account. Fig. 4 shows the simulated CPW parameters and -parameters of a 50- CPW transmission line on GaAs chip. As can be seen,
a 50- CPW line showed a simulated of
below 30 dB from dc to 100 GHz (Case I). After the flip-chip, an Al O substrate is present under the CPW circuit (Case II).
Fig. 5. Measured and simulatedS-parameters of the flip-chip assembly with and withoutZ matching.
slightly increased to 7.10 and became 45 due to the flip-chip detuning effect. The degraded about 10 dB in av-erage as compared to Case I. When an epoxy-based underfill with was applied (Case III), the increased to 8.77 and the minimum shifted to lower frequency (from 57 to 51 GHz). was further lowered to 41 and decayed up to 16 dB. In Case IV, was 50 after modifying G (the gap between the signal and ground conductor) to 84 m. was 6.52 and the simulated was below 25 dB from dc to 100 GHz.
Based on the simulation, the flip-chip assembly with the impedance matching design on the GaAs chip was fabricated and measured. Fig. 5 shows measurement and simulation results. After the matching design was adopted, and improved below 25 GHz, but became worse beyond 25 GHz. At higher frequencies, the parasitic capacitance becomes sig-nificant, especially when the underfill is injected. The parasitic capacitance can be reduced and compensated with proper matching design on the Al O substrate.
B. Matching Design on Al O Substrate
Generally speaking, a flip-chip interconnect shows an overall capacitive effect, which would result in impedance mismatch and reflection at MMW frequencies [1], [2]. To improve the in-terconnect performance, reducing and compensating the para-sitic capacitance by employing proper matching design on the packaging carrier is essential. In previous reports, the MMW flip-chip interconnect with a matching design on the packaging carrier has been studied and investigated [1]–[9]. It has been demonstrated that reducing the metal pad overlap, increasing the bump height, and employing the inductive compensations can improve the reflection at the transitions [1]–[9]. Fig. 6 shows the optimized interconnect structure and performance after both matching designs on the GaAs chip and Al O substrate were adopted. The matching designs on the Al O substrate included a small metal pad overlap m , a high impedance line m , and a ground pad shrinking m . The bump height was fixed to 20 m due to the fabrication
Fig. 6. Optimized interconnect structure and performance.
Fig. 7. De-embeddedS11 of the optimized interconnect structure from 1 to 67 GHz (EM simulation).
concern. As can be seen, the flip-chip interconnect showed good broadband performance up to 67 GHz. From dc to 40 GHz, was less than 20 dB; from 40 to 67 GHz, was less than
25 dB. was within 0.6 dB from dc to 67 GHz, demon-strating excellent performance for flip-chip assembly with un-derfill material. Fig. 7 shows the de-embedded from the electromagnetic (EM) simulation. The inductive and capacitive behaviors versus frequency bands indicate that the matching de-signs were well adopted with a good counterbalance between the inductance and capacitance at the transition.
C. Dielectric Loss of Underfill Material
The loss induced by the underfill is not only due to the mis-match loss (reflection), but also due to the real loss (attenuation). In general, the real loss consists of three components: metal loss,
Fig. 8. L ,L ,L Al O , and L of the flip-chip as-sembly as extracted from the EM simulation; theL
was extracted from the measurement for comparison.
dielectric loss, and radiation loss. For a flip-chip assembly, the radiation loss is very small so that it can be neglected. The di-electric loss means an overall loss in carriers (chip and substrate) and underfill. To specifically identify the carrier loss , un-derfill loss , and metal loss , the following calcula-tions were employed. Equation (1) is the definition of the loss factor [19], the real loss
(1) To get the real loss induced by underfill with , one can subtract the real loss of the flip-chip assembly with
from the real loss of the flip-chip assembly with . Equation (2) gives the real loss induced by underfill. A similar approach can be applied for calculating the chip loss
and substrate loss Al O . Equation (3) gives the real loss induced by carriers. In the simulation, the of GaAs and Al O were set to be 0.006 and 0.0002, respectively,
(2) (3) On the other hand, to get the real loss induced by metal (gold), one can subtract the real loss of the flip-chip assembly with a perfect electrical conductor (PEC) from the real loss of the flip-chip assembly with a gold conductor. Equation (4) gives the real loss induced by metal as follows:
(4) Fig. 8 shows the underfill loss , chip loss , substrate loss Al O , and metal loss of the flip-chip assembly as extracted from the EM simulation. The underfill loss was also extracted from the
measurement for comparison. In
Fig. 9. 85 C=85% RH test results of the flip-chip assembly.
be seen, at lower frequencies, the measurement and simulation showed fair agreement, below 20 dB from dc to 35 GHz. Beyond 35 GHz, the underfill loss decayed up to 13 dB, which is almost the same level as the metal loss, the dominant loss at MMW frequency. The underfill loss can be minimized by using low-loss underfill material with . Further reducing to less than 0.0002 is not necessary since the induced loss is too small and can be neglected.
IV. RELIABILITY ANDMECHANICALSTRENGTH
Reliability investigation is always essential for commercial applications. In Sections IV-A–C, three types of reliability tests, i.e., 85 C 85 RH test, thermal cycling test, and shear force test, were performed to test the interconnect reliability of the flip-chip assembly.
A. 85 C 85 RH Test
The water absorption is an important issue, which would compromise the reliability during a long-term operation, espe-cially for a package with polymer materials. To test the water absorption of the flip-chip assembly, the samples were stored in an testing environment of 85 C and 85% RH for 96 h. Fig. 9 shows the testing results. The weight increased 4.3% (0.6 mg) for the sample without underfill and 6.8% (0.9 mg) for the sample with underfill after 96-h testing. The underfill contributed the water absorption of around 2.5% weight to the tested samples. Furthermore, no electrical failure was observed after the test.
B. Thermal Cycling Test
During temperature variation, the CTE mismatch between the chip and packaging carrier could lead to joint fatigue and con-sequent failure. To test the interconnect reliability, the thermal cycling test, i.e., temperature range from 55 C to 125 C with 15-min dwell time (specification of the Joint Electron Device Engineering Council (JEDEC) standard) was employed. The contact resistance measurement and -parameters measurement were used to check the testing results. In Fig. 10, it indicates that no sample failed and the contact resistance showed negli-gible change during the test no matter with or without under-fill. Fig. 11 shows the comparison of the measured -parame-ters (with underfill) before and after 1000 thermal cycles. The
Fig. 10. Thermal cycling test results of the flip-chip assembly.
Fig. 11. MeasuredS-parameters of the flip-chip assembly (with underfill) be-fore and after thermal cycling test.
RF performance did not decay after the test, showing excellent thermal mechanical stability of the flip-chip assembly. To the best of our knowledge, this was the first time the -parameters measurement was employed to check the flip-chip reliability in open literature.
Table I shows the material properties of some commonly used chip and substrate materials. As can be seen, GaAs, Si, and Al O have similar CTE and small CTE mismatch. Hence, using the Al O substrate for GaAs or Si flipped-chips has a negligible thermal effect in temperature variation [17]. This point is also supported by the testing results above. However, if one wants to further reduce cost by introducing organic substrates, the CTE mismatch becomes an important issue, and hence, the underfill is essential to improve the reliability.
C. Shear Force Test
Adhesion between the chip and substrate is very critical to the flip-chip reliability since it relies only on a few metallic con-nections, which is deficient and very fragile at mechanical vi-bration. The shear force test was performed to investigate the adhesion of the flip-chip assembly. Fig. 12 shows the testing results. Four samples were tested for each condition to obtain the average shear force. The shear force of the samples without
Fig. 12. Shear force test results of the flip-chip assembly.
underfill was 173 g. With the underfill application, the shear force was improved to 2052 g, which is about 12 times improve-ment, as compared to the samples without underfill. After 1000 thermal cycles, the shear force of the samples were 1584 g (with underfill) and 19 g (without underfill), respectively. The shear strength decayed after the thermal cycling test, especially for the samples without underfill. It is shown from these testing results that the application of the underfill has significantly improved the interconnect reliability of the flip-chip assembly.
V. CONCLUSION
In this study, the use of the epoxy-based underfill in the flip-chip interconnect is evaluated for applications from dc to 67 GHz. The matching designs on both the GaAs chip and Al O substrate were employed with the underfill effects taken into account. The optimized structure showed excellent performance of below 20 dB and less than 0.6 dB from dc to 67 GHz. For the dielectric loss induced by the underfill, the extracted results indicated that the loss can be further improved by using other lower loss underfill materials. The reliability tests including the 85 C 85 RH test, thermal cycling test, and shear force test were performed. The testing results revealed that with underfill, the flip-chip assembly had low water absorption, sustainable joint fatigue life, and robust joint strength, showing its potential for commercial MMW packaging applications.
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Göteborg, Sweden.
His main research interest is millimeter-wave packaging technology including flip-chip interconnects, hot-via interconnects, and integration ofV -/E-band multichip module (MCM) transceiver modules.
Wei-Cheng Wu was born in Hsinchu, Taiwan, in
1979. He received the B.S. degree from in mate-rials science and engineering from National Chiao Tung University, Hsinchu, Taiwan, in 2001, and is currently working toward the dual Ph.D. degrees in materials science and engineering and microtech-nology and nanoscience from National Chiao Tung University, Hsinchu, Taiwan and the Chalmers University of Technology, Göteborg, Sweden.
His research interests include fabrication, charac-terization, and packaging technologies of compound semiconductor devices and integrated circuits (ICs) for high-frequency applica-tions, especially flip-chip interconnects and transition design.
Edward Yi Chang (S’85–M’85–SM’04) received
the B.S. degree in materials science and engineering from National Tsing Hua University, Hsinchu, Taiwan, in 1977, and the Ph.D. degree in materials science and engineering from the University of Minnesota at Minneapolis–St. Paul, in 1985.
From 1985 to 1988, he was with the GaAs Component Group, Unisys Corporation, Eagan, MN. From 1988 to 1992, he was with the Micro-electronic Group, Comsat Laboratories. In 1992, he was involved with the GaAs monolithic microwave integrated circuit (MMIC) programs for both groups. In 1992, he was with National Chiao Tung University (NCTU), Hsinchu, Taiwan. In 1994, he helped set up the first GaAs MMIC production line in Taiwan, and in 1995, he became the President of Hexawave Inc., Hsinchu, Taiwan. In 1999, he returned to NCTU, where he is currently a Professor with the Department of Materials Science and Engineering. His research interests include new device and process technologies for compound semiconductor RF integrated circuits (RFICs) for wireless communication.
Dr. Chang is a Senior Member and Distinguished Lecturer of the IEEE Elec-tronic Devices Society.
Herbert Zirath (S’84–M’86) was born in Göteborg,
Sweden, on March 20, 1955. He received the M.Sc. and Ph.D. degrees from the Chalmers University, Göteborg, Sweden, in 1980 and 1986, respectively.
He is currently a Professor of high-speed elec-tronics with the Department of Microtechnology and Nanoscience, Chalmers University. In 2001, he became the Head of the Microwave Electronics Laboratory. He currently leads a group of approxi-mately 30 researchers in the area of high-frequency semiconductor devices and circuits. His main re-search interests include InP-HEMT devices and circuits, SiC- and GaN-based transistors for high-power applications, device modeling including noise and large-signal models for field-effect transistor (FET) and bipolar devices, and foundry-related monolithic microwave ICs for millimeter-wave applications based on both III–V and silicon devices. He also works part-time with Ericsson AB, Mölndal, Sweden, as a Microwave Circuit Expert. He has authored or coauthored over 220 papers in international journals and conference proceed-ings and one book. He holds four patents.
Chin-Te Wang was born in Taipei, Taiwan, on
November 6, 1983. He received the B.S. degree in materials science and engineering from Na-tional Chung Hsing University (NCHU), Taichung, Taiwan, in 2006, and is currently working toward the M.S. and Ph.D. degrees at National Chiao Tung University (NCTU), Hsinchu, Taiwan.
While with NCHU, he was interested in electric materials. He then joined the Compound Semicon-ductor Device Laboratory, NCTU.
Yun-Chi Wu was born in Chiayi, Taiwan. He
received the B.S. degree in materials science and engineering from Tatung University, Taipei, Taiwan, in 2001, the M.S. degree in materials science and engineering from National Chiao Tung University (NCTU), Hsinchu, Taiwan, in 2003, and is currently working toward the Ph.D. degree in materials science and engineering at NCTU.
He is currently with the Compound Semicon-ductor Device Laboratory, Department of Materials Science and Engineering, NCTU. His research is focused on HEMT device and process technologies for wireless communication applications.
Szu-Ping Tsai was born in Pingtung, Taiwan on
Feb-ruary 2, 1985. She received the B.S. degree in ma-terials science and engineering from National Chiao Tung University (NCTU), Hsinchu, Taiwan, in 2007, and is currently working toward the M.S. degree at NCTU.
In 2007, she joined the Compound Semiconductor Device Laboratory, NCTU, where she has been in-volved in the area of the flip-chip technology with a focus on aspects of finite-element thermomechanical modeling and simulation.
