The extraction of MOSFET gate capacitance from S-parameter measurements

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The extraction of MOSFET gate capacitance from

S-parameter measurements

Jiong-Guang Su

a

, Shyh-Chih Wong

b

, Chun-Yen Chang

a,*

, Tiao-Yuan Huang

a

a_{Institute of Electronics, National Chiao Tung University, 1001 Ta Hsueh Road, Hsinchu 300, Taiwan} b_{Research &Development, Taiwan Semiconductor Manufacturing Co., 9 Creation Road 1, Science-Based Industrial Park,}

Hsinchu 300, Taiwan

Received 21 November 2000; received in revised form 26 July 2001; accepted 18 January 2002

Abstract

A new gate capacitance extraction method from S-parameter measurements is proposed. The distributed nature of MOS transistor and the in-series substrate resistance and in-parallel gate conductance are taken into consideration in the gate capacitance extraction by using high-frequency S-parameter measurements. The error due to dissipation factor can be more eﬀectively reduced by this method, compared to the conventional C–V measurements. Successful

ex-traction of gate capacitance from test transistors with designed test pads has been demonstrated. Ó 2002 Elsevier

1. Introduction

Gate capacitance measurement of MOS transistor is an important technique to monitor the quality and also to determine the electrical thickness of gate dielectric. In addition, its role is also crucial in gaining physical in-sights into the MOSFET operation, and for developing suitable large- and small-signal models. For deep-sub-micron devices, due to the short- and narrow-channel effects, the electric field and charge distribution can no longer be treated by one-dimensional analysis. Hence, direct gate capacitance measurement of MOS transistors should be performed to reflect the exact physical features of the transistors themselves. However, existing tech-niques in direct gate capacitance measurements of MOS transistors are not sufficiently adequate in this regard.

Conventional methods for determining the gate ca-pacitance of MOS transistor are to use the quasi-static or high-frequency capacitance–voltage (C–V ) measure-ments. However, even with the so-called

‘‘high-frequen-cy’’ C–V measurement, a universally accepted frequency of no more than 1 MHz is usually employed [1]. Worse, test structures with large capacitor area are normally required to minimize possible instrument errors due to the large dissipation factor when the gate capacitance is too small, and/or the dielectric conductance is too large [2]. These large test structures, however, cannot be used to reflect the short- and/or narrow-channel effects ex-isting in small-size real MOS transistors. Instead, two-dimensional and/or three-two-dimensional device simulators are usually adopted for calculating capacitance of small dimensional devices. This approach, however, can only yield qualitative results due to improper device models and difficulties in accurate parameter calibration. To make things worse, the capacitance measured by these conventional techniques may not faithfully predict the behavior of the MOS transistor when the device is under high-frequency operation (e.g., more than 1 GHz).

Recently, several literatures have reported the capac-itance extraction of MOS transistor by using y-param-eter that was obtained from high-frequency S-paramy-param-eter measurements [3–5]. The capacitance was extracted by using the equivalent small-signal model. However, the capacitance was based on the lump elements of small-signal equivalent circuit, and second-order approx-imation of frequency was used. Besides, the distributed

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*

Corresponding author. Tel.: 517-8083; fax: +886-3-572-1500.

E-mail address:cyc@cc.nctu.edu.tw(C.-Y. Chang).

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nature of the high-frequency behavior was not taken into account in these methods.

In this paper, we proposed a new method to extract the gate capacitance, using a simple test transistor structure, from the S-parameter measurements and transmission line theory. This method is more robust to errors caused by dissipation factor, and can be used to more accurately extract the small gate capacitance in small (i.e., short- and narrow-channel) test transistor without resorting to two-dimensional numerical simu-lation [1,6].

2. Experiment and measurement

MOS transistors used in this study were fabricated on 6-in. wafers with a 0.35 lm logic baseline technology.

The gate oxide thickness was 70 AA. The as-grown poly-silicon gate thickness was 0.25 lm. A sidewall spacer with a width of 0.21 lm was used in the self-aligned silicidation of source/drain and gate (i.e., salicidation) with TiN material. The ﬁnal gate sheet resistance was 2– 5 X/ after salicidation.

The conﬁguration of a conventional C–V measure-ment is shown schematically in Fig. 1(a). The source, drain and bulk of an n-channel MOS transistor are tied together and connected to the Hi-end of an HP4284 LCR meter to avoid substrate noise. The gate terminal is connected to the Lo-end of the LCR meter for sensing the AC signal coming out from the gate [7]. A BSIMPro extractor was used as the controller [7]. The magnitude

Fig. 1. (a) The setup conﬁguration using a HP4284 LCR meter. (b) Measured gate capacitance from a conventional C–V mea-surement for a device with gate width=length¼ 100 lm=0:35 lm. The bias range is3:6 to 3.6 V. Note that a large width is usually required in this method.

Fig. 2. Test pads configuration for (a) conventional common-source configuration for RF testing, and (b) special G–S–G pad configuration for the proposed method. Note that the bulk is connected to port-2 of the network analyzer in the new method.

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of the input AC signal was 50 mV with 100 KHz fre-quency in the LCR meter setup. Fig.1(b) shows an example of the measured Cggversus the gate bias for an

n-channel transistor. The gate bias is swept from3:6 to þ3:6 V. The masked gate width and length of the transistor are 100 and 0.35 lm, respectively. It is worthy to note here that a large-width transistor is normally

necessary in this approach to ensure a suﬃcient Cgg

value.

The proposed method of extracting Cgg from

S-parameter measurements, on the other hand, allows the use of test transistor with smaller dimensions. In addi-tion, higher frequency (i.e., GHz) is used, which can more faithfully represents the capacitance behavior un-der high-frequency operation. Fig. 2(a) shows the com-monly used common-source conﬁguration of RF testing pattern, while Fig. 2(b) shows the test pads design for the new method. The bulk of the test transistor in the pro-posed method is connected to port-2, while the source and drain are connected to the ground pads. In addition, the pads are conﬁgured in ground–signal–ground of each port for S-parameter measurements. The S-parameter measurements are executed using an HP8510C network analyzer, and the sweep frequency range is 1.25–10.05 GHz. The controller is a HP ICCAP. The network an-alyzer performed short-open-load-through (SOLT) cali-bration in ISS (i.e., impedance-standard-substrate) before S-parameter measurements [8]. Fig. 3 shows an extracted gate capacitance by using the proposed method. The gate bias range here is2.5 to 2.5 V with the bulk bias equal to zero volts (i.e., bias of port-2 is 0 V). The masked gate width and length of the test transistor are 20 and 0.35 lm, respectively. All the extracted values by using S-param-eter measurements were de-embedded by using the ‘‘two-step de-embedding’’ procedure before extraction [9,10]. The proposed gate-capacitance extraction method will be discussed in more detail in the next section.

3. Extraction method

Since port-2 of nMOS transistor used in S-parameter measurements is the bulk terminal, the RF power ﬂows mainly along the gate width direction and toward the substrate. As shown schematically in Fig. 4, the dis-tributed elements along the gate width direction as seen from the gate contact consist, in per unit length, of in-series gate resistance (Rg), in-series gate inductance (Ls),

in-parallel gate capacitance (Cp), in-parallel gate

con-ductance (Gp) and in-series substrate resistance (Rb).

Hence, the gate stack can be modeled using a set of distributed elements as shown in Fig. 4. Here we assume that the in-parallel capacitance Cpcontains all pertinent

capacitance such as Cox, Csemi, Cpoly [2] and the

outer-fringing and overlap capacitance.

Based on the distributed structure of Fig. 4, the input impedance, Zin, as seen from the gate contact, can be

derived by using the transmission line theory [11], and we obtain: Zin¼ q_sheetW 3L þ Gpþ RbG2pþ x 2_R bCp2 WðG2 pþ x2Cp2Þ þ j xWLs 3 " xCp WðG2 pþ x2C2pÞ # ; ð1Þ

where q_sheetis the sheet resistance of the resistive gate, W and L are the gate width and length, respectively. x is the operation radius frequency, and Rb, Ls, Gp, Cp are the

substrate resistance, series inductance, parallel conduc-tance and capaciconduc-tance per unit length along the gate width direction, respectively. It is interesting to note that

Fig. 3. Gate capacitance versus gate voltage curve extracted by using S-parameter measurements. The gate width and length are 20 and 0.35 lm, respectively.

Fig. 4. Schematic showing the distributed nature of MOS gate stack. Rg, Rb, Ls, Gp, Cpare the series gate resistance, substrate

resistance, series inductance, parallel conductance and capaci-tance per unit length along the gate width direction, respec-tively.

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the contribution of the substrate resistance is incorpo-rated into the real part of the input impedance. The term we are most interested is the imaginary part of Eq. (1). By using only the imaginary term, the substrate resis-tance that causes the measured capaciresis-tance degradation in [2] can be excluded in our capacitance extraction. The ﬁrst term in the imaginary part of Eq. (1) can be ignored in a few GHz frequency range, because of the small value of Ls (in the order of pico-H/lm range) [5]. Then

we can express the imaginary part of input impedance in a simpliﬁed form: ImðZinÞ ﬃ xCp WðG2 pþ x2C2pÞ ¼ 1 WðxCpÞ 1 1þ G2 p=x2Cp2 1 WðxCpÞ : ð2Þ

Eq. (2) neglects the termðGp=xCpÞ2, which will be

dis-cussed in the next section. By taking the logarithm on both sides of Eq. (2), we obtain the following equation: log½ImðZinÞ ¼ logðxWCpÞ

¼ log f logð2pCggÞ: ð3Þ

Here x is equal to 2pf and WCp is equal to Cgg, which

represents the capacitance seen from the gate contact. Eq. (3) is a linear function with the slope equal to1, and its interception equals logð2pCggÞ, if the variables

are Y ¼ log½ImðZinÞ and X ¼ log f , respectively. By

using the relationship shown in Eq. (3), the eﬀective capacitance at the gate contact can be determined from the interception.

4. Results and discussions

Fig. 5 shows the measured log½ImðZinÞ versus log f

with diﬀerent gate biases of1, 0 and 2.5 V. The device

under test (DUT) is an n-type MOS transistor with the gate width and length equal to 20 and 0.35 lm, respec-tively. The input impedance can be obtained from the measured S-parameters of DUT. It shows that the slope approaches1, and all the curves are in parallel. This result is consistent with Eq. (3). Hence, the interception can be determined by extrapolation of the lines and the capacitance Cgg can be extracted. The extracted Cggby

using our method is shown previously in Fig. 3. The

range of gate bias is from 2:5 to 2.5 V, with 0.25 V

increments. Despite the high-frequency operation, the

nþ _{source/drain serves to supply abundant channel}

charge that follows the applied gate signal, as the source/ drain of the DUT is connected to the AC ground of the network analyzer [12]. Hence the capacitance increases with increasing gate bias in strong inversion region. This is regardless of the fact that the thermal recombination– generation rate of carriers in the bulk depletion region cannot follow the fast excitation of the input signal, and thus does not contribute to the inversion layer charges.

As mentioned previously, the dissipation factor cau-ses instrument error in LCR meter. The error increacau-ses when the gate oxide conductance is larger or the ca-pacitance is smaller [1,2]. Eqs. (4) and (5) represent the dissipation factor and the corresponding instrument error, respectively.

D¼ G

xC; ð4Þ

%error¼ 0:1pffiffiffiffiffiffiffiffiffiffiffiffiffiffi1þ D2_; _ð5Þ

where G and C are the eﬀective in-parallel conduc-tance and capaciconduc-tance of the measured capacitor, respectively.

Fig. 5. Imaginary part of input impedance (Zin) versus

fre-quency with diﬀerent gate biases of1, 0 and 2.5 V.

Fig. 6. The error term as a function of operation frequency with diﬀerent gate biases of1, 0 and 2.5 V.

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A useful way to reduce the dissipation factor is to increase the operation frequency of AC signal, and hence, reduce the dissipation factor. However, this is diﬃcult to achieve in an LCR meter, and the distribu-tion nature should be taken into account. One can compare the neglected termðGp=xCpÞ

2

in Eq. (2) with the dissipation factor in Eq. (4). The neglected term in the new method is proportional to D2_{, meaning that our}

method is more eﬀective in reducing the possible errors as long as xCp> Gp. This is especially true in GHz

operation frequency. Fig. 6 shows the measured ne-glected term versus frequency. It can be seen that this term indeed approaches zero with increased operation frequency. The maximum value occurs when the applied gate bias equals 0 V. Besides, all the observed values in this ﬁgure are less than 107_{, indicating that the eﬀect}

due to this term can indeed be neglected when we cal-culate the capacitance seen from the gate contact in our proposed method.

Table 1 shows the ﬁve-point oxide thickness on the same wafer by using the large-area capacitance mea-surement. The oxide thickness shown in Table 1 was determined by using the conventional C–V measure-ment. The calculated oxide capacitance for a device with gate width/length equal to 20 lm/0.35 lm is shown in the second row of the table. The third row is the gate capacitance obtained from our new method. It can be seen clearly that the extracted results from our method are satisfactorily accurate.

5. Conclusion

A method to extract gate capacitance of MOSFET by using S-parameter is proposed. This method con-siders the eﬀects of the in-parallel substrate resistance and gate conductance, and also considers the distributed nature of the MOS transistor. In addition, the proposed method is inherently more robust to errors caused by the dissipation factor, and therefore it is more suitable for measuring small-geometry capacitance than conven-tional C–V measurements.

Acknowledgement

This work was supported in part by National Science Council, Taiwan, ROC, under contract NSC90-2215-B009-072.

References

[1] Arora N. MOSFET models for VLSI circuit simulation. Wien (NY): Springer; 1993.

[2] Henson WK, Ahmend KZ, Vogel EM, Hauser JR, Wortman JJ, Venables RD, et al. Estimating oxide thick-ness of tunneling oxides down to 1.4 nm using conventional capacitance–voltage measurements on MOS capacitors. IEEE Electron Dev Lett 1999;20:179.

[3] Dambrine G, Cappy A, Heliodore F, Playez E. A new method for determining the FET small-signal equivalent cir-cuit. IEEE Trans Microwave Theory Tech 1988;36: 1151. [4] Lovelace D, Costa J, Camilleri N. Extracting small-signal

model parameters of silicon MOSFET transistors. IEEE Dig MTT-S 1994:865.

[5] Lee S, Yu HK, Kim CS, Ko JG, Nam KS. A novel approach to extracting small-signal model parameters of silicon MOSFET’s. IEEE Microwave Guided Wave Lett 1997;7(3):75;

Stathis JH, DiMaria DJ. In: Reliability projection for ultra-thin oxides at low voltage. IEDM Tech; 1998. p. 167. [6] BSIM3v3 Manual, 1995. p. 4–5.

[7] BSIMPro Manual. 1997.

[8] Kolding TE. On-wafer calibration techniques for gigahertz CMOS measurements. In: International Conference on MTS, 1999 March, vol. 12.

[9] Koolen MCAM, Geelen JAM, Versleijen MPJG. An improved de-embedding technique for on-wafer high-frequency characterization. In: IEEE Proceedings of Bi-polar Circuit and Technology Meeting, 1991. p. 188. [10] Jen SHM, Enz CC, Pehlke DR, Schr€ooter M, Sheu BJ.

Accurate modeling and parameter extraction for MOS transistors valid up to 10 GHz. IEEE Trans Electron Dev 1999;46(11):2217.

[11] Kolding TE. Calculation of MOSFET input gate imped-ance. Technology Report of RISC, 1998.

[12] Chan M, Hui KY, Hu C, Ko PK. A robust and physical BSIM3 non-quasi-static transient and AC small-signal model for circuit simulation. IEEE Trans Electron Dev 1998;45(4):834.

Table 1

Five-point on-wafer oxide thickness by using large-area capacitance measurements (ﬁrst row), their equivalent small-geometry oxide capacitance (second row) and oxide capacitance extracted from S-parameter measurements (third row)

Position Center Up Down Left Right

tox(nm) 7.3353 7.352 7.4075 7.3983 7.393

Cox¼ ðeox=toxÞWL (fF) 32.937 32.862 32.616 32.657 32.680