Performance Enhancement of the nMOSFET Low Noise Amplifier by Package Strain

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160 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 54, NO. 1, JANUARY 2007

REFERENCES

[1] A. W. L. Ng and H. C. Luong, “A 1-V 17 GHz 5 mW quadrature CMOS VCO based on transformer coupling,” in Proc. IEEE ISSCC, San Francisco, CA, 2006, pp. 198–199.

[2] D. J. Cassan and J. R. Long, “A 1-V transformer-feedback low-noise amplifier for 5-GHz wireless LAN in 0.18 µm CMOS,” IEEE J. Solid-State Circuits, vol. 38, no. 3, pp. 427–435, Mar. 2003.

[3] K. Kwok and H. C. Luong, “Ultra-low-voltage high-performance CMOS VCOs using transformer feedback,” IEEE J. Solid-State Circuits, vol. 40, no. 3, pp. 652–660, Mar. 2005.

[4] C. P. Yue and S. S. Wong, “On-chip spiral inductors with patterned ground shields for Si-based RF IC’s,” IEEE J. Solid-State Circuits, vol. 33, no. 5, pp. 743–752, May 1998.

[5] K. T. Ng, B. Rejaei, and J. N. Burghartz, “Substrate effects in monolithic RF transformers on silicon,” IEEE Trans. Microw. Theory Tech., vol. 50, no. 1, pp. 377–383, Jan. 2002.

[6] T. H. Lee, The Design of CMOS Radio-Frequency Integrated Circuits, 2nd ed. Cambridge, U.K.: Cambridge Univ. Press, 2004, pp. 148–158. [7] G. R. Aiello and G. D. Rogerson, “Ultra-wideband wireless systems,”

IEEE Microw. Mag., vol. 4, no. 2, pp. 36–47, Jun. 2003.

[8] K. Chong and Y. H. Xie, “High-performance on-chip transformers,” IEEE Electron Device Lett., vol. 26, no. 8, pp. 557–559, Aug. 2005.

Performance Enhancement of the nMOSFET Low-Noise Amplifier by Package Strain W.-C. Hua, H.-L. Chang, T. Wang, C.-Y. Lin, C.-P. Lin,

S. S. Lu, C. C. Meng, and C. W. Liu

Abstract—The package strain improves the noise figure (NF) of the low-noise amplifier (LNA). The maximum noise reduction is∼0.53 dB (13%) at the operating frequency of 2.4 GHz under the biaxial tensile strain of 0.037%. The NF reduction of the strained LNA is mainly due to the enhanced transconductance and cutoff frequency of the individual nMOSFET device under the same strain and bias conditions.

Index Terms—Biaxial strain, cutoff frequency, low-noise amplifier (LNA), noise factor, noise figure (NF), package strain, tensile, transconductance.

I. INTRODUCTION

The strained-Si technology has attracted great attention due to the enhancement of the carrier mobility. There are three methods to obtain the strain in the Si channel of the MOSFET device, namely 1) substrate strain [1]–[4], 2) process strain [5]–[8], and 3) mechan-ical strain/package strain [9]–[12]. The shortages of the substrate strained-Si are high defect density, thermal budget limitation, and higher fabrication cost. Although the process strain technology can im-prove the current drive and mobility of both nMOSFET and pMOSFET devices with the advantage of simplicity and low cost, it can only be applied to very short-channel devices (Lg<∼50 nm). However,

the package strain has the flexibility to apply the uniaxial or biaxial strain to the devices with different channel lengths. Package strain can be also applied to the circuits that already have built-in strain to

Manuscript received June 9, 2006; revised September 25, 2006. The review of this brief was arranged by Editor M. J. Deen.

W.-C. Hua, H.-L. Chang, T. Wang, C.-Y. Lin, C.-P. Lin, S. S. Lu, and C. W. Liu are with the Department of Electrical Engineering and Graduate Institute of Electronics Engineering, National Taiwan University, Taipei 10617, Taiwan, R.O.C. (e-mail: [email protected]).

C. C. Meng is with the Department of Communication Engineering, National Chiao-Tung University, Hsinchu 30050, Taiwan, R.O.C.

Digital Object Identifier 10.1109/TED.2006.887194

Fig. 1. Schematic of the LNA circuit and the circuit block for the noise analysis.

further increase the circuit performance by the strain addition. The low cost, flexibility, and modular properties of the package strain make it attractive for future production. The performance enhancement of the strained-Si is proven not only at the transistor level but also at the circuit level. The performance enhancement of ring oscillators and transimpedance amplifiers by package strain has been reported previously [12].

In this brief, the noise figure (NF) reduction of the 0.35-µm nMOSFET low-noise amplifier (LNA) by external package strain is reported, and the theoretical analysis is also given to study the NF reduction.

II. LNA DESIGN

Fig. 1 shows the schematic of the LNA circuit. The designed central frequency of the LNA is 2.4 GHz. The geometries (L× W × finger) of the nMOSFET devices in the LNA circuit are 0.35 µm× 20 µm × 8 and 0.35 µm× 20 µm × 4 for M1 and M2, respectively. The LNA consists of a source input stage cascaded with a common-gate (CG) output stage. The inductor LIMis the interstage matching

inductor.

III. RESULTS ANDDISCUSSION

The noise factor F of a cascaded two-stage LNA is given by [13] F = F1+

F2− 1

G1

≈ F1 (1)

where F1, F2, and G1 denote the noise factor of the first stage,

the noise factor of the second stage, and the gain of the first stage, respectively. The total noise factor is mainly determined by F1if G1

is large enough.

Thus, the noise analysis of the LNA can be simplified to the circuit block of M1 with Lgand Ls(dashed block in Fig. 1). The noise factor

of such LNA topology is given by [14]

F = 1 +Rg Rs +Rl Rs + γχgd0RS f0 fT 2 (2) where Rs, Rg, and Rlare the source resistance (50 Ω), the gate

resis-tance, and the parasitic resistance of Lg, respectively. γ, χ, gd0, f0, and

fT are the fitting parameter of the channel thermal noise, the scaling

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IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 54, NO. 1, JANUARY 2007 161

Fig. 2. Measured gmversus VGSof the individual device with the same size

as M1 for the strained and unstrained conditions. The enhancement of gmis

∼5.8% under the biaxial tensile strain of 0.037%.

M1, the operating frequency, and the cutoff frequency of M1. Since α = gm/gd0[14], the total noise factor can be simplified to

F = 1 + Rg Rs + Rl Rs +gm f2 T A (3)

by assuming A = γχRsf02/α. The transconductance (gm)

propor-tionality of the last term in (3) is due to the proporpropor-tionality of the channel thermal noise to gm, and the inverse fT2 of the last term

in (3) is due to the referring of the drain current noise to the gate. To calculate the noise factor reduction (∆F ) and NF reduction (∆NF) of the LNA under package strain, we assume that A and the resistances Rs, Rg, and Rlremain unchanged under package strain.

Since the last term in (3) is the most significant term [14], ∆F and ∆NF can be expressed as ∆F = F− FS F = gm f2 T A 1−gm,S gm fT fT ,S 2 F ≈ (F− 1) 1−gm,S gm fT fT ,S 2 F (4) ∆NF = NF− NFS

= 10 log F− 10 log FS = 10 log(1− ∆F )

≈ 10 log        1− (F− 1) 1−gm,S gm fT fT ,S 2 F        (5)

respectively. The parameters with a subscript of S are the values under package strain.

The package strain conditions for all the experiments in this brief are biaxial tensile strain of 0.037%. All the measurements for both LNA circuit and nMOSFET device under strained and unstrained conditions are on-wafer measurements without package bondwires. The chip of the LNA circuit is tightly glued to the Si wafer, which serves as the package substrate. The mechanical stress is applied to the package substrate, and the chip is stressed via the glue between the chip and the package substrate. The details of the strain mechanism can be found in the previous work [12]. More than ten samples have been characterized to ensure the repeatability of the performance enhancements of the LNA and nMOSFET device under package strain. The results of the typical samples are presented in this brief.

Fig. 2 shows the measured gmversus gate–source voltage (VGS) of

the individual device with the same size as M1 for both strained and

Fig. 3. Measured fTof the device with the same size as M1 for the strained

and unstrained conditions. The enhancement of fTis∼7.7% under the biaxial

tensile strain of 0.037%.

Fig. 4. Measured NF of the LNA circuit and the nMOSFET device under both strained and unstrained conditions. The inset shows the NF of the device with 50-Ω source and load terminations.

unstrained conditions. The measured gmunder strained and unstrained

conditions at VGSof 1.2 V and at drain voltage of 2 V are 54.8 and

51.8 mS, respectively. The enhancement of gmis∼5.8% at the same

bias as M1 in Fig. 1. Fig. 3 shows the fT of the individual device

for both strained and unstrained conditions. The extrapolated fT

(−20 dB/dec) from the h21 data under strained and unstrained

con-ditions are 26.5 and 24.6 GHz, respectively. The enhancement of fTis

∼7.7% under the same strain and bias conditions as M1 in Fig. 1. Fig. 4 shows the measured NF of the LNA circuit and the nMOSFET device under both strained and unstrained conditions. The inset of Fig. 4 shows the NF of the device with 50-Ω source and load termina-tions. The ∆NF of the strained device is about 0.2–0.3 dB as compared to the unstrained device. The NF of the device is larger than the NF of the LNA due to the nonoptimized source impedance. The statistical results of the LNA NF in Fig. 4 are obtained from 20 measurements of the same sample. The error bars stand for the standard deviation of the NF data, which result from the measurement error. The NF of the LNA at 2.4 GHz in this brief is relatively larger than the NF of the LNA in 0.35-µm CMOS device technology reported in the literatures (3.7–5.3 dB) [15]–[17]. The maximum ∆NF is 0.53 dB, which is equivalent to the ∆F of 13% at 2.4 GHz. The calculated ∆NF based on (5) are from 0.29 to 0.33 dB, whereas the measured ∆NF vary from 0.18 to 0.53 dB (1.8–2.5 GHz). The calculation agrees qualitatively with the experimental data, but there is a quantitative discrepancy between the analytical value and the experimental data. This discrep-ancy is probably due to the negligence of the noise contribution of the second CG stage since gain G1is not sufficiently large.

IV. CONCLUSION

The performance enhancement of the 0.35-µm nMOSFET LNA circuit is achieved by the external package strain. Due to the enhanced

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162 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 54, NO. 1, JANUARY 2007

gmand fT of the nMOSFET device under biaxial tensile strain, the

NF (noise factor) of the LNA can be reduced to as high as 0.53 dB (13%) at 2.4 GHz. Theoretical analysis of the NF reduction based on the enhanced gmand fTis also proposed to study the noise reduction.

The performance enhancement under biaxial tensile strain is expected for the LNA with the same topology despite of the technology node of the device.

REFERENCES

[1] K. Rim, “Strained-Si surface channel MOSFETs for high-performance CMOS technology,” in Proc. IEEE ISSCC Dig. Tech. Papers, San Francisco, CA, 2001, pp. 116–117.

[2] J. L. Hoyt, H. M. Nayfeh, S. Eguchi, I. Aberg, G. Xia, T. Drake, E. A. Fitzgerald, and D. A. Antoniadis, “Strained silicon MOSFET technology,” in IEDM Tech. Dig., San Francisco, CA, 2002, pp. 23–26. [3] K. Rim, S. Narasimha, M. Longstreet, A. Mocuta, and J. Cai, “Low field

mobility characteristics of sub-100 nm unstrained and strained-Si MOSFETs,” in IEDM Tech. Dig., San Francisco, CA, 2002, pp. 43–46.

[4] M. H. Lee, P. S. Chen, W.-C. Hua, C.-Y. Yu, Y. T. Tseng, S. Maikap, Y. M. Hsu, C. W. Liu, S. C. Lu, and M.-J. Tsai, “Comprehensive low-frequency and RF noise characteristics in strained-Si nMOSFETs,” in IEDM Tech. Dig., Washington, DC, 2003, pp. 69–72.

[5] A. Shimizu, K. Hachimine, N. Ohki, H. Ohta, M. Koguchi, Y. Nonaka, H. Sato, and F. Ootsuka, “Local mechanical-stress control (LMC): A new technique for CMOS-performance enhancement,” in IEDM Tech Dig., Washington, DC, 2001, pp. 433–436.

[6] S. Thomson, N. Anand, M. Armstrong, C. Auth, B. Arcot, M. Alavi, P. Bai, J. Bielefeld, R. Bigwood, J. Brandenburg, M. Buehler, S. Cea, V. Chikarmane, C. Choi, R. Frankovic, T. Ghani, G. Glass, W. Han, T. Hoffmann, M. Hussein, P. Jacob, A. Jain, C. Jan, S. Joshi, C. Kenyon, J. Klaus, S. Klopcic, J. Luce, Z. Ma, B. Mcintyre, K. Mistry, A. Murthy, P. Ngujyen, H. Pearson, T. Sandford, R. Schweinfurth, R. Shaheed, S. Sivakumaar, M. Taylor, B. Tufts, C. Wallace, P. Wang, C. Weber, and M. Bohr, “A 90 nm logic technology featuring 50 nm strained silicon channel transistors, 7 layers of Cu interconnects, low-k ILD, and 1 µm2 _{SRAM cell,” in IEDM Tech. Dig., San Francisco, CA, 2002,}

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[7] T. Ghani, M. Armstrong, C. Auth, M. Bost, P. Charvat, G. Glass, T. Hoffmann, K. Johnson, C. Kenyon, J. Klaus, B. Mclntyre, K. Mistry, A. Murthy, J. Sandford, M. Silberstein, S. Sivakumar, P. Smith, K. Zawadzki, S. Thompson, and M. Bohr, “A 90 nm high volume manufacturing logic technology featuring novel 45 nm gate length strained silicon CMOS transistors,” in IEDM Tech. Dig., Washington, DC, 2003, pp. 978–991.

[8] C.-H. Ge, C.-C. Lin, C.-H. Ko, C.-C. Huang, Y.-C. Huang, B.-W. Chan, B.-C. Perng, C.-C. Sheu, P.-Y. Tsai, L.-G. Yao, C.-L. Wu, T.-L. Lee, C.-J. Chen, C.-T. Wang, S.-C. Lin, Y.-C. Yeo, and C. Hu, “Process-strained-Si (PSS) CMOS technology featuring 3-D strain engineering,” in IEDM Tech. Dig., Washington, DC, 2003, pp. 73–76.

[9] C. Gallon, G. Reimbold, G. Ghibaudo, R. A. Bianchi, and R. Gwoziecki, “Electrical analysis of external mechanical stress effects in short channel MOSFETs on (001) silicon,” Solid State Electron., vol. 48, no. 4, pp. 561–566, Apr. 2004.

[10] S. Maikap, C.-Y. Yu, S.-R. Jan, M. H. Lee, and C. W. Liu, “Mechanically strained strained-Si nMOSFETs,” IEEE Electron Device Lett., vol. 25, no. 1, pp. 40–42, Jan. 2004.

[11] S. Maikap, M. H. Liao, F. Yuan, M. H. Lee, C.-F. Huang, S. T. Chang, C. W. Liu, “Package-strain-enhanced device and circuit performance,” in IEDM Tech. Dig., San Francisco, CA, 2004, pp. 233–236.

[12] F. Yuan, C.-F. Huang, M.-H. Yu, and C. W. Liu, “Performance en-hancement of ring oscillators and transimpedance amplifiers by pack-age strain,” IEEE Trans. Electron Devices, vol. 53, no. 4, pp. 724–729, Apr. 2006.

[13] G. Gonzalez, Microwave Transistor Ampliﬁers Analysis and Design. Upper Saddle River, NJ: Prentice-Hall, 1997.

[14] D. K. Shaeffer and T. H. Lee, “A 1.5-V, 1.5-GHz CMOS low noise amplifier,” IEEE J. Solid-State Circuits, vol. 32, no. 5, pp. 745–759, May 1997.

[15] R.-M. Weng and P.-S. Lin, “A 2 V low noise amplifier with tunable image filtering,” in Proc. IEEE APCCS, Tainan, Taiwan, R.O.C., 2004, pp. 293–296.

[16] J.-Y. Su, C. C. Meng, Y.-H. Li, S.-C. Tzeng, and G.-W. Huang, “2.4 GHz 0.35 µm CMOS single-ended LNA and mixer with gain enhancement techniques,” in Proc. IEEE APMC, Suzhou, China, 2005, pp. 1550–1553. [17] C.-C. Tang, C.-H. Wu, and S.-I. Liu, “Miniature 3-D inductors in standard CMOS process,” IEEE J. Solid-State Circuits, vol. 37, no. 4, pp. 471–480, Apr. 2002.

Analytical Charge and Capacitance Models of Undoped Cylindrical Surrounding-Gate MOSFETs

Oana Moldovan, Benjamin Iñiguez, David Jiménez, and Jaume Roig

Abstract—We present an analytical and continuous charge model for cylindrical undoped surrounding-gate MOSFETs, from which analytical expressions of all total capacitances are obtained. The model is based on a unified charge control model derived from Poisson equation. The drain current, charge, and capacitances are written as continuous explicit functions of the applied voltages. The calculated capacitance character-istics show excellent agreement with three-dimensional numerical device simulations.

Index Terms—Compact device modelling, intrinsic capacitances, surrounding-gate (SGT) MOSFET.

I. INTRODUCTION

The surrounding-gate (SGT) MOSFET is one of the most promis-ing candidates for the downscale of CMOS technology toward the nanometer-channel-length range since the SGT architecture allows excellent control of the channel charge in the silicon film, reducing short-channel effects [1]–[5].

Compact models for SGT MOSFETs, which are adequate for cir-cuit simulators, are necessary for the future use of these devices in integrated circuits. Circuit design requires a complete small-signal model, which consists of analytical expressions of transconductance and conductance (derived from a drain current expression) and also of the total capacitances.

In a previous work [6], a channel-current model, which is written in terms of the charge densities at the source and drain ends, was developed from a unified charge control model derived from the solution of one-dimensional (1-D) Poisson equation. In this brief, we present the development of analytical charge and capacitance models obtained from the unified charge control model. This results in a com-plete charge-based small-signal model. The charge and capacitance expressions are written in terms of explicit and infinitely continuous

Manuscript received May 9, 2006; revised October 11, 2006. This work was supported in part by the European Commission under Contract IST-506844 (“SINANO”) and Contract IST-506653 (“EUROSOI”), by the Ministerio de Ciencia y Tecnología under Projects TEC2005-06297/MIC, and by the Distinc-tion of the Catalan Government for the PromoDistinc-tion of University Research. The review of this brief was arranged by Editor S. Kimura.

O. Moldovan and B. Iñiguez are with the Departament d’ Enginyeria Elec-trònica, Elèctrica i Automàtica, Universitat Rovira i Virgili, 43007 Tarragona, Spain.

D. Jiménez is with the Departament d’ Enginyeria Electrònica, Escola Tècnica Superior d’ Enginyeria, Universitat Autònoma de Barcelona, 08193 Bellaterra, Spain.

J. Roig is with the Laboratoire d’Analyse et d’Architecture des Systèmes-Centre National de la Recherche Scientifique, 31077 Toulouse, France.

Color versions of one or more of the figures in this brief are available online at http://ieeexplore.ieee.org.