of CMOS ICs in a microelectronics system, the chips fabricated in the advanced CMOS processes face the gate-oxide reliability prob-lems in the interface circuits due to the voltage levels higher than normal supply voltage (1 VDD) required by earlier applications. As a result, mixed-voltage I/O circuits realized with only thin-oxide devices had been designed with advantages of less fabrication cost and higher operating speed to communicate with the circuits at different voltage levels. In this paper, two new mixed-voltage-tol-erant crystal oscillator circuits realized with low-voltage CMOS devices are proposed without suffering the gate-oxide reliability is-sues. The proposed mixed-voltage crystal oscillator circuits, which are one of the key I/O cells in a cell library, have been designed and verified in a 90-nm 1-V CMOS process, to serve 1-V/2-V tolerant mixed-voltage interface applications.
Index Terms—Crystal oscillator, gate-oxide reliability,
mixed-voltage I/O.
I. INTRODUCTION
W
ITH new generations of CMOS technologies, the de-vice dimension of transistors has been scaled toward the nanometer region to reduce the silicon cost as well as to increase circuit performance and operating speed. The power supply voltage of chips in the nanoscale CMOS process has been also decreased for low power consumption [1]. Therefore, the maximum tolerable voltage across the transistor terminals (i.e., drain, source, gate, and bulk) should be correspondingly decreased to ensure lifetime. The normal lifetime is typically years with continuous operation under specified worst case operating conditions. The circuits or transistors should be oper-ated correctly without function error or leakage issue at least for years under the normal power supply voltage (1 VDD). The shrunken device dimension, however, makes the chip area smaller to save silicon costs and the lower power supplyManuscript received September 19, 2008; revised December 24, 2008. First published February 24, 2009; current version published May 20, 2009. This work was supported in part by National Science Council (NSC), Taiwan, under Contract NSC 97-2221-E-009-170 and by Faraday Technology Corporation, Taiwan. This paper was recommended by Guest Editor W. A. Serdijn.
T.-M. Wang and H.-T. Liao are with the Nanoelectronics and Gigascale Systems Laboratory, Institute of Electronics, National Chiao-Tung University, Hsinchu 300, Taiwan.
M.-D. Ker is currently with the Department of Electronic Engineering, I-Shou University, Kaohsiung, Taiwan, on leave from the Nanoelectronics and Giga-scale Systems Laboratory, Institute of Electronics, National Chiao-Tung Uni-versity, Hsinchu 300, Taiwan (e-mail: mdker@ieee.org).
Digital Object Identifier 10.1109/TCSI.2009.2016172
some peripheral components or other ICs in a microelectronic system could be still operated at some higher voltage levels for compatibility to the earlier interface specifications. In other words, the interface circuits between two chips have to deal with the I/O signals at different voltage levels [2]–[4].
A complete I/O library includes the digital and analog I/O cells, power/ground cells, and crystal oscillator cells. The design of mixed-voltage I/O circuits has been discussed and reported in some literatures [5]–[8], but the mixed-voltage- tolerant crystal oscillator circuit was never mentioned before.
A conventional crystal oscillator circuit is connected with a crystal between the output (XO) pad and the input (XI) pad for oscillation to generate the stable clock signal for chip op-erations. In some applications, the clock signal will be directly provided from the external clock sources and sent into the chip through the input (XI) pad with the output (XO) pad floating. However, the conventional crystal oscillator circuit designed with 1 VDD CMOS devices is unsuitable to receive the ex-ternal clock signal with voltage level over VDD, due to the gate-oxide reliability issue [9], [10] and the hot-carrier degra-dation issue [11].
In this paper, two new 2 VDD-tolerant crystal oscillator circuits realized with only low-voltage (1 VDD) CMOS devices are proposed without suffering the gate-oxide reli-ability issue. The proposed mixed-voltage crystal oscillator circuits have been designed and verified in a 90-nm 1-V CMOS process to serve 1-V/2-V-tolerant mixed-voltage interface applications.
II. PIERCEOSCILLATOR
The theory and application of crystal oscillator circuits had been reported in [12]. The Pierce-type crystal oscillator cir-cuit is one of examples with source-grounded configuration for high-precision application. The conventional Pierce-type crystal oscillator circuit is shown in Fig. 1 [13], where the crystal is ex-pected to oscillate in parallel resonant mode.
The equivalent circuit of a crystal is shown in Fig. 2. is the effective series resistance in the crystal, and and are the motional inductance and capacitance of the crystal. is the parasitic shunt capacitance due to the electrodes. Fig. 3 shows the reactance-frequency plot of a crystal. When the crystal is operating at series resonance, it performs purely resistively, and the series resonance frequency is given by
(1) 1549-8328/$25.00 © 2009 IEEE
Fig. 1. Pierce-type crystal oscillator circuit.
Fig. 2. Equivalent circuit of a crystal.
Fig. 3. Reactance-frequency plot of a crystal.
When the crystal is operating in parallel resonant mode, it looks inductive and the frequency of oscillation is given by
(2)
where the is
(3) and is the stray capacitance on the printed circuit board. The crystal can be designed to oscillate between and by varying the load of the crystal.
Fig. 4. Conventional crystal oscillator circuit (realized with 12 VDD devices) suffering the gate-oxide reliability issue when it receives a 22 VDD external input clock signal.
III. GATE-OXIDERELIABILITYISSUE
In the advanced CMOS process, the devices with thinner gate oxide can be operated at a higher operating speed under a lower VDD supply voltage. The power supply voltage level has been decreased from higher voltage level (around 2-V or higher) to lower voltage level (around 1 V or below) to maintain the gate-oxide reliability and to overcome the hot-carrier degradation in ICs fabricated by 90-nm CMOS technology. However, other components on the printed circuit board or in the microelec-tronics system could be still operated at higher voltage level. Therefore, the I/O interface circuit should be designed for such mixed-voltage applications.
Fig. 4 shows the conventional crystal oscillator circuit realized with 1 VDD devices. When this circuit is uti-lized in the mixed-voltage I/O interface, it suffers from the gate-oxide reliability issues [6], [7]. When the EN signal is kept at VDD and the 2 VDD external input clock signal is received at the XI pad, the pull-up pMOS and pull-down nMOS (marked with circles in Fig. 4) suffer the gate-oxide overstress problem. In order to avoid the gate-oxide reliability issue, the devices which suffer the gate-oxide overstress could be replaced by the thick-oxide devices. However, with both of the thick-oxide and thin-oxide devices in a chip, the fabrication cost of CMOS process is increased. The circuit solution to solve such mixed-voltage (2 VDD-tolerant) applications with only thin-oxide (1 VDD) devices is highly requested by IC industry.
IV. NEWPROPOSEDMIXED-VOLTAGE-TOLERANTCRYSTAL OSCILLATORCIRCUITI
Fig. 5 shows the new proposed mixed-voltage-tolerant crystal oscillator circuit I realized with only thin gate-oxide (1 VDD) devices [14]. XI pad and XO pad are the input and output pads of the proposed circuit I with EN and PA signals controlled by the internal circuits of IC. XC is the clock signal sending to internal circuits, which is produced by crystal oscillator circuit or by the external clock signal. In this study, this XC signal is especially connected to a bond pad for monitoring/verifying its voltage
Fig. 5. New proposed mixed-voltage-tolerant crystal oscillator circuit I.
waveform. In order to solve gate-oxide reliability issue in re-ceiving mode, the conventional crystal oscillator circuit is mod-ified with upper and lower paths by adding some transmission gates to pass signal in receiving and oscillation mode, respec-tively. By nMOS-blocking [7] and level-restoring techniques, MN1 is added in the upper path before theNANDgate to solve gate-oxide reliability issue as well as MP4 is utilized to pull the N01 node to full VDD when the input signal is logic “1.” In the meanwhile, MP7 is added to keep the lower path from gate-oxide reliability issue. The detail operation is shown in the following.
A. Oscillation Mode
When the voltage level of PA is VDD, the proposed mixed-voltage-tolerant crystal oscillator circuit I is operated with crystal and two load capacitances to generate the sinu-soidal-wave signal at both XI and XO pads. In this operating condition, transmission gates TRAN1 and TRAN2 are turned off, as well as TRAN3 and TRAN4 are turned on, so that the sinusoidal-wave signal can only pass through the lower path of this circuit from XI pad to XO pad. In the upper path, in order to keep the output terminal of the upper NAND gate at VDD, MN4 is turned on to keep MN2 off and MP3 on. Besides, the gate terminal of MP4 is directly connected to the output terminal of the upper NAND gate, so MP4 is turned off. The input node (N01) of the upperNANDgate will follow the voltage level of XI pad, while the output node of upperNAND gate keeps at VDD. The signal EN can be transmitted to one input node of the lower NANDgate to enable
or disable the lower NANDgate. In the lower path, MN7 and MP7 are turned off while the gate terminals of MN6 and MP6 are connected to VDD, so the generated
sinusoidal-wave signal will pass through the lower path of this circuit from XI pad to XO pad.
B. Receiving Mode
When the voltage level of PA signal is GND, the proposed mixed-voltage-tolerant crystal oscillator circuit I is operated to receive an external clock input signal whose voltage level could be 1 VDD or 2 VDD. TRAN1 and TRAN2 are turned on and the external clock signal passes through the upper path from XI pad to XC. In the upper path, MN4 is turned off, as well as MN1 and MP4 with upper NANDgate are used to transfer the external clock signal from the XI pad to the XO pad. MN1 is used to limit the voltage level of external clock input signal reaching to the gate oxide of the upperNANDgate. Because the gate terminal of MN1 is connected to the power supply voltage (VDD), the input (N01) voltage of the upperNANDgate is lim-ited to VDD-Vt when the voltage level of external clock signal is even up to 2 VDD. Then, transistor MP4 further pulls the input node (N01) of the upperNANDgate up to VDD, when the output node of the upperNANDgate is pulled down near to GND. The external clock signal can be successfully transferred into the internal input node XC. Meanwhile, TRAN3 and TRAN4 are turned off. MN7 is turned on to keep MN6 off and MP6 on in order to keep the output terminal of the lowerNANDgate at VDD.
MP7 is also turned on to keep the node between MN5 and MN6 at VDD. Thus, when the XI pad is with the input signal voltage level of 2 VDD, any voltage drop between the gate ter-minal and source/drain terter-minal of MN5 and MP5 is still limited to VDD. Therefore, the new proposed crystal oscillator circuit I can receive the external clock signal of 2 VDD without suf-fering the gate-oxide overstress issue.
Fig. 6. Simulated waveforms of the new proposed crystal oscillator circuit I with (a) a crystal of 20-MHz fundamental frequency and load capacitance of 20 pF(PA = VDD) and (b) 20-MHz external clock signal with voltage level of 22 VDD into XI pad (PA = GND).
C. Simulations
Fig. 6 shows the simulated waveforms of the proposed mixed-voltage-tolerant crystal oscillator circuit I in a 90-nm 1-V CMOS process to serve 1-V/2-V-tolerant mixed-voltage interface. In Fig. 6(a), the proposed mixed-voltage crystal oscillator circuit I with the crystal of 20-MHz fundamental frequency and a load capacitance of 20 pF at the pad can suc-cessfully generate the clock signal of 20 MHz at the XC node under the power supply of 1 VDD. As shown in Fig. 6(b), with the 20-MHz external clock signal of 2 VDD into XI pad, the input (N01) voltage of the upper NAND gate can be limited and biased at the desired voltage level (1 V). The final signal voltage level reaching to the XC node is successfully shifted down to 1 VDD. In addition, the power consumption in the oscillation mode with 20-MHz fundamental frequency is 0.46 mW, whereas the power consumption is 0.42 mW in the receiving mode with 20-MHz external clock signal of 2 VDD. From the simulated results, the desired functions of this mixed-voltage-tolerant crystal oscillator circuit I have been verified without suffering the gate-oxide reliability issue. D. Layout
Fig. 7 shows the layout view of the proposed mixed-voltage-tolerant crystal oscillator circuit I implemented in a 90-nm CMOS process. The cell size of XI, as well as XO, is only
Fig. 7. Layout view of new proposed mixed-voltage-tolerant crystal oscillator circuit I in a 90-nm CMOS process.
Fig. 8. Measurement setups for (a) the oscillation mode and (b) the receiving mode.
190.5 m 60 m (including the bond pad), which is the same as that of digital and analog I/O cells in a given standard I/O cell library. Feedback resistance is also included and implemented by the poly resistance in the cell.
E. Measured Results
The measurement setups for oscillation mode and re-ceiving mode are shown in Fig. 8(a) and (b), respectively. Agilent 86100C is utilized to measure jitter performance, TEK TDS3054 can observe the output waveforms, and Agilent 81110A is used to generate the external clock signal. The measured voltage waveforms of the new proposed mixed-voltage-tolerant crystal oscillator circuit I, which has been fabricated in a 90-nm CMOS process, in the oscillation mode with 4-MHz and 20-MHz crystals are shown in Fig. 9(a) and (b), respectively. As shown in Fig. 9, the clock signals of 4 and 20 MHz can be successfully generated at the XC node by the sinusoidal voltage waveforms at the XO pad. The degraded voltage waveforms measured at XI, XO, and XC nodes are due to the large parasitic capacitive loading at the bond pad with on-chip ESD protection device and the limited output driving capability of circuit in the test chip.
The voltage waveforms of the new proposed mixed-voltage-tolerant crystal oscillator circuit I operating in the receiving mode with the external 4-MHz input clock signals of 0–1 V and 0–2 V are measured in Fig. 10(a) and (b), respectively. Fig. 11 shows the measured voltage waveforms of the proposed circuit I operated in the receiving mode with the external 20-MHz input clock signals of 0–1 V and 0–2 V. As shown in Figs. 10 and 11, the input clock signals can be correctly received and shifted to
Fig. 9. Measured voltage waveforms of the new proposed mixed-voltage-tol-erant crystal oscillator circuit I with a crystal of fundamental frequency at (a) 4 MHz and (b) 20 MHz.
Fig. 10. Measured voltage waveforms of the new proposed mixed-voltage-tol-erant crystal oscillator circuit I with a 4-MHz external input clock signal under the voltage levels of (a) 0-to-1 V and (b) 0-to-2 V.
Fig. 11. Measured voltage waveforms of the new proposed mixed-voltage-tol-erant crystal oscillator circuit I with a 20-MHz external input clock signal under the voltage levels of (a) 0-to-1 V and (b) 0-to-2 V.
the 0–1-V signal at the XC node. Fig. 12 shows the jitter perfor-mance of the proposed circuit I in oscillation mode at 20 MHz, where the standard deviation (std dev) and peak-to-peak (p-p) jitter are 358 ps and 3.83 ns in this measurement. Fig. 13 shows the jitter performance of the proposed circuit I in receiving mode with 20-MHz external clock signal of 2 VDD, where the stan-dard deviation and peak-to-peak jitter are 265 ps and 2.2 ns. From the measured results, the new proposed mixed-voltage-tolerant crystal oscillator circuit I can be operated correctly.
Fig. 12. Measured jitter of the new proposed mixed-voltage-tolerant crystal oscillator circuit I with a crystal of fundamental frequency at 20 MHz.
Fig. 13. Measured jitter of the new proposed mixed-voltage-tolerant crystal oscillator circuit I with a 20-MHz external input clock signal under the voltage level of 0-to-2 V.
V. NEWPROPOSEDMIXED-VOLTAGETOLERANTCRYSTAL OSCILLATORCIRCUITII
Fig. 14 shows anther new proposed 2 VDD-tolerant crystal oscillator circuit II realized with only 1 VDD thin-oxide de-vices [15]. Compared with the proposed circuit I, the signal PA is no longer needed. XI and XO pads are the input and output pads of the proposed circuit, respectively. Signal EN is con-trolled by the internal circuits of IC, and XC is the clock signal which is produced by crystal oscillator circuit or received from the external clock signal. The transistors MN2, MN3, MP2, and MP3 form the inverting amplifier of the proposed circuit. Inverters INV4 and INV5 can transform the sinusoidal-wave signal to a square signal or to pass the external clock signal into the internal node XC.
Compared with the proposed circuit I, the proposed circuit II solves the gate-oxide reliability issue with only single path and no additional control signal PA is needed. In order to combine the two paths of the proposed circuit I into single one, floating N-well technique [5] is applied to keep MN1 and MP1 from gate-oxide reliability issue and some extra devices are utilized to
Fig. 14. New proposed mixed-voltage-tolerant crystal oscillator circuit II.
make N01 and FNW biased at proper voltage levels. The detail operation is described in the following.
A. Oscillation Mode
It is operated to generate the sinusoidal-wave signal, when the proposed circuit II is connected with crystal and two load capacitances ( and at XI and XO pads. MP4 and MP5 are turned off while MN4 is turned on with the gate terminal connected to power supply (VDD). The sinusoidal-wave signal with voltage level less than VDD-Vt at XI pad can pass through the transistor MN1 to the input (N01) of the NAND gate, when oscillation starts up. When the input node (N01) of the inverter INV1 is with a low voltage level ( V), MN5 is turned on to bias the gate terminal of MP1 at GND, and the inverters INV2 and INV3 hold this voltage level by a latch configuration. The si-nusoidal-wave signal, even if the voltage level is over VDD-Vt, can pass through the transistor MP1 to N01. Therefore, the si-nusoidal-wave signal can completely pass through the MN1 and MP1 to the input terminal of theNANDgate without distortion. Moreover, MP6 is turned on to bias the floating N-well (FNW) at VDD.
B. Receiving Mode
For the mixed-voltage interface applications, the proposed circuit II may receive an external input clock signal with voltage level of 1 VDD or 2 VDD. In order to limit the voltage level of input clock signal reaching to the gate oxide of theNANDgate, MP4 is utilized to trace the signal at the XI pad and control the gate voltage of transistor MP1. When the voltage level at the XI pad exceeds , MP4 is turned on to charge the gate terminal of MP1 up to 2 VDD. MP1 is completely turned off to prevent the voltage level at the input node (N01) of theNAND gate from rising up to 2 VDD.
With the input voltage of 2 VDD at XI pad, MP5 is turned on and MP6 is turned off to bias the floating N-well (FNW) at 2 VDD. Besides, when the voltage level of XI pad is at GND, MN5 will be turned on by the inverter INV1, and further to turn on the MP1. With the input signal of 0 V at XI pad, MP5 is turned off and MP6 is turned on to bias the floating N-well (FNW) at VDD.
Fig. 15. Simulated waveforms of the new proposed mixed-voltage-tolerant crystal oscillator circuit II with (a) a crystal of 20-MHz fundamental frequency and load capacitance of 20 pF at the XI and XO pads and (b) 20-MHz external input clock signal with voltage level of 22 VDD into XI pad.
C. Simulations
Fig. 15 show the simulated waveform of the proposed mixed-voltage-tolerant crystal oscillator circuit II in a 90-nm 1-V CMOS process to serve 1/2-V mixed-voltage interface. In Fig. 15(a), the proposed circuit II with the crystal of 20-MHz fundamental frequency and 20-pF load capacitance at the XI and XO pads can successfully generate the clock signal of 20 MHz at the XC node under the power supply of 1 VDD.
Fig. 16. (a) Layout view and (b) die photograph of the proposed mixed-voltage-tolerant crystal oscillator circuit II realized in a 90-nm CMOS process.
As shown in Fig. 15(b), with the 20-MHz external clock signal of 2 VDD at XI pad, the input node (N01) of theNANDgate can be limited to the voltage level of V. The final signal voltage level reaching to the XC node is successfully shifted down to 1 VDD. In addition, FNW is biased at 1 VDD in oscillation mode, at 2 VDD in receiving mode when the XI pad is 2 VDD, and at 1 VDD in receiving mode when the XI pad is 0 V. By simulation, the power consumption in the oscillation mode with 20-MHz fundamental frequency is 1.1 mW. The power consumption is 0.26 mW in the receiving mode with 20-MHz external input clock signal of 2 VDD. From the simulated results, the desired functions of the pro-posed mixed-voltage-tolerant crystal oscillator circuit II have been verified.
D. Experimental Results
The layout view and die photograph of the mixed-voltage-tol-erant crystal oscillator circuit II implemented in a 90-nm 1-V CMOS process are shown in Fig. 16(a) and (b), respectively. The cell size is only 190.5 m 60 m (including the bond pad), which is the same as that of digital and analog I/O cells in a standard I/O cell library. The feedback resistance , im-plemented by the poly resistance, is also included in the layout. ESD protection is also provided by following the foundry ESD design rules to draw the nMOS and pMOS devices which are directly connected to the pads.
The measured results of the new proposed mixed-voltage- tol-erant crystal oscillator circuit II in oscillation mode are shown in Fig. 17. In Fig. 17(a) and (b), the new proposed circuit II can suc-cessfully transmit the 0-/1-V sinusoidal-wave signal with fre-quency of 4 MHz and 20 MHz to the XC node, respectively. The measured results of the new proposed circuit II in the re-ceiving mode are shown in Figs. 18 and 19 under the operating
Fig. 17. Measured voltage waveforms of the new proposed mixed-voltage-tol-erant crystal oscillator circuit II with crystal fundamental frequency at (a) 4 MHz and (b) 20 MHz.
Fig. 18. Measured voltage waveforms of the new proposed mixed-voltage-tol-erant crystal oscillator circuit II with a 4-MHz external input clock signal under the voltage levels of (a) 0-to-1 V and (b) 0-to-2 V.
Fig. 19. Measured voltage waveforms of the new proposed mixed-voltage-tol-erant crystal oscillator circuit II with a 20-MHz external input clock signal under the voltage levels of (a) 0-to-1 V and (b) 0-to-2 V.
frequency of 4 MHz and 20 MHz, respectively. The new pro-posed circuit II can successfully transmit the 0-/1-V external input clock signal to the XC node with the input voltage levels of 0–1 V or 0–2 V.
Fig. 20 shows the measured jitter performance of the pro-posed circuit II in oscillation mode with the crystal fundamental frequency at 20 MHz. The standard deviation and peak-to-peak
Fig. 20. Measured jitter of the new proposed mixed-voltage-tolerant crystal oscillator circuit II with the crystal fundamental frequency at 20 MHz.
Fig. 21. Measured jitter of the new proposed mixed-voltage-tolerant crystal oscillator circuit II, when a 20-MHz external input clock signal is applied with the voltage level of 0-to-2 V.
jitter are 392 ps and 4.19 ns, respectively. Fig. 21 shows the mea-sured jitter performance of the proposed circuit II in receiving mode with the 20-MHz external input clock signal of 2 VDD. The standard deviation and peak-to-peak jitter are 231 ps and 2.7 ns in Fig. 21. The degraded voltage waveforms measured at XI, XO, and XC nodes are due to the large parasitic capacitive loading at the bond pads with on-chip ESD protection devices and the limited driving capability of the output transistors in the test chip. To improve the circuit performance in the high-fre-quency measurement, additional buffers should be added be-tween the XC node and the bond pad.
VI. COMPARISON ANDDISCUSSION
Table I shows the comparison between the two proposed cir-cuits. The proposed circuit I has 27 transistors with additional signal PA. The proposed circuit II has 21 transistors with FNW technique. In the oscillation (Osc.) mode, the sinusoidal-wave at the N01 node of circuit II has higher power consumption due to the short circuit current of theNAND gate. These two pro-posed circuits in the receiving (Rec.) mode have better jitter per-formance than those in oscillation mode, because the external
clock signal is generated by pulse generator during the measure-ment. Compared with some earlier works [16], [17], the jitter performance of those earlier circuits is better than that of this work. However, the main contribution of the proposed circuits in this work is to solve the gate-oxide reliability issue in the mixed-voltage I/O applications with low-voltage devices. Fur-ther optimization on this work to get a better jitter performance should be involved when such a design is applied for high-pre-cision applications.
In an SoC chip, there are often many building blocks working with different VDD voltage levels, such as the digital part is typically supplied with 1-V VDD and the analog part is sup-plied with 2.5-V VDD in a given 90-nm CMOS process. More-over, the I/O circuits are often requested to be tolerant to signal voltage level of 3.3 V (or even up to 5 V). To support such SoC applications with different signal voltage levels, the semicon-ductor foundry has provided the transistors with multiple gate-oxide thickness by adding the corresponding additional mask layers into the CMOS process flow. However, the increase of mask layers also causes the increase on the fabrication cost of a chip. The more process steps corresponding to the increased mask layers also cause some yield loss due to the increased op-portunity to defect or particle pollution during wafer fabrication, which will in turn increase the fabrication cost of a chip. There-fore, some circuit solutions have been strongly requested by IC design houses to use the low-VDD devices for high-VDD-tol-erant circuit applications. Typically, the mixed-voltage I/O cir-cuits realized with only low-VDD devices have been widely used in IC industry [5]. Moreover, the analog circuits were also designed with only low-VDD devices for high-voltage-tolerant applications to save chip fabrication cost [18].
In this study, two 2 VDD-tolerant crystal oscillator cir-cuits have been realized with only 1 VDD devices in a 90-nm CMOS process. With the circuit design skill of NMOS-blocking technique [7], even a 3 VDD-tolerant crystal oscillator circuit can be further developed and realized with only 1 VDD devices.
VII. CONCLUSION
Two new mixed-voltage-tolerant crystal oscillator circuits re-alized with low-voltage CMOS devices have been proposed and successfully verified in a 90-nm CMOS process, which can be operated correctly without suffering gate-oxide reliability issue in the mixed-voltage interface applications. This circuit design solution can be extended to other different mixed-voltage in-terfaces for chip fabrication in the advanced nanoscale CMOS processes.
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the Ph.D. degree from the Institute of Electronics, National Chiao-Tung University, Hsinchu, Taiwan, in 1993.
From 1994 to 1999, he was with the VLSI Design Division, Computer and Communication Research Laboratories, Industrial Technology Research In-stitute (ITRI), Hsinchu. Since 2004, he has been a Full Professor with the Department of Electronics Engineering and Institute of Electronics, National Chiao-Tung University. From 2006 to 2008, he served as the Director of Master Degree Program in the College of Electrical Engineering and Computer Science, National Chiao-Tung University, as well as the Associate Executive Director of the National Science and Technology Program on System-on-Chip, Taiwan. In 2008, he was rotated to be a Chair Professor and Vice President of I-Shou University, Kaohsiung, Taiwan. In the field of reliability and quality design for circuits and systems in CMOS tech-nology, he has published over 360 technical papers in international journals and conferences. He has proposed many inventions to improve the reliability and quality of integrated circuits, which have been granted with 140 U.S. patents and 144 R.O.C. (Taiwan) patents. His current research interests include relia-bility and quality design for nanoelectronics and gigascale systems, high-speed and mixed-voltage I/O interface circuits, on-glass circuits for system-on-panel applications, and biomimetic circuits and systems for intelligent prosthesis. He has been invited to teach or to consult reliability and quality design for integrated circuits by hundreds of design houses and semiconductor companies in the worldwide IC Industry.
Prof. Ker has served as the member of Technical Program Committees and the Session Chair of numerous international conferences. He served as the Asso-ciate Editor for the IEEE TRANSACTIONS ONVERYLARGESCALEINTEGRATION
(VLSI) SYSTEMS. He was selected as the Distinguished Lecturer of the IEEE Circuits and Systems Society (2006–2007) and the IEEE Electron Devices So-ciety (2008–2009). He was the President of Foundation in Taiwan ESD Associ-ation. In 2009, he was selected as one of the top ten Distinguished Inventors in Taiwan and one of the Top Hundred Distinguished Inventors in China. In 2008, he was elected to be an IEEE Fellow with the citation of for contributions to electrostatic protection in integrated circuits, and performance optimization of VLSI micro-systems.
Hung-Tai Liao was born in Taiwan in 1982. He
received the M.S. degree in electronics engineering from National Chiao-Tung University, Hsinchu, Taiwan, in 2005.
He is now a Design Engineer with Amazing Mi-croelectronic Corporation, Hsinchu, where he is re-sponsible for IC design and IO library establishment.
