established in this paper. The core of this method relies on the con-stant mobility criteria, while for different gate lengths, it preserves the shape of universal mobility curves in the high-vertical-field regime. Consequently, the series resistance of a MOSFET can be extracted in an analytical and self-consistent manner, achieved without the knowledge of the gate oxide thickness, channel length, channel doping, or channel stress. Reasonable values of extracted series resistance are demonstrated in a wide range of gate length. Technology computer-aided design simulation further corrobo-rates the validity of the proposed method, particularly for devices with heavily doped source/drain extensions. The constant mobility criteria with respect to the bulk charge linearization coefficient are also verified.
Index Terms—MOSFET, series resistance, universal mobility. I. INTRODUCTION
M
OSFET series resistance (Rsd), as shown in Fig. 1, leads to a voltage drop within source and drain diffusion regions, reducing the voltage across the intrinsic device and degrading drive capability. It constitutes an increasing portion of total resistance as gate length(Lgate) shrinks due to reducedintrinsic channel resistance. Hence, the degradation of drive current becomes most serious in short-channel devices. In inte-grated circuit technology development,Rsdextraction remains
one of the most critical tasks during device characterization and simulation. ManyRsdextraction methods [1]–[3] have one
assumption in common: both the channel dopant concentration and carrier mobility are independent of Lgate. However, the
significance of the halo ion implantation and mechanical-stress-dependent dopant diffusion [4], as encountered in modern MOSFETs, renders this model inadequate. Recently, a constant mobility criterion in the high-surface-electrical-field regime
Manuscript received November 30, 2009. First published March 1, 2010; current version published April 2, 2010. This work was supported by the National Science Council of Taiwan, under Contract NSC 98-2221-E-009-164-MY3. The review of this paper was arranged by Editor C. McAndrew.
D.-W. Lin is with the Taiwan Semiconductor Manufacturing Company, Hsinchu 300, Taiwan, and also with the Department of Electronics Engineering, National Chiao Tung University, Hsinchu 30010, Taiwan (e-mail: dwlin@ tsmc.com).
M.-L. Cheng, S.-W. Wang, and C.-C. Wu are with the Taiwan Semiconductor Manufacturing Company, Hsinchu 300, Taiwan.
M.-J. Chen is with the Department of Electronics Engineering, National Chiao Tung University, Hsinchu 30010, Taiwan.
Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TED.2010.2041508
Fig. 1. Schematic of the equivalent circuit of the device used in Rsd extraction.
was proposed [5], which can not only considerably improve
Rsd extraction precision but also eliminate the disadvantages
of conventional methods [1], [2], [6] such as requiring multi-ple I–V measurements over different channel lengths and/or sophisticatedC–V measurements for short-channel devices.
Contrary to the drain current model used in the literature [1]–[3], [5], [6], a bulk charge linearization coefficient (α) is adopted in this paper. This leads to a cancellation of the debiasing effect and the threshold voltage change induced by
IR drop. Hence, an exact and compact drain current
formu-lation results. In addition, a self-consistent algorithm is estab-lished by combining the constant mobility criterion [5] and an updated method of effective surface electrical field (Eeff)
extraction. In contrast to [5], which uses a constant η in the analytic expression of Eeff, this empirical factor is treated as
a fitting parameter(ηana) in this work. The values of Rsdand
ηanaare determined by using an iterative procedure. With the
constant mobility criterion taken into account, theRsdcan be
more accurately extracted for a certain short-channel device by matching the shape of its universal mobility curve with that of a long-channel device. The procedure is conducted without requiring knowledge of the effective channel length (Leff),
substrate doping concentration(Nsub), or channel stress. With
this unique feature in mind, the proposed method is particularly suitable for the short-channel devices for which unambiguous definition ofLeff is often hard to make. Reasonable values of
extractedRsdare successfully demonstrated in a wide range of
gate lengths. The validity of the constant mobility criterion is addressed as well.
The device samples used in this work are fabricated using the 40-nm low-power process technology of Taiwan Semiconduc-tor Manufacturing Company. This technology features abrupt and heavily doped ultra shallow junction for source/drain exten-sions (SDEs). Millisecond annealing is implemented to enhance
Fig. 2. Measured inversion carrier mobility (μ) versus effective surface electric field(Eeff) under different Vbs bias conditions of a long-channel NMOSFET. The inversion carrier mobility converges to the same trend when Eeff is sufficiently high. The curve of “best fitting” is obtained withμ0= 720 cm2/V · s, E
0= 0.82 MV/cm, and ν = 1.63 for the long-channel device used in this work.
the dopant activation level. Aggressive strain engineering is used to boost device performance.
II. UNIVERSALMOBILITY ANDANALYTICEeff WITHηana
AS AFITTINGPARAMETER
The universality of carrier mobility in the high-electrical-field regime is demonstrated in Fig. 2 for a long-channel MOSFET. The effective silicon vertical electrical field (Eeff)
at the SiO2/Si interface can be expressed as a function of the
depletion charge (Qd) and inversion layer charge (Qi). The
charge componentsQdandQi can be obtained via splitC–V
measurements [7], [8]. TheEeff formula can read as
Eeff_CV =
1
εSi
(|Qd| + η|Qi|) (1)
whereεSiis the silicon permittivity, andη is an empirical factor
with common values of∼1/2 and ∼1/3 for electrons and holes at room temperature, respectively [9]–[13]. Note that in this paper, η, which is the reciprocal of that in [5], follows the convention in existing publications [9]–[13]. In order to obtain accurate carrier mobility, split C–V and I–V measurements are performed on a long-channel MOSFET in which fringing capacitance and Rsd are insignificant as compared with
in-trinsic gate capacitance and channel resistance, respectively. As shown in Fig. 2, under various back bias(Vbs) conditions,
carrier mobility appears to converge toward a universal mobility (μuniversal) curve in the high-Eeff region. This means that if the
device is operated in the high-Eeff region, a constant mobility
is achieved at a givenEeff, regardless of the varying impurity
scattering element. At sufficiently highEeff, carrier mobility is
well described by [14]–[16]
μuniversal= μ0
1+ (Eeff/E0)ν
(2) whereμ0,E0, andν are process-specific constants. Best fitting
result, also shown in Fig. 2, is obtained withμ0=720 cm2/V·s,
Fig. 3. Comparison between the effective surface electric field obtained from analytical equation(Eeff_ana) and split C–V measurement (Eeff_CV).
ηana= 1/1.7 provides the best fitting result.
E0= 0.82 MV/cm, and ν = 1.63 for the long-channel device
used in this work.
To further investigate (1), it is transformed into the following analytical form: Eeff_ana= Vgs+ 1 ηana−1 Vth−ηana1 VFB−ηana2 ψB 3 ηanaTOX . (3)
The parameters associated with (3) have the usual meanings [5]. The threshold voltageVthin (3) is extracted using a maximum
transconductance method under a low drain bias (25 mV), ensuring a linear operation mode. In the derivation of (3), a constant Nsub is presumed. However, aggressive engineering
of channel doping profile, such as retrograded channel and/or heavy halo ion implantation, is commonly used in modern MOSFETs. In addition, a nonuniform doping profile caused by mechanical-stress-dependent diffusion is also evident. These factors make the constantNsubassumption problematic, and a
specific treatment is needed.
In this paper,ηanain the analytic expression (3) is treated as a
fitting parameter in order to accommodate the error introduced by the constantNsubassumption, as mentioned above. Similar
to the method described in [15], the Eeff_ana values acquired
through (3) are compared to those of split C–V method. A long-channel NMOSFET (Lmask= Wmask= 1 μm) is used
to examine the consistency between the two methods. One should note that the value ofη used for split C–V is set at 1/2 for NMOSFETs fabricated on wafers with (100) surface ori-entation. As shown in Fig. 3, in order to match the Eeff
values between both methods, ηana= 1/1.7, instead of 1/2, is
suggested when applying the analytic expression (3).
III. METHODOLOGY OFRsdEXTRACTION: CONSTANTMOBILITYCRITERION
The Rsd extraction method based on a constant mobility
criterion is first described in [5]. Here, to testify to the validity of the constant mobility criterion, an extra parameter is intro-duced: the bulk charge linearization coefficient denoted as α.
Id=CoxLWeffμ eff Vgs−Rsd 2 Id − Vth+ (α − 1)Rsd 2 Id −α 2(Vds− RsdId) (Vds− RsdId) =CoxWeffμ Leff Vgs− Vth−α 2Vds (Vds− RsdId). (5)
The above derivation process clearly demonstrates that cancel-lation of the debiasing effect and the threshold voltage change induced by IR drop takes place. As a result, the term in the first parentheses of (5) reduces to(Vgs− Vth− αVds/2),
thus constituting an exact and simple formulation for the drain current. By incorporating the criterion described in [5], a con-stant mobility can be achieved at the following two sets of bias conditions: 1) (Vgs(1), Vth(1)) and 2) (V
(2)
gs , Vth(2)), where
V(2)
gs = Vgs(1)+ (1/ηana− 1)(Vth(1)− V (2)
th ). Again, using the
same derivation procedure in [5] with the incorporation ofα, series resistance can be written as
Rsd= B I(2) d − A I(1) d ηanaVds V(1) th − V (2) th (6)
whereA=Vgs(1)−Vth(1)−0.5αVds, andB =Vgs(1)+(1/ηana−1)
V(1) th − V
(2)
th /ηana− 0.5αVds.
The expression ofRsdin (6) shows no dependency onCox,
Leff, andWeff. Therefore, this method is particularly suitable
for modern MOSFETs with small geometries in which accurate measurements ofCox,Leff, andWeff are hard to achieve.
For a modern MOSFET with thin gate oxide,α is close to 1, as will be explained later. In the following discussion, α is presumed as 1, and the error caused by this assumption will be further examined.
IV. ALGORITHM OFSELF-CONSISTENTRsd
ANDηanaCALCULATION
As device feature size shrinks, fringing capacitance andRsd
become no longer negligible. It is difficult to extract carrier mobility andEeff_CV by using simple splitC–V and I–V
mea-surements. Thus, at small feature sizes, analytical derivations forμ and Eeff become necessary. OnceRsdhas been extracted
Fig. 4. (a) Fitting parameterμ0 dominating the magnitude ofμuniversal versusEeffbehavior. (b) Fitting parameterηanadominating the slope ofμana versusEeffbehavior.
by using (6), an analytical expression of mobilityμanacan be
written as μana= WLeff effCox Id Vgs− Vth−α2Vds (Vds− RsdId) . (7)
BecauseRsdis a function ofηana, as described in (6),μanais
consequently also a function ofηana. For a givenηana,
corre-sponding Eeff_ana, Rsd, and μana are generated analytically.
Moreover, a series of Eeff_ana and μana can be defined for
bias conditions in the vicinity of the specific Vgs, whereRsd
is extracted. It is worth noting that Vgsshould be sufficiently
high, as mentioned in Section III. In a sense,Vgsof∼2.5 V is
typically used in this work.
Process-induced strain and intensive strain engineering are pervasive in modern MOSFETs. These may lead to signifi-cant variability in carrier mobility [19]–[22] and changes to
μ − Eeff behavior. The difference in μ − Eeff behavior in a
high-Eeff regime between strained and unstrained MOSFETs
approaches a constant ratio, as mentioned in the literature [16], [23]–[25]. This implies that only μ0 in (2) is sensitive
to strain engineering in the high-Eeff regime. Consequently,
theμ − Eeff behavior in the high-Eeff regime extracted using
long-channel MOSFETs is valid for shorter channel devices by simply modifying it with a constant ratio. μ0 is therefore
regarded as a fitting parameter for shorter channel MOSFETs in this work. In addition, determining Leff for short-channel
MOSFETs remains one of the most challenging issues in the industry. Without explicitly assigning a value to Leff, mask
Fig. 5. (a) Self-consistent method ofRsdextraction using bothμ0andηanaas fitting parameters in order to minimize the difference betweenμuniversaland μana. (b) Summation of(μana− μuniversal)2over a wide range ofE
effin the vicinity ofVgs, whereRsdis extracted. NMOSFET with 0.5μm Lmaskis used as an example.ηana= 1/1.7 provides the lowest error.
length (Lmask) is used in this work. The difference between
Lmask and Leff of a given short-channel MOSFETs is also
absorbed byμ0. As shown in (6), no information aboutLeff
is necessary for Rsd extraction, as mentioned in Section III.
Therefore, the ambiguous definition of Leff does not lead to
erroneousRsd extraction [5]. In the vicinity of theVgswhere
Rsd is extracted,μ0 is a fitting parameter accounting for the
difference introduced by long- to short-channel mobility shifts as well as the constant ratio betweenLeffandLmaskof a given
shorter channel MOSFET. As shown in Fig. 4(a) and (b), μ0
dominates the magnitude ofμuniversal− Eeff behavior, while
ηana changes the slope of μana− Eeff for a shorter channel
device in which significant effects from strain engineering may take place. The most important task in this work is to determine a set ofηanaandμ0that minimizes the difference betweenμana
andμuniversal.
An iterative method to determineRsd,ηanaandμ0is detailed
in Fig. 5(a). For a givenηana, the summation of the square of
the difference between μana andμuniversal at each Eeff with
modified μ0 is plotted in Fig. 5(b). By using the MOSFET
with a 0.5-μm gate length as an example, it is obvious that a minimum exists at ηana= 1/1.7 (∼0.59). This is consistent
with the value obtained in Section II, which exhibits a good correlation betweenEeff_CV andEeff_ana. For state-of-the-art
MOSFETs, localized doping profiles introduced by halo ion implantation from both source and drain sides are not strongly
overlapped for a gate length longer than 100 nm. As a result, the substrate doping profile should not change significantly for the MOSFETs with a gate length longer than 100 nm. A consistent value of ηana is therefore extracted by using the
analytical method described in Section II and by using the iteration introduced in this section for devices having similar substrate doping profiles.
V. EXPERIMENTALRESULTS
The algorithm introduced in Section IV has been applied to a series of test devices, and the extractedRsdvalues are shown in
Fig. 6(a). SimilarRsdvalues are observed for long- and
short-channel devices. This result is expected because all devices are located on a single wafer and share the same process conditions. As also shown in Fig. 6(a),μ0increases asLmaskshrinks from
1 μm and reaches a peak at 0.1 ∼ 0.2 μm. Below 0.1 μm, μ0
decreases. This implies that the effects of strain engineering in these devices are more pronounced at Lmaskvalues around
0.1∼ 0.2 μm. The root cause of the decreasing μ0needs more
theoretical study.
The gate length dependency of ηana is shown in Fig. 6(b).
It stays at a constant value for gate lengths longer than 0.1μm and starts to roll off gradually for shorter gate lengths. As gate length shrinks, substrate doping concentration changes because of overlap of halo ion implantation from the source
Fig. 6. (a)Rsd andμ0extracted using the method proposed in this paper. SimilarRsdvalues are extracted over a wide range ofLmask.μ0increases fromLmask= 1 μm down to Lmask∼ 0.1 um and then decreases toward the short-channel regime. (b) Extractedηana−Lmaskbehavior.ηanakeeps at a constant level for long-channel devices and then decreases forLmaskshorter than 0.1μm.
and drain sides. Consequently, the value ofηanamay deviate
from that of the long-channel devices. In addition,ηanaitself is
also a function of subband occupancy [26]. When gate length shrinks, 2-D charge sharing from source and drain junctions leads to a reduction in charge confinement in the channel region [27], [28]. This reduction in confinement reduces the subband separation. As a result, η decreases due to higher probability of carriers occupying high-level subbands [26]. The trend of decreasingηanawith decreasing gate length supports
this argument.
In this section, a self-consistent algorithm has been suc-cessfully demonstrated for the extraction of Rsd from
long-channel to sub-100-nm devices. The extractedRsdshows weak
dependency on gate length. The reason for the gate length dependence of each parameter has also been proposed and discussed. This algorithm can easily be implemented with aforementioned analytical equations, and no C–V measure-ment for short-channel devices is required. These features avoid unnecessary error caused by fringing capacitance and therefore result in an accurately extractedRsd.
VI. DISCUSSION
A. Technology Computer-Aided Design (TCAD) as Corroborating Evidence
Based on calibrated TSUPREM and Medici [29] (also used in [4] and [5]), the net doping concentration near the gate
Fig. 7. (a) TSUPREM-4 simulated 2-D doping concentration in the vicinity of gate edge of the NMOSFET used in this work. (b) Carrier concentration on the drain side along the horizontal direction(A−A), as shown in Fig. 7(a), under variousVgsconditions.Vgsshows little effect on modulating the carrier concentration inside source/drain extension regions. The inset table provides an example of TCAD-simulatedRsdvalues based on the potential drop between two characteristic points on the drain and the source sides of a 0.1-μm-Lmask MOSFET. TheRsdvalues are reasonably consistent with the extracted ones shown in Section V. (c) Carrier concentration along the vertical direction (B−B), as shown in Fig. 7(a), under various Vbsconditions. The current flow in the source/drain extension is mainly located in a region where the carrier concentration is insensitive toVbs.
edge of a typical NMOSFET (Lmask= 0.1 μm) used in this
work is shown in Fig. 7(a). In a state-of-the-art MOSFET, the doping concentration inside the SDE region is higher than 1020 cm−3. It takes only several nanometers to change the doping polarity in the transition region from SDE to channel
(lateral transition) and SDE to substrate (vertical transition). Fig. 7(b) illustrates the electron concentration on the drain side along the lateral direction A−A defined in Fig. 7(a). Over a wide range of bias conditions, Vgs shows little effect on
modulating the electron concentration inside highly doped SDE region, while the modulation of carrier concentration in the channel region is obvious. In addition, the current flow in SDE is mainly located in a region where the carrier concentration is insensitive toVbs, as shown in Fig. 7(c), which is plotted along
the vertical direction B−B defined in Fig. 7(a). It is obvious that the applied bias shows little effect on modulating both the carrier concentration and current flow inside the highly doped SDE region. Therefore, the Rsd values extracted under
high-Vgsand high-Vbsbias conditions well represent theRsdvalues
under regular operating bias conditions for devices with highly doped and abrupt SDE.
On the other hand, when the carrier concentration is lower than a critical value (4× 1019 cm−3 for the device used in this work based on TCAD simulation), it is sensitive to Vgs
bias conditions, as shown in Fig. 7(b). Rsd should comprise
the regions (on both source and drain sides) where electrical conductivity is Vgs independent. Therefore, Rsd can be
esti-mated by subtracting theVgs-dependent resistance from total
re-sistance:Rsd= Vds/Id− ΔVc/Id, whereΔVcis the potential
drop (Vc_drain− Vc_source) between two characteristic points
where the carrier concentration meets the critical value at the drain and source sides. Based on this method,Rsd values are
calculated under various bias conditions, and the results are summarized in the inset of Fig. 7(b). TheRsd values obtained
by using this simulation study are reasonably consistent with the extractedRsdvalues shown in Section V.
B. On the Bulk Charge Linearization Coefficientα
Bulk charge linearization coefficient(α) is treated as unity in previous sections. The error caused by this assumption is discussed in this section. By definition,α = 1 + 3Tox_inv/WD
[17], where WD is the channel depletion width. Based on
TCAD simulation, WD is about 43 nm for a 0.1-μm-Lmask
NMOSFET operated in the linear region (Vgs= 1.5−2.5 V,
Vds= 0.05 V, and Vbs= 0 V), as shown in Fig. 8(a). WD
is much thicker as compared to Tox_inv, which is 2.4 nm in
this work. As a result, the value ofα is 1.17 under this bias condition. When a negativeVbsis applied, the value ofα further
decreases becauseWDfurther increases. A table of values ofα under different bias conditions is shown in the inset of Fig. 8(a). As shown in Fig. 8(b), the impact of different values of α, from 1 to 1.4, on the extractedRsdis minor. The assumption of
“α = 1” is adequate for the proposed Rsdextraction method.
VII. CONCLUSION
Rsd extraction is realized by using a self-consistent
algo-rithm, combining the constant mobility criterion and an updated analytic calculation of the effective surface electrical field. By matching the shape of universal mobility curves of short- and long-channel devices using an iterative procedure, reasonable
Rsdvalues have been obtained for a wide range of gate lengths
Fig. 8. (a) Schematic plot of depletion width under gate area of a 0.1-μm-Lmask NMOSFET. A table of values of bulk charge linearization coefficient “α” under various bias conditions is shown in the inset. The values of “α” are typically lower than 1.2. (b) Extracted Rsdshows negligible sensi-tivity on the bulk charge linearization coefficient. Therefore, the assumption of “α = 1” is adequate in this extraction procedure.
without requiring information aboutLeff,Cox, andWeff. Even
in the presence of process-variation-induced uncertainty, the proposed method has proved promising for short-channel de-vices with heavily doped SDE.
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Engineering.
In 2000, he joined Taiwan Semiconductor Man-ufacturing Company, Hsinchu. His work mainly fo-cuses on the ultra-shallow-junction design and strain engineering for mobility enhancement of advanced logic CMOS devices. He is currently working on 22 nm node CMOS device technology research and development. He is the holder of five U.S. patents as well as six Taiwanese patents in the field of CMOS fabrication. His research interests include the extraction of MOSFET series resistance and carrier mobility enhancement with strained silicon.
Mr. Lin is a member of the Phi Tau Phi.
Ming-Lung Cheng was born in Tainan, Taiwan, in
1981. He received the B.S. degree in electrical engi-neering from the National Taiwan Ocean University, Keelung, Taiwan, in 2003 and the M.S. degree in electronic engineering from National Tsing Hua Uni-versity, Hsinchu, Taiwan, in 2005. His M.S. research focused mainly on low-temperature polysilicon thin film transistor (LTPS TFT) modeling.
In 2006, he joined Taiwan semiconductor Manu-facturing Company, Hsinchu. He worked on 45 nm layout dependency research and 32 nm CMOS de-velopment. Currently, he is working on 22 nm advance device dede-velopment.
Shyh-Wei Wang was born in Taiwan, in 1968. He
received the M.S. and Ph.D. degrees in electrical en-gineering from the National Chiao Tung University, Hsinchu, Taiwan, in 1992 and 1998, respectively.
He served as a Second Lieutenant in the Amy Air-borne from 1998 to 2000. In 2002, he joined Taiwan Semiconductor Manufacturing Company, Hsinchu. He worked on 65/45 nm low-power CMOS device technology development. Currently, he is working on 22 nm CMOS advanced device technology research and development.
Chung-Cheng Wu was born in Taiwan, in 1965.
He received the B.S., M.S., and Ph.D. degrees in electrical engineering from the National Taiwan Uni-versity, Taipei, in 1987, 1989, and 1992, respectively. His M.S. and Ph.D. research was focused mainly on the fabrication and study of III–V compound heterojunction bipolar transistors (HBTs).
Since December 1992, he has been working at the integrated circuit (IC) and thin-film transistor liquid-crystal display (TFTLCD) manufacturing compa-nies in Hsinchu Science Park, Hsinchu, Taiwan. In 1997, he joined Taiwan Semiconductor Manufacturing Company, Hsinchu. He worked on 0.18/0.15/0.13μm and 90/65/45 nm CMOS advanced device tech-nology definition and development. Currently, he is a Deputy Director in charge of 22 nm CMOS advanced device technology research and development. He is the author of more than ten journal or international conference publications. He is the holder of more than 30 U.S. and Taiwanese patents in the aforementioned fields.
Ming-Jer Chen (S’78–M’79–SM’98) received the
B.S. degree (with highest honors) in electrical engi-neering from the National Cheng-Kung University, Tainan, Taiwan, in 1977, and the M.S. and Ph.D. degrees in electronics engineering from the National Chiao Tung University (NCTU), Hsinchu, Taiwan, in 1979 and 1985, respectively.
Since 1985, he has been with the Department of Electronics Engineering, NCTU. He has been a Full Professor since 1993. From 1987 to 1992, he was a Consultant for the Taiwan Semiconductor
Manu-facturing Company, where he led a team from the NCTU and the Electronics Research and Service Organization/Industrial Technology Research Institute to build up a series of process windows and design rules. From 2000 to 2001, he was a Visiting Professor with the Department of Electrical Engineering and the Center for Integrated Systems, Stanford University, Stanford, CA. He is the holder of eight U.S. patents and six Taiwanese patents in the field of the high-precision analog capacitors, 1-T memory cell, dynamic threshold MOS, elec-trostatic discharge protection, and Flash memory. He has graduated 15 Ph.D. students and more than 100 M.S. students. His current research interests include semiconductor device physics and nanoelectronics.
