Effective Mobility Enhancement by Using Nanometer Dot Doping in Amorphous IGZO Thin-Film Transistors

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Hsiao-Wen Zan , * Wu-Wei Tsai , Chia-Hsin Chen , and Chuang-Chuang Tsai

Effective Mobility Enhancement by Using Nanometer Dot

Doping in Amorphous IGZO Thin-Film Transistors

Prof. H.-W. Zan , W.-W. Tsai , C.-H. Chen , Prof. C.-C. Tsai

Department of Photonic and Institute of Electro-Optical Engineering National Chiao Tung University

Hsin-Chu 30010, Taiwan

E-mail: [email protected]

DOI: 10.1002/adma.201102530

With a high mobility ( > 10 cm 2 _V − 1 _s − 1 _{) and a low threshold} voltage ( < 5 V) in low-temperature processes, transparent oxide semiconductor thin-fi lm transistors (TOS TFTs) have drawn considerable attention due to their applications on fl exible dis-plays, level shifters, drivers, and pixel-driving circuits for active-matrix organic light-emitting-diode (AMOLED) displays. [ 1 − 3 ] _In addition to display applications, amorphous indium gallium zinc oxide (a-IGZO) TFTs are also promising for the develop-ment of radio-frequency identifi cation (RFID) tags, smart cards, and other types of fl exible electronics. When TOS TFTs are developed for a low-power high-frequency circuit, high elec-tron mobility and a low parasitic capacitance are required. Most TFTs fabricated with ZnO, SnO 2 , In 2 O 3 , IGZO, or other semi-conducting oxide thin fi lms exhibit electron mobilities smaller than 35 cm 2 _V − 1 _s − 1 _. [ 4–6 ] _{Recent reports on transparent oxide} nanowire transistors (NWTs) have demonstrated high electron mobilities approximately 70 to 4000 cm 2 _V − 1 _s − 1 _. [ 7–9 ] _The quasi-1D structure of NWTs may reduce low-angle carrier scattering to produce high electron mobility. [ 9 ] _{However, the fabrication} process of NWTs has poor reproducibility and is still not prac-tical for real-world applications. Because TOS transistors are transparent, developing TOS circuits on windows is appealing. Particularly, for modern buildings or trains with series of win-dows, TOS RFID circuits on windows can deliver various types of signals through a low-power transmission system. In this type of application, the dimension of the transparent transistor can be large because an integrated circuit on a small chip is not necessary. A low-cost production method for delivering a high-performance TOS transistor is a critical challenge.

Here, a nanostructure to improve the effective mobility in a-IGZO TFTs is proposed. A large channel dimension of 1000 μ m, defi ned by a shadow mask, is utilized. The nano-structure is developed using a low-cost, lithography-free process to produce abundant nanometer-scale dot-like doping in a-IGZO channel. The new method, called nanodot doping (NDD) increases the effective electron mobility to a level 19 times higher than that of the control and the intrinsic elec-tron mobility is also 10 times higher than that of the control. This study demo nstrates a process utilizing self-organized poly-styrene spheres with a diameter of 200 nm to fabricate a porous gate structure. Ar plasma treatment through the porous gate performs dot-like doping on a-IGZO channel region. A top-gate

self-aligneda-IGZO TFT with an effective fi eld-effect mobility as 79 cm 2 _V − 1 _s − 1 _{(an intrinsic electron mobility as 39.6 cm} 2 _V − 1 _s − 1 ₎ is realized. The top-gate (TG) self-aligned structure also elimi-nates the overlaps between the gate electrode and the source/ drain contacts, which are known to suppress the parasitic capacitance and increase the response speed. The infl uences of dot and doping concentrations on device performance are also discussed. The application of NDD treatment on conventional bottom-gate (BG) a-IGZO TFTs is also demonstrated. After NDD treatment, a twofold improvement in electron mobility in a conventional bottom-gate a-IGZO TFT is observed.

Top-gate (TG) structures with NDD and without NDD (named STD hereafter) were fabricated. Two device structures called “TG-STD” (top-gate without NDD) and “TG-NDD” (top-gate with NDD) are depicted in Figure 1 a,b, respectively. The scanning electron microscopy (SEM) image of the cross-sectional view of the channel region of TG-NDD device is shown in Figure 1 c. Openings with 200 nm diameter can be observed in the channel region.

The process fl ow of fabricating TG-NDD is shown in Figure 2 a. A 30-nm-thick a-IGZO (3-in. circular target: In:Ga:Zn = 1:1:1 at%) was deposited by radio-frequency (RF) sputtering onto a precleaned glass substrate through a shadow mask to form the active layer at room temperature. During the sput-tering, the RF power and chamber pressure were 100 W and 9 mTorr, while the Ar fl ow rate was maintained at 30 sccm. The annealing process was then performed at 400 °C in a nitrogen furnace for 90 min. A 4000 Å cross-linkable poly(4-vinyl phenol) (PVP) was spin-coated on the a-IGZO surface and then cross-linked at 200 ° C for 60 min in air to serve as the gate insulator. The capacitance and the relative dielectric constant of PVP are 13.2 nF cm − 2 _{and 3.5, respectively.} co -formaldehyde) (methylated, Aldrich, M w ≈ 511) was utilized as a crosslinking agent for PVP. The surface of PVP was made hydrophilic by short-time exposure to a 50 W O 2 plasma before submerging the substrate into 2000 Å, positively charged poly-styrene spheres (Merck, K6–020) diluted in an ethanol solu-tion at 0.2 or 0.8 wt%. The SEM images of the PVP with 0.2 or 0.8 wt% PS sphere concentrations are shown in Figure 2 b,c, respectively. By counting the PS spheres in the SEM images in Figure 2 b,c, the concentration of dots per area is estimated to be 6.8 × 10 6 _mm − 2 _{for 0.8 wt% PS spheres and 4.8 × 10} 6 _mm − 2 for 0.2 wt% PS spheres, respectively.

The polystyrene spheres were adsorbed on the PVP surface to serve as the shadow mask. After submerging the substrate for 3 min in a polystyrene sphere solution, the substrate was then transferred into a beaker with boiling isopropyl alcohol solution for 10 s. The substrate was immediately blown dry to form 2D columnar arrays. A 1000 Å Al was evaporated as a metal gate electrode. After removing the polystyrene spheres

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fi lm (not shown), the relative concentrations of oxygen vacancies ( Vö, peak centered at

≈ 531.4 eV) in IGZO fi lms is increased from 20.18% to 24.67% after the Ar plasma treat-ment. (the relative concentrations of oxygen vacancies in IGZO fi lms is calculated by the area integration of O 1s ( Vö ) peak to the area integration of each O 1s peak). [ 10 ] _In previous reports, it has been found that the Ar-plasma-treated surface exhibits higher In concentration, lower Ga concentration, and lower Zn concentration than does the untreated sample. [ 11 ] _{The In-rich surface} contributes to the formation of a region with high electron concentration because the weak bonds between the In ions and oxygen are more likely to generate carriers than the Ga–O bonds or Zn–O bonds. [ 12 ] _The varia-tion in the cavaria-tion composivaria-tion (In, Ga, and Zn), however, was not the only reason for the dramatic decrease in the resistivity after Ar plasma treatment. The increase in oxygen defi ciency after the Ar ion bombardment was a critical factor in causing the drastic resis-tivity change. [ 11 ]

The transfer characteristics of TG-STD devices with different Ar plasma treatment durations are compared in Figure 3 b. In Figure 3 b, device channel width is 3000 μ m and the channel length is 1000 μ m. In this top-gate device, the Ar plasma treatment produces the source and drain regions with high electron concentration. Without the Ar plasma treatment, the offset regions between the gate-induced-channel and the source/ drain electrodes are highly resistive. As a result, no turn-on characteristics can be observed. After a suitable Ar plasma treat-ment (for example, the 3 min treattreat-ment depicted in Figure 3 b), the conductivity in the offset regions becomes high enough to serve as the source and drain regions. The transistor exhibits normal transfer characteristics. When the Ar plasma treat-ment time increases to 5 min, the leakage current increases because the sidewall of the PVP layer is damaged by the Ar ions. When the Ar plasma treatment time increases to 10 min, the thin IGZO fi lm is damaged due to the etching effect caused by the Ar ion bombardment. No turn-on characteristics can be observed.

The transfer characteristics of TG-NDD (PS 0.8 wt%) device with different Ar plasma treatment durations are shown in Figure 3 c. Device channel width is 3000 μ m and the channel length is 1000 μ m. In addition to forming the conductive source and drain regions, Ar plasma treatment in TG-NDD devices also produces a nanometer-scale dot-like doping in IGZO front channel surfaces. When the Ar plasma time is 3 min, the device exhibits superior transfer characteristics. The on cur-rent is higher than 0.1 mA, the off curcur-rent remains lower than 1 nA, the effective fi eld-effect mobility is 79 cm 2 _V − 1 _s − 1 _{, the} sub-threshold swing is 1.2 V decade − 1 _{, and the threshold voltage is} –2.94 V. When the Ar plasma time increases to 5 min, both the using an adhesive tape (Scotch, 3M), the PVP at sites without

Al coverage was removed after 8 min of 150 W O 2 plasma treat-ment. The source/drain region and the bare channel region (without PVP coverage) was then treated with Ar plasma to increase the conductivity. Finally, a 100-nm-thick layer of Al used as a source/drain metal was evaporated at room temper-ature through a shadow mask. The Ar plasma treatment on the source/drain regions of the a-IGZO active layer lowered the series resistance between the source/drain metal pads and the induced channel under the gate region. After Ar treatment, a self-aligned structure was formed. The channel width is defi ned by the edge of the a-IGZO pattern. For top-gate device (TG-STD and TG-NDD), the channel length is defi ned by the edge of the gate electrode. Due to the confi nement of the a-IGZO pattern, there is no current spreading outside the channel region. The channel width and length of the top gate devices are listed in Table 1 . For TG-STD, the process fl ow is similar to that depicted in Figure 2 (a) except that the PS sphere absorption process is removed.

Figure 3 a shows the resistivity of the a-IGZO thin fi lm as a function of the Ar plasma exposure time. The resistivity of a-IGZO fi lm is drastically reduced from > 10 5 _{Ω cm to 3.85 Ω cm} during the Ar plasma treatment. Also, from the result of O 1s X-ray photoelectron spectroscopy (XPS) spectra for a-IGZO thin

Glass

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Figure 1 . The schematic device structures of a) STD (standard) and b) TG-NDD a-IGZO TFTs.

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The infl uences of the nanodot concentration on the device performance are studied by fabricating TG-NDD devices with different PS sphere densities. The SEM images of the low-density PS sphere mask (PS 0.2 wt%) and the high-low-density PS sphere mask (PS 0.8 wt%) are shown in Figure 2 b,c, respec-tively. The transfer characteristics and the root square of the drain current plotted as a function of gate bias of TG-STD, TG-NDD (PS 0.2 wt%), and TG-NDD (PS 0.8 wt%) are com-pared in Figure 4 when channel width and length are 3000 μ m and 1000 μ m, respectively. In Table 1 , we listed the threshold voltage, the maximum fi eld-effect mobility, the average mobility, the standard deviation of the mobility, the subthreshold swing, and the on/off current ratio for the TG-STD and TG-NDD devices with different W / L (width/length) ratios (3, 3.3, and 10). The TG-STD devices, the TG-NDD with high density dots (produced with 0.8 wt% polystyrene spheres), and the TG-NDD with low density dots (produced with 0.2 wt% polystyrene spheres) are compared. The TG-NDD structure obviously increases the fi eld-effect mobility when we increase the concen-tration of the doping dots. High effective fi eld-effect mobility (71.7 to 87.4 cm 2 _V − 1 _s − 1 _{) can be obtained for TG-NDD with} high density dots and with a W / L ratio ranged from 3 to 10. The reproducibility is represented by the standard deviation of the mobility as listed in Table 1 . To improve the reproducibility and the uniformity, an ordered dot-like structure is required. Nanoimprinting may be utilized to produce an ordered nano-scale dot-like structure in future works. The improvement of mobility by NDD is observed for devices with various channel widths and lengths. Also, changing the W / L ratio does not sig-nifi cantly infl uence the mobility. The reported mobility overes-timation due to the current spreading is not observed. [ 13 ] _{In our} work, the channel width is defi ned by the IGZO pattern, not by the source/drain electrodes. A well-confi ned active region avoids current spreading outside the channel region. When most reported fi eld-effect mobilities of a-IGZO TFTs are lower than 35 cm 2 _V − 1 _s − 1 _, [ 4–6 ] _{three previous studies have reported} high mobility a-IGZO TFTs. The typical parameters of the high mobility a-IGZO TFTs in these previous reports are also listed in Table 1 . Kim et al. proposed that the metal-oxide TFT with ITO/IGZO double active layer exhibits a high mobility of 104 cm 2 _V − 1 _s − 1 _. [ 14 ] _{Lee et al. utilized a multilayer gate insulator} to realize an effective fi eld-effect mobility of 100 cm 2 _V − 1 _s − 1 _. [ 3 ] In these reports, the photolithography process is required to realize a channel length smaller than 20 μ m. Chiu et al. pro-posed a lithography-free long-channel a-IGZO TFT with a k (where k is the dielectric constant) gate dielectric to realize a high mobility of 62 cm 2 _V − 1 _s − 1 _. [ 15 ] _{In our work, an effective} mobility of 79 cm 2 _V − 1 _s − 1 _{can be achieved using nanodot} doping with a 1000 μ m channel length and a conventional sil-icon nitride gate dielectric. It is expected that the effective fi eld-effect mobility could be further increased if a high- k dielectric is used with the NDD structure.

The drastically enhanced mobility in NDD structures may be for two reasons. First, the effective channel length is reduced due to the conductive dot regions inside the channel. The effective channel length for TG-NDD devices can be esti-mated by calculating the dot concentration. For TG-NDD devices with high-density dots (with 0.8 wt% PS spheres), the effective channel length is reduced from 1000 μ m to 500 μ m. source to drain leakage current and the gate leakage current

are raised. Figure 3 d shows the output characteristics (drain current ( I D ) as a function of drain voltage ( V D )) of TG-NDD (PS 0.8 wt%) a-IGZO TFT with channel width and length of 3000 μ m and 1000 μ m, respectively. The transistor operates in the enhancement mode. I D increases linearly with increasing V D at low V D , and saturates at higher V D .

Figure 2 . a) The processes fl ow of the TG-NDD (top-gate with nano-dot

doping) a-IGZO TFT. The SEM images of the PVP substrate adsorbed with b) 0.2 wt% and c) 0.8 wt% polystyrene spheres. The diameter of the spheres is 200 nm.

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Figure 3 . a) Resistivity of the a-IGZO thin fi lm as a function of the Ar plasma exposure time. b) The transfer characteristics of TG-STD devices with

different Ar plasma treatment times on source/drain electrodes. c) The transfer characteristics of TG-NDD devices with high density dots (0.8 wt% PS spheres) with different Ar plasma treatment time. d) The output characteristics of TG-NDD devices (PS spheres: 0.8 wt%) with the optimal Ar plasma treatment time (3 mins). In Figure 3 b–d, the device channel width was 3000 μ m and the channel length was 1000 μ m.

Table 1. Comparisons of typical parameters in TG-STD and TG-NDD a-IGZO TFTs. W/L [ μ m/ μ m] W/L ratio V th [V] μ max a) ( μ avg b)) [cm 2 _V − 1 _s − 1 _] σ c) [cm 2 _V − 1 _s − 1 _] S.S . (V dec − 1 ₎ On/Off TG-STD 1000/100 10 − 3.1 5.53 (4.87) 0.304 0.97 1.7 × 10 5 1000/300 3.33 − 3.1 5.54 (5.3) 0.13 0.39 2.8 × 10 6 3000/1000 3 0.5 4 (3.38) 0.24 0.67 1.6 × 10 6 TG-NDD (0.8 wt%) 1000/100 10 − 2.29 87.4 (N/A) N/A 0.49 1.06 × 10 6 1000/300 3.33 − 2.47 71.7 (N/A) N/A 0.34 1.81 × 10 5 3000/1000 3 − 2.94 79.2 (67.5) 6.1 0.92 9.42 × 10 6 TG-NDD (0.2 wt%) 1000/100 10 5.91 45.6 (N/A) N/A 0.29 3.5 × 10 6 1000/300 3.33 4.5 47.5 (43.7) 4.16 0.72 5.6 × 10 6 a) _μ

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For TG-NDD devices with low-density dots (with 0.2 wt% PS spheres), the effective channel length is reduced from 1000 μ m to 684 μ m. If the effective intrinsic channel length is used to estimate the mobility inside the intrinsic a-IGZO region, the intrinsic mobility is 39.6 cm 2 _V − 1 _s − 1 _{for TG-NDD devices with} high-density dots and is 32.5 cm 2 _V − 1 _s − 1 _{for TG-NDD devices} with low-density dots. The mobility for TG-STD devices is only around 3.8 cm 2 _V − 1 _s − 1 _{, which is 8–10 times smaller than the} mobility in the intrinsic channel region for TG-NDD devices. The reduction of the effective channel length is not suffi cient to explain the enhanced mobility in TG-NDD devices.

The second reason to explain the enhanced mobility in the intrinsic channel region for TG-NDD devices is the fi eld-induced barrier lowering effect. It is known that the electron transport in a-IGZO is governed by the percolation trans-port. [ 16 , 17 ] _{The random distribution of Ga} 3 + _{and Zn} 2 + _{ions in}

the network structure forms potential barriers around the conduction band and then reduces electron mobility. [ 18 ] _The potential barrier can be signifi cantly reduced when carrier con-centration is increased. [ 16–18 ] _{When high-density conductive} dot-like regions are introduced into the intrinsic a-IGZO fi lm, the potential barrier in the intrinsic a-IGZO is lowered by the neighboring high conductive regions. Increasing the dot con-centration leads to a more pronounced barrier lowering effect. As a result, when dot density increases from 4.8 × 10 6 _mm − 2 _to 6.8 × 10 6 _mm − 2 _{, the mobility in the intrinsic channel increases} from 32.5 cm 2 _V − 1 _s − 1 _{to 39.6 cm} 2 _V − 1 _s − 1 _.

The barrier lowering effect is well observed in many semi-conductor devices. For example, the Schottky barrier at the metal–organic interface exhibits a Schottky barrier lowering effect when increasing the doping level of the organic semicon-ductor. [ 19 ] _{For short-channel MOSFETs, the built-in potential} barrier between the heavily doped source and the bulk suffers from the drain-induced barrier-lowering effect. [ 20–22 ] _{For poly-Si} TFTs, the grain boundary barrier is also lowered by the drain-to-source electric fi eld. [ 23 ] _{Drain-induced barrier lowering effect} is also observed in short channel ZnO TFT. [ 24 ] _{The high} den-sity dot-like doping in channel region of fi eld-effect transistors was not reported in previous studies. However, in our work, it

is believed that the effective potential barrier in the intrinsic a-IGZO surrounded by heavily-doped dots is lowered when the dot density is increased and when the doping level is increased. Since the electron mobility in a-IGZO is exponentially dependent on the negative of the potential barrier height, [ 16 , 17 ] the reduction of potential barrier leads to a signifi cant improve-ment of the electron mobility.

Finally, the NDD process is utilized on the back interface of conventional gate (BG) a-IGZO TFTs. The bottom-gate (BG) a-IGZO TFTs with and without NDD are denoted as BG-NDD and BG-STD, respectively. The schematic diagrams of BG-STD and BG-NDD a-IGZO TFTs are shown in Figure 5 a,b, respectively. For bottom-gate devices, process fl ow is similar to that shown in Figure 2 a, with two exceptions. The fi rst differ-ence is that the glass substrate is replaced by a heavily doped silicon substrate capped with a 100 nm silicon nitride. The second is that the top aluminum electrode above the PVP layer is replaced by a thermally evaporated SiO x (silicon oxide) with a thickness of 40 nm. The SiO x is served as a mask and the Figure 4 . The transfer characteristics and the root square of the drain

cur-rent plotted as a function of gate bias for three devices: TG-STD, TG-NDD (PS 0.2 wt%), and TG-NDD (PS 0.8 wt%). The device channel width is 3000 μ m and the channel length is 1000 μ m.

-20 -15 -10 -5 0 5 10 15 20 250.0 2.0x10-3 4.0x10-3 6.0x10-3 8.0x10-3 1.0x10-2 1.2x10-2 1.4x10-2 1.6x10-2 -20 -15 -10 -5 0 5 10 15 20 25 10-11 10-9 10-7 10-5 10-3

I

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Figure 5 . The schematic device structures of a) STD and b) NDD-BG

a-IGZO TFTs. c) Four typical parameters (threshold voltage, on/off ratio, mobility, and subthreshold swing) of BG-STD and BG-NDD devices are extracted and plotted as a function of Ar plasma treatment time. Each data point was extracted from the transfer characteristics measured at V D = 20 V. The device channel width is 1000 μ m and the channel length

is 100 μ m.

(a) (b)

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of the proposed a-IGZO TFTs with NDD are promising for the development of low cost circuit-like RFID tags, smart cards, and transparent circuits on windows.

Acknowledgements

This work was supported by the National Science Council of Taiwan under Contract Nos. NSC 99-2628-E-009-010 and NSC 99-2628-M-009-001.

Received: July 3, 2011 Published online: August 11, 2011

PVP without the SiO x coverage is etched by oxygen plasma. The channel width and length of the bottom gate devices are 1000 μ m and 100 μ m, respectively. The channel width is defi ned by the edge of the a-IGZO pattern. For bottom-gate devices (BG-STD and BG-NDD), the channel length is defi ned by the edge of the source/drain electrodes. Four typical para meters, including threshold voltage ( V th), on/off ratio, fi eld-effect mobility ( μ ), and subthreshold swing ( S.S. ), are extracted and plotted as a function of Ar plasma treatment time, as shown in Figure 5 c.

For BG-STD devices, when the Ar plasma time increases from 0 s to 180 s, the fi eld-effect mobility slightly increases from 10.76 to 15.6 cm 2 _V − 1 _s − 1 _{and the threshold voltage} decreases from 3.7 to –0.42 V. The subthreshold swing and the on/off current ratio are almost unchanged. The decrease in the threshold voltage and the increase of the fi eld-effect mobility after Ar plasma treatment was also reported by Park et al. and was explained by the improvement of the contact resistance between the source/drain electrodes and a-IGZO semiconductor. [ 11 ]

For BG-NDD devices, when the Ar plasma time increases from 0 s to 180 s, the fi eld-effect mobility signifi cantly increases from 10.8 to 32.7 cm 2 _V − 1 _s − 1 _{. The threshold voltage decreases} from 3.1 to –5.9 V. The NDD structure infl uences the electric fi eld distribution in the front channel because the a-IGZO fi lm is only 30 nm thick. As a result, the fi eld-effect mobility is enlarged by NDD treatment due to the reduced effective channel length together with the barrier-lowering effect. The shift of the threshold voltage is not clearly understood. In our previous report, the removal or the injection of electrons into body region causes a positively shifted or a negatively shifted threshold voltage, respectively. [ 25 ] _{When electron} concentra-tion in body region is increased, a more negative gate bias is required to deplete the channel. In this work, the dot doping creates localized high electron concentration regions. The 3D potential distribution in channel region is still not clearly inves-tigated. However, the negatively shift of threshold voltage is consistent with the phenomenon reported in our previous work when electrons are injected into back channel by capping cal-cium/aluminum layer onto the back interface of a bottom-gate a-IGZO TFT. [ 25 ]

To summarize, this study proposes a top-gate self-aligned a-IGZO TFT with nanometer-scale dotted channel doping. With a simple, low-cost, and lithography-free process, the effective mobility level of TG a-IGZO TFT becomes 19 times higher than that of the control sample and the maximum effective mobility reaches 79 cm 2 _V − 1 _s − 1 _{. If an effective intrinsic channel length} is used to estimate the mobility inside the intrinsic a-IGZO region, the maximum intrinsic mobility of TG-NDD a-IGZO TFT reaches 39.6 cm 2 _V − 1 _s − 1 _{and is 10 times larger than that of} the control (STD). The nanodot doping (NDD) structure reduces the effective channel length and lowers the potential barrier in the intrinsic a-IGZO by the neighboring high conductive regions. Increasing the dot concentration leads to a more pro-nounced barrier lowering effect. According to the percolation conduction model, the decrease of the potential barrier leads to a signifi cant increase of the fi eld-effect mobility in a-IGZO semiconductor. The high mobility and the self-aligned structure

[ 1 ] Y. Kwon , Y. Li , Y. W. Heo , M. Jones , P. H. Holloway , D. P. Norton , Z. V. Park , S. Li , Appl. Phys. Lett. 2004 , 84 , 2685 .

[ 2 ] H. Q. Chiang , J. F. Wager , R. L. Hoffman , J. Jeong , D. A. Keszler , Appl. Phys. Lett. 2005 , 86 , 013503 .

[ 3 ] H. N. Lee , J. Kyung , M. C. Sung , D. Y. Kim , S. K. Kang , S. J. Kim , C. N. Kim , H. G. Kim , S. T. Kim , J. Soc. Inf. Disp. 2008 , 16 , 265 . [ 4 ] C. T. Tsai , T. C. Chang , S. C. Chen , I. Lo , S. W. Tsao , M. C. Hung ,

J. J. Chang , C. Y. Wu , C. Y. Huang , Appl. Phys. Lett. 2010 , 96 , 242105 .

[ 5 ] H. Seo , Y. J. Cho , J. Kim , S. M. Bobade , K. Y. Park , J. Le , D. K. Choi , Appl. Phys. Lett. 2010 , 96 , 222101 .

[ 6 ] W. Lim , E. A. Douglas , S. H. Kim , D. P. Norton , S. J. Pearton , F. Ren , H. Shen , W. H. Chang , Appl. Phys. Lett. 2009 , 94 , 072103 .

[ 7 ] J. Sanghyun , F. Antonio , X. Yi , L. Jun , I. Fumiaki , Y. Peide , Z. Chongwu , J. M. Tobin , B. J. David , Nat. Nanotechnol. 2007 , 2 , 378 .

[ 8 ] P. C. Chang , Z. Fan , C. J. Chien , D. Stichtenoth , C. Ronning , J. G. Lua , Appl. Phys. Lett. 2006 , 89 , 133113 .

[ 9 ] F. Liu , M. Bao , K. L. Wang , C. Li , C. Zhou , Appl. Phys. Lett. 2005 , 86 , 213101 .

[ 10 ] S. Jeong , T. G. Ha , J. Moon , A. Facchetti , T. J. Marks , Adv. Mater. 2010 , 22 , 1346 .

[ 11 ] J. S. Park , J. K. Jeong , Y. G. Mo , H. D. Kim , S. I. Kim , Appl. Phys. Lett. 2007 , 90 , 262106 .

[ 12 ] K. Nomura , A. Takagi , T. Kamiya , H. Ohta , M. Hirano , H. Hosono , Jpn. J. Appl. Phys. 2006 , 45 , 4303 .

[ 13 ] K. Okamura , D. Nikolova , N. Mechau , H. Hahn , Appl. Phys. Lett. 2009 , 94 , 183503 .

[ 14 ] S. I. Kim , C. J. Kim , J. C. Park , I. Song , S. W. Kim , H. Yin , E. Lee , J. C. Lee , Y. Park , IEDM Tech. Dig. 2008 , 1 .

[ 15 ] C. J. Chiu , S. P. Chang , S. J. Chang , IEEE Electron Device Lett. 2010 , 31 , 1245 .

[ 16 ] A. Takagia , K. Nomura , H. Ohta , H. Yanagi , T. Kamiya , M. Hirano , H. Hosono , Thin Solid Film 2005 , 486 , 38 .

[ 17 ] K. Nomura , H. Ohta , A. Takagi , T. Kamiya , M. Hirano , H. Hosono , Nature 2004 , 432 , 488 .

[ 18 ] K. Nomura , T. Kamiya , H. Ohta , K. Ueda , M. Hirano , H. Hosono , Appl. Phys. Lett. 2004 , 85 , 11 .

[ 19 ] E. J. Lous , P. W. M. Blom , L. W. Molenkamp , D. M. de Leeuw , Phys.

Rev. B 1995 , 51 , 23.

[ 20 ] Y. Taur T. H. Ning , Fundamentals of Modern VLSI Devices , Cambridge University Press , Cambridge 1998 .

[ 21 ] L. D. Yau , Solid-State Electron. 1974 , 17 , 1059 .

[ 22 ] Y. Taur , G. J. Hu , R. H. Dennard , L. M. Terman , C. Y. Ting , K. E. Petrillo , IEEE Trans. Electron Devices 1985 , ED-32 , 203 . [ 23 ] W. J. Wu , R. H. Yao , IEEE Electron Device Lett. 2008 , 29 , 1128 . [ 24 ] H. H. Hsieh , C. C. Wu , Appl. Phys. Lett. 2006 , 89 , 041109 .

[ 25 ] H. W. Zan , W. T. Chen , C. C. Yeh , H. W. Hsueh , C. C. Tsai , H. F. Meng , Appl. Phys. Lett. 2011 , 98 , 153506 .