Improved Electrical Performance and Reliability
of Poly-Si TFTs Fabricated by Drive-In Nickel-Induced
Crystallization with Chemical Oxide Layer
MING-HUI LAI,1YEWCHUNG SERMON WU,1,2and CHIH-PANG CHANG1
1.—Department of Materials Science and Engineering, National Chiao Tung University, 1001 Ta-Hsueh Road, Hsinchu 300, Taiwan, R.O.C.2.—e-mail: [email protected] Ni-metal-induced crystallization (MIC) of amorphous Si (a-Si) has been employed to fabricate low-temperature polycrystalline silicon thin-film tran-sistors (TFTs). However, the Ni residues degrade the device performance. In this study, a new method for manufacturing MIC–TFTs using drive-in Ni-induced crystallization with a chemical oxide layer (DICC) is proposed. Compared with that of MIC–TFTs, the on/off current ratio (Ion/Ioff) of DICC– TFTs was increased by a factor of 9.7 from 9.21 9 104 to 8.94 9 105. The leakage current (Ioff) of DICC–TFTs was 4.06 pA/lm, which was much lower than that of the MIC–TFTs (19.20 pA/lm). DICC–TFTs also possess high immunity against hot-carrier stress and thereby exhibit good reliability. Key words: Drive-in nickel-induced crystallization, chemical oxide, fluorine
ion implantation, metal-induced crystallization, thin-film transistors (TFTs)
INTRODUCTION
Low-temperature polycrystalline silicon (LTPS) thin-film transistors (TFTs) have attracted consid-erable interest for their use in active-matrix liquid-crystal displays because they exhibit good electrical properties and can be integrated in peripheral cir-cuits on inexpensive glass substrates.1 Intensive studies have been carried out to reduce the crys-tallization temperature and time of amorphous sil-icon (a-Si) films. Metal-induced crystallization (MIC) is one of these efforts. The advantages of MIC include low cost, good uniformity, low tion temperature (500°C), and short crystalliza-tion time (0.5 h to 5 h). The Ni-MIC process produces crystallized a-Si thin films of the best quality, because NiSi2 has the lowest lattice mis-match (0.4%) with Si.2,3 Unfortunately, Ni and NiSi2 residues in the poly-Si film increase the leakage current and shift the threshold voltage.4,5 Therefore, Ni concentration in MIC poly-Si should be reduced to enhance device performance. The
atomic layer deposition system and gettering method have been employed to reduce the amount of undesired metal impurity. However, both methods are complex and incur high cost.6–8 Several recent studies have demonstrated that the introduction of fluorine (F) atoms can improve the performance and reliability of poly-Si TFTs, especially under electri-cal stress. Unfortunately, the minimum off-currents were almost unchanged,9–11 probably because the Ni concentration was constant.
This study proposes two processes for improving the performance of MIC–TFTs. First, Ni atoms were collided into the a-Si film by fluorine ion implanta-tion. Second, a chemical oxide layer was introduced between the Ni and a-Si layer. With these two pro-cesses, the electrical performance and reliability of TFTs were both improved. They showed a 4.73-fold decrease in minimum leakage current and a 9.70-fold increase in on/off current ratio compared with MIC–TFTs.
EXPERIMENTAL PROCEDURES
Three kinds of poly-Si TFTs were investigated in this study: MIC–TFT, fabricated by the traditional
(Received August 4, 2010; accepted January 14, 2011; published online February 8, 2011)
Ó2011 TMS
Ni-MIC method; DIC–TFT, in which F ions were implanted to drive Ni into the a-Si layer; and DICC– TFT, in which a chemical oxide layer was intro-duced into DIC–TFT before the F+ implantation. n-Type self-alignment poly-Si TFTs were investi-gated in this study. A 100-nm-thick undoped a-Si layer was deposited onto a 500-nm-thick oxide-coated Si wafer by using a low-pressure chemical vapor deposition (LPCVD) system.
To fabricate DICC–TFTs, samples were dipped into a mixed solution of H2SO4and H2O2for 20 min to form a chemical oxide (chem-SiO2) layer on top of the a-Si layer, as shown in Fig.1c. A 5-nm-thick Ni film was then deposited. Samples were subjected to F+ implantation to drive Ni into the a-Si layer, as shown in Fig. 1a.
The working and dose ranges of our ion implan-tation system (E220HP) are from 10 keV to 200 keV and 1 9 1012cm 2 to 5 9 1015cm 2, respectively. In this study, the ion accelerating energy was set to 10 keV. Simulation software (SRIM) was employed to adjust the projection range. Figure 2 shows the simulation data for the DIC–TFTs and DICC–TFTs. The projection range was set at a depth of 15 nm, near the surface of the a-Si layer. The fluorine ion dose was 2 9 1015 cm 2. To reduce Ni contamina-tion, the remaining Ni film and chemical oxide layer were then removed by wet etching (Fig.1b). The a-Si was subsequently annealed at 500°C for 1 h in N2 to achieve crystallization.
DIC–TFTs and MIC–TFTs were prepared for the purpose of comparison. The basic fabrication pro-cesses for both TFTs were almost the same as those for DICC–TFTs. In the DIC–TFTs, no chemical oxide layer was introduced. As for MIC–TFTs, the major difference was that the surfaces of the MIC poly-Si did not undergo any F+ implantation. A 5-nm-thick Ni film was deposited on the a-Si. After annealing at 500°C, the remaining Ni was removed. The deduced crystallization process parameters of all poly-Si films are summarized in TableI. It is
Fig. 1. Schematic illustration of the DICC–TFTs process: (a) F+
implantation process to drive Ni into the a-Si layer, (b) removal of remaining Ni film and chemical oxide, and (c) TEM image of chemical oxide layer.
worth noting that this DIC process does not need any additional annealing steps and is compatible with MIC processes.
TFT devices were fabricated by standard IC pro-cesses. The islands of poly-Si regions on the wafers were defined by reactive-ion etching. Next, a 100-nm-thick tetraethylorthosilicate/O2oxide layer was deposited as the gate insulator by plasma-enhanced chemical vapor deposition (PECVD). Then, a 100-nm-thick poly-Si film was deposited as the gate electrode by LPCVD. After defining the gate, self-aligned 35-keV phosphorous ions were implanted at a dose of 5 9 1015cm 2to form the source/drain and gate. After dopant activation, a 500-nm-thick SiO2 layer was deposited by PECVD as the passivation layer. Contact holes were formed, and a 500-nm-thick Al layer was then deposited by thermal evaporation and patterned as the electrode. Finally, a sintering process was performed at 400°C for 30 min in N2ambient.
RESULTS AND DISCUSSION
Figure3 exhibits the ID–VGtransfer characteris-tics of TFTs at a drain bias of 5 V for W/L = 10 lm/ 10 lm devices. The measured and extracted key device parameters are summarized in TableII. Ten TFTs were measured in each case to investigate device-to-device variation; average values with standard deviations in parentheses are shown in TableII. As can be seen, the minimum leakage current of DIC–TFTs was much lower than that of conventional MIC–TFTs. In poly-Si film, Ni resi-dues serve as deep-level traps, which promote thermionic emission-dominated leakage current because the Ni concentration in DIC–TFTs was reduced.12–14 Secondary-ion mass spectroscopy (SIMS) was employed to verify both Ni and F con-centrations in TFTs. As shown in Fig. 4a, the DIC process did reduce the Ni content in MIC poly-Si. As a result, the minimum leakage current of DIC–TFTs was much lower than that of conventional MIC– TFTs. Unfortunately, the on-current of DIC–TFTs was lower than that of MIC–TFTs. This degradation might be due to channel damage caused by ion implantation.15
To improve this on-current degradation, the DICC process (chemical oxide layer) was applied to the fabrication of DIC–TFTs. As shown in Fig. 3, the on-currents of TFTs were much improved by this
DICC process. Compared with that of MIC–TFTs, the on/off current ratio (Ion/Ioff) of DIC–TFTs was increased by a factor of 9.7 from 9.21 9 104 to 8.94 9 105. The leakage current (Ioff) of DICC–TFTs was 4.06 pA/lm, which was much less than that of DIC–TFTs (9.08 pA/lm) and MIC–TFTs (19.20 pA/ lm). This improvement is attributed to the reduc-tion of Ni concentrareduc-tion,12–14which was verified by SIMS measurement. As shown in Fig.4a, the Ni content in DICC was lower than that in DIC and MIC. Obviously, the Ni concentration in the channel layer was reduced by the introduction of the chem-ical oxide layer.
In addition, the improvement of the on-current of DICC–TFTs implies that the chemical oxide layer has ameliorated the channel damage caused by ion implantation. Moreover, as shown in Fig.4b, high F content is present at the poly-Si/oxide interface, meaning that F atoms have diffused to the interface to terminate Ni-related defects.10The on-current of DICC–TFTs was expected to be higher than that of MIC–TFTs, since F atoms can passivate dangling and strain bonds (trap states).9–11
To verify the interaction between implant damage and passivation of F+implantation on the channel
Fig. 3. Typical IDS VGS transfer characteristics of DIC–TFTs,
DICC–TFTs, and MIC–TFTs (W/L = 10 lm/10 lm).
Table I. Deduced crystallization process parameters of all poly-Si films
Chemical Oxide Implant Energy Implant Dose
MIC N/A N/A N/A
DIC N/A 10 keV 5 9 1015
DICC 5 nm 13 keV 5 9 1015
Table II. Average device characteristics of DIC– TFTs, DICC–TFTs, and MIC–TFTs with standard deviations in parentheses
W/L =
10 lm/10 lm MIC DIC DICC
LFE(cm 2 /V s) 15.60 (1.13) 10.85 (1.86) 26.70 (1.31) VTH(V) 12.85 (0.71) 14.99 (1.03) 11.99 (0.18) S.S. (V/dec) 2.77 (0.12) 2.52 (0.14) 2.06 (0.03) Imin(pA/lm) 19.20 (1.02) 9.08 (3.79) 4.06 (0.22) Max. on/off ratio (9105) 0.92 (0.07) 1.25 (0.71) 8.94 (0.76)
layer, the surface roughness and effective trap state density (Nt) were measured. The damage of poly-Si surfaces (after the residual Ni and chemical oxide layer were removed) was assessed using atomic force microscopy (AFM). As shown in Fig.5, the root-mean-square (rms) roughness of MIC, DIC, and
DICC films were 1.348 nm, 1.754 nm, and
0.866 nm, respectively. DIC poly-Si has the rough-est surface due to ion bombardment.15On the other hand, DICC poly-Si has the smoothest surface. The chemical oxide layer did improve surface roughness (reduced implantation damage).
The effective trap state density (Nt) was mea-sured using Levinson and Proano’s method, where Ntis estimated from the slope of the linear segment of ln[IDS/(VGS VFB)] versus 1/(VGS VFB)2at low VDSand high VGS, where VFBis defined as the gate
voltage that yields the minimum drain current at VDS= 0.1 V.16,17 As shown in Fig.6, the Nt of DICC–TFTs was 4.98 9 1012cm 2, which was
much less than that of MIC–TFTs (5.85 9
1012cm 2) and DIC–TFTs (6.69 9 1012cm 2). In other words, there were three major defects related to the performance of MIC–TFTs: (1) Ni concentration (Ni-related defects), (2) grain bound-aries, and (3) channel damage. In DIC and DICC, F+ implantation was employed to drive Ni into the a-Si layer. Compared with MIC, DIC and DICC can reduce the Ni concentration, thus overcoming the Ni-related defects. Moreover, F atoms can passivate dangling bonds and strain bonds, thus improving the negative effects of grain boundaries. However, the on-current of DIC–TFTs was lower than that of MIC–TFTs due to channel damage caused by ion implantation. In DICC, a chemical oxide layer was introduced between the Ni and a-Si layer to reduce
Fig. 4. SIMS depth profiles of (a) nickel and (b) fluorine in the structure of poly-Si films.
Fig. 5. AFM images and rms roughnesses of poly-Si after remaining Ni and chemical oxide were removed.
Fig. 6. ln[IDS/(VGS VFB)] versus 1/(VGS VFB)2at low VDS and
channel damage. As a result, DICC–TFTs has the highest on-current.
The other important issue of poly-Si TFTs is their reliability, which was examined under hot-carrier stress. In general, the stress voltage was set at the on-state saturation region. Early studies have demonstrated that device degradation increased with stress voltage from 20 V to 30 V. In this case, the stress voltage was set at 25 V (VDS= VGS= 25 V for 2500 s).9,15,18Figure7presents the I–V curves of the TFTs. As shown in Figs. 8and9, the on-current and the threshold voltage of TFTs were both degraded because dangling bonds were created due to the trapping of electrons at weak Si–Si and Si–H bonds.19,20 Compared with that of conventional
MIC–TFTs, the on-current degradation of DICC– TFTs is greatly improved by F+ implantation. DICC–TFTs also possess high immunity against the hot-carrier stress and thereby exhibit lower DVth and DIon/Ion, compared with conventional MIC– TFTs. This is because weaker Si–H and Si–Si bonds were replaced by stronger Si–F bonds,21which could not be broken under hot-carrier stress, thus leading to improved electrical reliability.
CONCLUSIONS
In this study, an investigation of poly-Si TFTs using the DICC process led to the development of a simple process for manufacturing LTPS TFTs. In
Fig. 7. I–V curves of DICC–TFTs and MIC–TFTs after stress.
Fig. 8. Variation of on-current versus hot-carrier stress time for the DICC–TFTs and MIC–TFTs.
Fig. 9. Variation of threshold voltage versus hot-carrier stress time for the DICC–TFTs and MIC–TFTs.
DICC, F implantation was employed to drive Ni into the a-Si layer. This implantation could reduce Ni concentration, and passivate dangling bonds and strained bonds by F atoms. As a result, DICC–TFTs had the lowest leakage current (4.06 pA/lm), which was much lower than that of MIC–TFTs (19.20 pA/lm). In addition, a chemical oxide layer was introduced between the Ni and a-Si layer to reduce channel damage/defects caused by ion implan-tation. As a result, the on/off current ratio of DICC– TFTs was increased by a factor of 9.7 from 9.21 9 105 to 8.94 9 105 compared with that of MIC–TFTs. It was also found that DICC can greatly alleviate the threshold voltage and on-current degradation under hot-carrier stress. DICC–TFTs possess high immu-nity against the hot-carrier stress and thereby exhibited lower DVth and DIon/Ion compared with conventional MIC–TFTs. This is because weaker Si–H and Si–Si bonds were replaced by stronger Si–F bonds, which could not be broken under hot-carrier stress, thus leading to improved electrical reliability.
ACKNOWLEDGEMENTS
This project was funded by Sino American Silicon Products Incorporation and the NSC of the ROC under Grant No. 98-2221-E-009-041-MY3. Techni-cal supports from the National Nano Device Labo-ratory, Center for Nano Science and Technology and the Nano Facility Center of the National Chiao Tung University are also acknowledged.
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