應用電容誤差校正技術之CMOS導管式類比數位轉換器

國 立 交 通 大 學

電信工程學系

碩 士 論 文

應用電容誤差校正技術之 CMOS 導管式類比

數位轉換器

A CMOS Pipelined Analog-to-Digital

Converter With Capacitor-Mismatch

Calibration Technique

研究生：邱建豪

指導教授：洪崇智 博士

應用電容誤差校正技術之 CMOS 導管式類比數位轉換器

A CMOS Pipelined Analog-to-Digital Converter With

Capacitor-Mismatch Calibration Technique

研 究 生：邱建豪 Student：Chien-Hao Chiu

指導教授：洪崇智 博士 Advisor：Dr. Chung-Chih Hung

國 立 交 通 大 學

電 信 工 程 學 系 碩 士 班

碩 士 論 文

A Thesis

Submitted to Department of Communication Engineering College of Electrical Engineering and Computer Science

National Chiao Tung University In Partial Fulfillment of the Requirements

For the Degree of Master In

Communication Engineering October 2007

Hsinchu, Taiwan.

應用電容誤差校正技術之 CMOS 導管式類比數位轉換器

研究生：邱建豪 指導教授：洪崇智 博士

國立交通大學

電信工程學系碩士班

摘要

在無限通訊系統以及影像或音訊應用中，類比數位轉換器扮演了一個重要的 角色。當今，對於低功率、高速及高解析度之類比數位轉換電路有著不可或缺的 需求。在許多種類之互補式金氧半類比數位轉器的架構當中，導管式類比數位轉 換器幾乎可以同時達到以上所述之三項效能。 在此次研究當中，一個十位元每秒取樣 100 百萬次操作電壓為 1.8 伏特的導 管式類比數位轉換器，從設計、佈局到製造均使用台積電標準 0.18 微米互補式 金氧半製程來完成，最後並完整地測試晶片。此類比數位轉換器主要包含前端的 取樣保持電路、相同 8 級串接的轉換器，和最後ㄧ級的 2 位元的快閃式轉換器。 所有的類比電路皆以全差動輸入設計，輸入峰對峰 1.2V 的輸入訊號並且供應電 源為 1.8 伏特。採用每級 1.5 位元解析度的架構是為了更高之類比數位轉換器之 轉換率。同時結合數位錯誤校正技術，可容忍比較器的偏移電壓到某個程度，使 比較器不需要前置放大器，進而減少整體的功率消耗。最後，因為製程漂移讓電 容發生不匹配而導致的增益錯誤，對於導管式類比數位轉換器來說是無法避免的 非線性效應。與過去的傳統架構來比較，此研究應用了”隨機切換電容”的技術 來抵抗電容不匹配之錯誤並維持線性度。當類比數位轉換器操作在保持相位時， 此方法讓位於一級之內的迴授電容可與取樣電容做隨機的切換，換句話說，這兩 種電容角色可以隨機互換。所以在此機制下，每一級發生的電容不匹配錯誤可被 平均出來並提昇整體類比數位轉換器之線性度。

此原型設計的類比數位轉換器之模擬表現出在頻率 100 萬赫茲的輸入弦波 訊號下,無寄生動態範圍(SFDR)達到 69.43dB，訊號對雜訊加上失真比(SNDR)約 為 59.15dB 且有效位元數將近 10 位元。最大的微分型非線性誤差為 0.55 最小位 元單位,積分型非線性誤差則是 0.7 最小位元單位。當我們假設有 3%的電容不匹 配存在時，實驗結果顯示線性度依然維持住，足以證明此技術之有效性。當輸入 80 百萬赫茲取樣頻率及 100 萬赫茲輸入訊號的情形，操作在隨機切換電容模式 下，量測到的 SNDR 為 42.73dB、ENOB 約為 6.81 位元;當操作在關閉隨機電容切 換模式下，所量測到的 SNDR 降低為 33.57dB、ENOB 約為 5.28 位元。此類比數位 轉換器晶片面積約 1.87mm2_{，並在最大取樣頻率 100 百萬赫茲及 1.8 伏特電源供} 應下,共消耗功率 88 毫瓦。

A CMOS Pipelined Analog-to-Digital Converter With

Capacitor-Mismatch Calibration Technique

Student：Chien-Hao Chiu Advisor：Dr. Chung-Chih Hung

Department of Communication Engineering National Chiao Tung University

Abstract

The analog-to-digital converter (ADC) plays a critical role in wireless communication systems and video/audio applications. Nowadays, the demand for low-power, high-speed, and high-resolution ADC circuit is indispensable. Among many types of CMOS ADC architectures, the Pipelined architecture can almost achieve above three performances at the same time.

In this work, a 10-bit 100MS/s Pipelined A/D converter operated at 1.8V power supply had been designed, laid out, and fabricated with standard TSMC 0.18μm CMOS 1P6M process, and this chip was also measured completely. This ADC mainly consists of one front-end S/H, eight cascaded MDAC stages, and a 2-bit flash converter in the last stage. All analog circuits are fully differential with a 1.2Vpp input signal and 1.8V power supply. A 1.5-bit/stage architecture is adopted for higher conversion rate. Furthermore, incorporating digital error correction technique, which is a successful algorithm of the redundant signed digit (RSD), tolerates comparators offset to some extent and thus no preamplifier is required. Therefore, total power consumption is reduced. Gain error resulted from capacitor-mismatch which is due to process variation, is an inevitable non-linear effect for the Pipelined ADC. As

compared with the conventional architecture, this research implements a “random capacitor-swapping” technique against the capacitor-mismatch error and maintains the linearity. This technique makes the feedback capacitor randomly swapped with the sampling capacitor in one stage during the hold cycle of the ADC operation, that is, their roles can randomly interchange. Therefore, the capacitor-mismatch error in each stage can be averaged out, and thus overall Pipelined ADC linearity is improved.

The prototype design of ADC simulation exhibits a peak spurious-free dynamic range (SFDR) of 69.43dB, a signal-to-noise-plus-distortion ratio (SNDR) of 59.15dB and the effective number of bits (ENOB) is about 10-bit with a 1MHz sinusoidal input. The maximum differential non-linearity (DNL) is 0.55 least significant bits (LSB) and the integral non-linearity is 0.7LSB. When we assume that there exists a 3% capacitor mismatch, experimental result shows the linearity still sustain to demonstrate the effectiveness of this technique. At 80MHz sampling rate with 1MHz sinusoidal input, the measured peak SNDR is 42.73dB and ENOB is about 6.81-bit when the capacitor-swapping is on; when the capacitor-swapping is off, the measured SNDR degrades to 33.57dB and ENOB is about 5.28-bit. This A/D chip occupies an area of 1.87mm2 and dissipates 88mW at the maximum sampling rate of 100MHz with 1.8V supply voltage.

誌謝

隨著這份碩士論文的完成，兩年來在交大的求學生活也即將告一個段落，往 後迎接著我的，又是另一段嶄新的人生旅程。本論文得以順利完成，首先，要感 謝我的指導教授洪崇智老師在我兩年的研究生活中，對我的指導與照顧，並且在 研究主題上給予我寬廣的發展空間。而類比積體電路實驗室所提供完備的軟硬體 資源，讓我在短短兩年碩士班研究中，學習到如何開始設計類比積體電路，乃至 於量測電路，甚至單獨面對及思考問題的所在。此外要感謝劉萬榮教授、闕河鳴 教授撥冗擔任我的口試委員並提供寶貴意見，使得本論文更為完整。也感謝國家 晶片系統設計中心提供先進的半導體製程，讓我有機會將所設計的電路加以實現 並完成驗證。 另一方面，要感謝所有類比積體電路實驗室的成員兩年來的互相照顧與扶 持。首先，感謝博士班的學長羅天佑、薛文弘、廖介偉、黃哲揚以及已畢業的碩 士班學長何俊達、黃琳家、蔡宗諺、林政翰、楊家泰和陳家敏在研究上所給予我 的幫助與鼓勵，尤其是俊達學長，由於他平時不吝惜的賜教與量測晶片時給予的 幫助，使得我的論文研究得以順利完成。另外我要感謝白逸維、廖德文、高正昇、 林明澤、吳國璽和傅崇賢等諸位同窗，透過平日與你們的切磋討論，使我不論在 課業上，或研究上都得到了不少收穫。尤其是電資710實驗室的同學們，兩年來 陪我ㄧ塊兒努力奮鬥，一起渡過同甘苦的日子，也因為你們，讓我的碩士班生活 更加多采多姿，增添許多快樂與充實的回憶。此外也感謝學弟們的熱情支持,因 為你們的加入，讓實驗室注入一股新的活力與朝氣。 到這邊，特別要致上最深的感謝給我的父母及家人們，謝謝你們從小到大所 給予我的栽培、照顧與鼓勵，讓我得以無後顧之憂地完成學業，朝自己的理想邁 進，衷心感謝你們對我的付出;還有默默陪伴著我的女友竹芸，感謝妳體諒我平 時的忙碌，以及在背後不斷地鼓勵我、支持我，並在這段成長的路上與我相伴。 最後，所有關心我、愛護我和曾經幫助過我的人，願我在未來的人生能有一 絲的榮耀歸予你們，謝謝你們。 邱建豪 于 交通大學電資大樓 710 實驗室 2007.10.1

Table of Contents

Abstract I Acknowledgment V Table of Contents VI List of Figures IX List of Tables XIII

Chapter 1 Introduction 1

1.1 Motivation ……… 1

1.2 Thesis Organization ……… 5

Chapter 2 Fundamentals and Architectures of Analog-to-Digital

Converters 7

2.1 Introduction ……… 7

2.2 The Concept and Performance Limitations of A/D Converters ……… 7

2.2.1 Quantization and Error ……… 8

2.2.2 ADC Performance Metrics ……… 11

2.3 ADC Architectures Overview ………. 18

2.3.1 Flash ADC ………. 18

2.3.2 Two-Step ADC ……….. 20

2.3.3 Pipelined ADC ………... 21

2.3.4 Key Circuit Components of Pipelined ADC ………. 23

2.4 Summary ……… 24

Chapter 3 System Analysis of The Pipelined Analog-to-Digital

Converter 25

3.1 Introduction ……… 25

3.2 Signal Processing of the Pipelined Stage ………... 25

3.3 Error Sources Consideration in One Stage ………. 29

3.3.1 Non-idealities in the Sub-ADC ……… 30

3.3.2 Non-idealities in the Sub-DAC .……… 32

3.4 Digital Error Correction with Stages Redundancy ………. 34

3.6 Behavior Model of Pipelined ADC ……… 42

3.6.1 S/H Circuit ………. 43

3.6.2 1.5-bit Sub-ADC ………... 45

3.6.3 Multiplying-DAC (MDAC) ……….. 46

3.6.4 2-bit Flash ……….. 48

3.6.5 Digital Error Correction Logic ……….. 49

3.6.6 Ideal 10-bit Pipelined ADC ………... 50

3.6.7 Non-ideal Effects in Behavior Models ……….. 52

3.6.7.1 Comparator Offset Effect ……….. 52

3.6.7.2 Finite Op-amp Gain Effect ………. 53

3.6.7.3 Capacitor-Mismatch Effect ………... 54

3.7 Proposed Capacitor-Mismatch Calibration Technique ………... 54

3.8 Summary ……… 58

Chapter 4 Design and Simulation of The Pipelined ADC With

Capacitor-Mismatch Calibration Technique 59

4.1 Introduction ……… 59

4.2 Accuracy Requirements of One Pipelined Stage ……… 60

4.2.1 Op-amp Requirements ………... 60

4.2.2 Capacitor Requirements ……… 63

4.3 Design of Analog Sub-Circuits ……….. 65

4.3.1 Input-Stage Sample-and-Hold Circuit ……… 65

4.3.1.1 Switched-Capacitor Technique ………. 65

4.3.1.2 Bootstrapped Switch ……… 70

4.3.1.3 Precharged S/H ………. 72

4.3.1.4 Bottom-Plate Sampling Technique ………... 76

4.3.2 Operational Amplifier ………... 77

4.3.3 Random Capacitor-Swapping Multiplying-DAC ……….. 82

4.3.4 Low-Power Dynamic Comparators ………... 84

4.3.5 Flash Quantizers ……… 85

4.4 Digital Circuitry ………. 87

4.5 Two Non-Overlapping Clock Generator ……… 89

4.6 Simulation Results of Overall Pipelined ADC ………... 90

4.7 Layout and Floor Plan ……… 94

Chapter 5 Testing Setup and Measurement Results 97

5.1 Introduction ……… 97

5.2 PC Board Design and Testing Setup ……….. 97

5.3 Measurement Results ………... 101 5.4 Summary ……….. 103

Chapter 6 Conclusions 104

6.1 Conclusions ..……… 104 6.2 Future Works ……… 105

Bibliography 106

List of Figures

Chapter 1

Figure 1.1 Applications of analog-to-digital converters ……… 2

Figure 1.2 ADC spec. v.s applications ……….. 3

Figure 1.3 ADC architectures v.s sampling rate and resolution ……… 3

Chapter 2

Figure 2.1 Signal characteristics caused by data conversion ……… 8

Figure 2.2 Ideal conversion characteristic of a N-bit ADC ………... 9

Figure 2.3 (a) An Ideal 3-bit ADC quantizer (b) Transfer curve (c) Quantization error centered about zero ……… 10

Figure 2.4 Assumed probability density function of the quantization error Qe .. 10

Figure 2.5 The power spectrum with the signal, distortions and noise ………... 13

Figure 2.6 (a) Dynamic range (b) Effective resolution bandwidth ………. 14

Figure 2.7 Offset error for quantization ……….. 15

Figure 2.8 Gain error for quantization ………. 16

Figure 2.9 DNL for quantization ………. 16

Figure 2.10 Missing code for quantization ……….. 17

Figure 2.11 INL for quantization ………. 17

Figure 2.12 N-bit Flash ADC ……….. 20

Figure 2.13 (a) N-bit Two-Step ADC (b) Coarse and Fine Conversions ……… 21

Figure 2.14 N-bit Pipelined ADC with multi-stage ……… 22

Chapter 3

Figure 3.1 (a) A single K-bit Pipelined stage (b) Vi toVi+1 residueplot ……….. 26

Figure 3.2 The 1-bit/stage example (a) transfer curve (b) trace diagram ……… 27

Figure 3.3 Timing analysis of Pipelined ADC ……… 28

Figure 3.4 M-stage Pipelined ADC with K-bit/stage architecture ……….. 29

Figure 3.5 Ideal 2-bit/stage (a) residue transfer curve (b) conversion characteristic ………... 30

Figure 3.6 2-bit/stage with offsets (a) residue transfer curve (b) conversion characteristic ………... 31

Figure 3.7 Residue transfer curve and conversion characteristic of 2-bit/stage with gain error (a) (b) larger and (c) (d) smaller than 4 ………. 32

Figure 3.8 2-bit/stage with non-linearity in MDAC (a) residue transfer curve (b) conversion characteristic ……….. 33

Figure 3.9 Two types of digital error correction for 2-bit/stage ……….. 35 Figure 3.10 Block diagram of one stage with offset in ADC and DAC ……….. 36 Figure 3.11 Residue plot with inter-stage gain of 2 (a) without offsets (b) with

offsets ………... 36

Figure 3.12 Ideal residue with 1/2 LSB offset ……… 37 Figure 3.13 New residue without the top-most comparator ……… 38 Figure 3.14 RSD correction in digital domain (a) ideal case (b) offset within

±VREF/4 ………. 39

Figure 3.15 10-bit Pipelined ADC with 1.5-bit/stage architecture ……….. 40 Figure 3.16 Switched-capacitor implementation of 1.5-bit stage ……… 40 Figure 3.17 (a) Basic implementation of S/H (b) Sample mode of (a) (c) Hold

mode of (a) ………... 43

Figure 3.18 S/H with (a) behavior model (b) MATLAB simulation ………… 44 Figure 3.19 1.5-bit Sub-ADC with (a) behavior model (b) MATLAB

simulation ………. 45

Figure 3.20 (a) Differential implementation of MDAC (b) sample mode of (a)

(c) amplification mode of (a) ……… 46

Figure 3.21 MDAC with (a) behavior model (b) MATLAB simulation with sine

input (c) MATLAB simulation with ramp input ………... 47

Figure 3.22 2-bit Flash ADC with (a) behavior model (b) MATLAB

simulation ……… 49

Figure 3.23 Behavior model of digital error correction ……….. 49 Figure 3.24 Behavior model of ideal 10-bit Pipelined ADC ………... 50 Figure 3.25 The reconstructed waveform of (a) sine wave (b) ramp ………….. 51 Figure 3.26 Ideal Pipelined ADC model with (a) FFT spectrum (b) DNL and

INL versus code ………... 52

Figure 3.27 FFT spectrum with an offset effect of (a) 0.2VREF (b) 0.4VREF …... 53

Figure 3.28 Finite op-amp gain effects of (a) 60dB (b) 54dB ……… 53 Figure 3.29 Capacitor-mismatch effects with (a) 1% mismatch (b) 3%

mismatch ……….. 54

Figure 3.30 Conventional MDAC for 1-bit or 1.5-bit Pipelined stages ……….. 56 Figure 3.31 (a) 1.5-bit MDAC with capacitor-swapping technique (b) Pseudo-

random clock generator ……… 57

Chapter 4

Figure 4.1 Operation of adjacent Pipelined stages ……….. 60 Figure 4.2 Settling analysis of step response ……….. 62 Figure 4.3 (a) The simple sampling circuit (b) Functionality ………. 66

Figure 4.4 (a) Equivalent circuit of sample mode (b) Transition from sample mode

to hold mode ………. 66

Figure 4.5 Finite falling time with aperture jitter ……… 69 Figure 4.6 Bootstrapped switch with (a) basic idea (b) transistor-level

implementation ………... 70

Figure 4.7 Simulation result of bootstrapped switch ………... 71 Figure 4.8 Precharged S/H with (a) fully differential scheme (b) timing

operation ………. 72

Figure 4.9 Precharged S/H with (a) sample mode (b) hold mode ………... 73 Figure 4.10 S/H simulation results with (a) input/output transient response

(b) FFT spectrum ……….. 75

Figure 4.11 Bottom-plate sampling ………. 76 Figure 4.12 Fully-differential folded-cascode op-amp with gain boosting ……. 78 Figure 4.13 (a) Impedance boosting with feedback (b) Small signal model …... 79 Figure 4.14 Switched-capacitor CMFB circuit ………... 80 Figure 4.15 AC response simulation of the op-amp ……… 81 Figure 4.16 Random capacitor-swapping MDAC with (a) circuit implementation

(b) swapping-enable circuit ……….. 82

Figure 4.17 MDAC simulation result of input/output transient response ……... 84 Figure 4.18 Low-power dynamic comparator ………. 84 Figure 4.19 Comparator simulation result (a) without SR latch (b) with SR

latch ………. 85

Figure 4.20 (a) 1.5-bit Flash Sub-ADC (b) Simulation result ………. 86 Figure 4.21 (a) 2-bit Flash Sub-ADC (b) Simulation result ……… 87 Figure 4.22 Shift register arrays and digital error corrections logics ………… 88 Figure 4.23 Multi-phase clock generator ………. 89 Figure 4.24 Simulation result of different clock phase ………... 90 Figure 4.25 Transient response simulation with (a) sinusoidal (b) ramp input

signal ……… 90

Figure 4.26 FFT spectrum of 10-bit output codes with (a) 1MHz (b) 6MHz

(c) 40MHz sinusoidal input ……….. 91

Figure 4.27 Simulation results of (a) DNL (b) INL ………. 92 Figure 4.28 Linearity with 3% capacitor-mismatch (a) capacitor-swapping is OFF

(b) capacitor-swapping is ON ………... 93

Figure 4.29 (a) Layout (b) Floor plan (c) Die photograph of the whole chip …. 94

Chapter 5

Figure 5.2 Power supply regulator with bypass filter ……….. 98

Figure 5.3 Photograph of the testing ADC on PCB ………. 98

Figure 5.4 (a) Function/arbitrary waveform generator (b) SPILLTER (c) BIAS TEE ………. 99

Figure 5.5 Pulse/pattern generator ………... 99

Figure 5.6 Logic analyzer ……… 99

Figure 5.7 Pins configuration and assignments ………. 100

Figure 5.8 Measured results of (a) 10-bit codes (b) decimal-recovered sine wave ………. 101

Figure 5.9 Comparison of FFT spectrum between (a) conventional operation and (b) capacitor-swapping operation ………. 102

Figure 5.10 The measured SNDR against the sampling frequency …………... 103

List of Tables

Table 2.1 A/D Converter Architectures ………... 18 Table 4.1 Simulation of the op-amp in five process corners ………... 82 Table 4.2 Performance comparison between capacitor-swapping ON and OFF

with 3% capacitor-mismatch ……… 93

Table 4.3 Simulation summary of this prototype ADC ………... 96 Table 5.1 Summary of measured results of this testing chip ………. 103

Chapter 1

Introduction

1.1 Motivation

With the rapid evolution of CMOS fabrication technology, more and more signal-processing functions are implemented in the digital domain for lower cost, lower power consumption, and higher yield requirements. As compared with analog circuits, digital circuits are not easily influenced by noise, operating voltage, and process variation. Nowadays, many applications utilize the digital signal processing (DSP) to resolve the transmitted information. Even though digital circuits have so many advantages, they must eventually communicate with the nature environment which abounds with analog signal. Therefore, an analog-to-digital interface between the received analog signal and the DSP system is required and critical. This interface achieves the digitization of the received waveform subject to a sampling rate requirement of the system. In order to make the transmission system more accurate, reliable, storable, faster, and higher yields, the interface of ADC is a critical component and plays an important role in the system.

Furthermore, the trend of increasing integration level for integrated circuits leads to systems with fewer numbers of chips, lower power dissipation, and process integration. The ultimate goal is to be a single chip solution, the system on a chip (SoC). This trend has forced the ADC to reside on the same silicon with a large amount of DSP and digital circuits. By operating at the same supply voltage on the same die, it reduces the overall system cost to save the requirement of generating

multiple supply voltages with DC-DC converters. Therefore, an ADC operating at the same voltage with digital circuits is desirable, and it makes low voltage operation to be a relevant issue. Besides, there is also a tendency for boosting the transmitted data rates, which is based on wider signal bandwidth and higher signal-to-noise ratio in the wireless communication or image processing systems, so, the increasing conversion rate and higher resolution of ADCs are urgently required.

However, the design of data converter accompanying the scaling of CMOS technology has more challenges to confront. Such as thinner gate-oxide in MOS devices, which bring about the problem of reliability and hot carrier effect; and the short channel effect, which is the cause of punch-through. Besides, the lower operating voltage following scaling CMOS technology also makes analog (mixed signal) circuits that emphasize transistors work region to face enormous difficulties in design. As a result, how to overcome these difficulties and choose an appropriate structure in Mixed-Mode ADC design are the research points.

The applications of analog-to-digital converters are widespread, such as wireless communication systems, cellar phones, digital video (audio) systems, etc…, as illustrated in Figure 1.1 [1].

There are different applications for different architectures of analog-to-digital converters. Various commercial applications demand different ADCs resolution and speed they claim, as illustrated in Figure 1.2. Also, many kinds of ADCs having their own characteristics are chosen for the best suitable applications, as illustrated in Figure 1.3 [2].

Figure 1.2 ADC spec. v.s applications

Figure 1.3 ADC architectures v.s sampling rate and resolution

Among many types of CMOS ADC architectures, the Pipelined ADC has many attractive merits in conversion speed, input bandwidth, power consumption, and chip area, that is, the Pipelined architecture offers good trade-off among speed, resolution, and power for Nyquist-ADC [3] when compared to other architectures.

This work, a 10-bit 100MS/s Pipelined A/D converter with a 1.8V supply voltage had been designed and implemented with standard TSMC 0.18μm CMOS 1P6M process, and no special process or multiplied voltage is required. Here the front-end “pre-charged” S/H, which is adopted to achieve high sampling rate, is easily designed to sample more precisely and settle more quickly than the conventional “flip-around” architecture. A 1.5-bit/stage architecture of digital error correction is adopted to make each Pipelined stage capable of correcting comparator offset errors from previous stages, relaxing the comparator accuracy for lower power requirement. Finally, a switched-capacitor (SC) implementation in the Pipelined ADC is sensitive to mismatch of capacitors, and the capacitor ratio determines the inter-stage gain. Therefore, a precision inter-stage gain is required to achieve the desired overall ADC linearity and we concentrate it in this thesis. Hence, a linearity-improving technique is employed under the capacitor-mismatch condition, which shows good linearity. It is not complex in circuit implementation and takes no extra clock cycle for calibration.

1.2 Thesis Organization

This thesis is organized into six chapters and is described as following.

Chapter 1 briefly introduces the analog-to-digital converters and this thesis.

Chapter 2 begins with the concepts of analog-to-digital conversion and performance metrics used to characterize ADCs. Then, several high-speed ADC architectures are introduced and the evolution of them is described. Finally, the Pipelined architecture is chosen and we focus on it in summary.

Chapter 3 concentrates on the characteristics of the Pipelined ADC, which is described in detail from its operation principle to the actual implementation of each stage including 1.5-bit/stage architecture with digital error correction. Furthermore, the behavioral models simulations of a Pipelined ADC are built to obtain the requirement of design, and we analyze the effects of circuit components non-idealities. Finally, the proposed technique of capacitor-mismatch calibration is introduced, and it was applied in our design to prevent overall resolution from degrading due to the capacitor-mismatch effect.

Chapter 4 illustrates the design and implementation of the Pipelined ADC with capacitor-mismatch calibration technique, where key circuit components will be introduced in detail. Among them are the operational amplifier, the bootstrapped switch, the comparator, the input stage sample-and-hold circuit (S/H), the 1.5-bit/stage circuit, the 2-bit flash ADC, and digital circuits including clock generator. The transistor level simulation results of each circuit are presented, and the simulation

of whole Pipelined ADC, as well as its layout and floor plan are also shown at the end of this chapter.

Chapter 5 presents the measurement environment, including component circuits on the DUT (device under test) board and the required instruments. Finally, the measured results of the prototype chip described in Chapter 3 and Chapter 4 are shown and summarized.

Finally, Chapter 6 is the conclusion for this work. Some suggestions and improved recommendations are proposed for the future work.

Chapter 2

Fundamentals and Architectures of

Analog-to-Digital Converters

2.1 Introduction

In this chapter, we first introduce the concepts of analog-to-digital conversions and discuss some fundamental issues in the design of data converters, which are the performance metrics to characterize ADCs. Second, some of the prominent ADC architectures for high-speed applications are the surveyed subjects and each of them has different trade-off among speed, resolution, power and area. At the end of this chapter, we summarize and focus on the most appropriate architecture to meet our target specification.

2.2 The Concept and Performance Limitations of A/D Converters

In signal transmission systems linking between the nature world and the digital processors, data converters including ADC and DAC are the devices translating the analog signals into digital codes or performing the reverse operation.

Figure 2.1 shows an overall signal transmission system [4]. The original analog signal (a) is filtered by an anti-aliasing filter (b) to remove any high-frequency components that may cause an effect known as aliasing. Then, the signal is converted into a digital form (d) by the analog-to-digital conversion (c) separated into two operations: sampling and quantization. Sampling operation transforms the continuous

and infinite valued signal into a corresponding discrete time signal, while quantization operation quantizes the discrete time signal to have a certain digital code level for each discrete period, which is generally expressed as conversion period. However, some ADC architectures, such as Flash ADC, can execute sampling and quantization simultaneously to achieve very high throughput rates.

Figure 2.1 Signal characteristics caused by data conversion

2.2.1 Quantization and Error

The analog-to-digital conversion tends to quantize the sampled input analog signal into an N-bit digital word, which is known as the total resolution. That is, the full range of analog signal defining as VFS is divided into several smaller sub-ranges (segments) according to the numbers of quantization steps 2N, and these sub-ranges are uniform in size ideally. Figure 2.2 illustrates the ideal conversion transfer curve of an N-bit ADC. During the conversion process, the value of signal in which segment range is decided and sends a set of corresponding output digital word representing the sampled input signal [5]. Furthermore, the quantization step size of each sub-range are also referred to as one least significant bit (LSB), and VLSB is the difference of two transition voltages defined as

2

FS LSB N

V

V = (2.1) , and the transition voltages can be written as

, 2 FS tn N V V = ⋅n n∈

{

0,1, 2,..., 2N

}

(2.2) By the way, if the circuit is operated in fully differential, then VFS=2VREF, where VREF is the analog reference signal applied to ADCs.

Figure 2.2 Ideal conversion characteristic of a N-bit ADC

Since the analog input signal is continuous-valued and the digital output is discrete-valued, this signal ambiguity produces what is known as quantization error, Qe, is defined as the difference between the actual analog input and the value of the quantized staircase given in voltage. In Figure 2.3(a), we take an ideal 3-bit ADC conversion for example and shift the transfer curve like Figure 2.2 to the left by 1/2 LSB [4], showing in Figure 2.3(b). The midpoints of the staircase curve defining

Vstaircase can be calculated by

2

FS

staircase N LSB

V

V = ⋅D = ⋅D V (2.3) , where the quantization error can be generated by subtracting the value of the staircase from the dashed line, and Qe is represented as

e IN staircase

Q =V −V (2.4) The result can be seen in Figure 2.3 (c), where a sawtooth waveform is centered about zero.

Figure 2.3 (a) An Ideal 3-bit AD quantizer (b) Transfer curve

(c) Quantization error centered about zero

As mentioned in Figure 2.3, quantization errors even occur in ideal A/D converters. Clearly, the average of Qe is zero and is limited to ±0.5VLSB, therefore, we can model these errors as being equivalent to an additive noise source and find its power. We assume that the quantization error Qe is a random variable uniformly distributed between ±0.5VLSB. The probability density function (PDF) for such an error signal will be a constant value, as shown in Figure 2.4. Hence, the quantization noise power (variance) PQ can be calculated by

2 0.5 2 2 0.5 1 ( ) 12 LSB LSB V LSB Q Q V LSB V P q f q dq q dq V ∞ −∞ − =

∫

=

∫

= (2.5)

, and the R.M.S value of the quantization noise equals V_LSB/ 12.

Finally, we can conclude that the quantization noise power is independent of the sampling frequency, fs; on the contrary, it is proportional to the size of VLSB. The size of VLSB is halved and the noise power decreases by 6 dB for each additional bit-resolution in the A/D converter.

2.2.2 ADC Performance

Metrics

In this section, some commonly used definition indicating the performance of the analog-to-digital converters are introduced as below, which can be separated into dynamic characteristics and static characteristics [4][6][7].

Dynamic Characteristics:

Resolution

The “ideal” resolution of ADCs is defined as the numbers of distinct analog input sub-ranges corresponding to the different output digital words. For a fixed full-scale analog input range, an N-bit resolution implies that the converter can resolve 2N distinct input segments, and the high resolution can resolve smaller sub-ranges of signals than the low resolution. Nevertheless, the “actual” resolution is generally degraded by either noise or non-linearity in ADCs, so it is also treated as effective number of bits (ENOB) of the ADC output digital bits.

Signal-to-Noise Ratio (SNR)

A sinusoidal input signal is usually used to characterize a data converter. The signal to noise ratio (SNR) means the ratio of the signal power to the noise-floor power at ADCs output, and the relationship is expressed as

_ ( ) 10 _ ( ) 20 IN signal RMS Total noise RMS V SNR log V   = _ _   dB (2.6)

We assume that the sampled sinusoidal input has the form as

V_IN( )k = Asin 2

(

πf kT_i⋅ _s

)

(2.7) , and its R.M.S value isA/ 2 . The noise power here is only referred to the quantization noise and its R.M.S value had been described asV_LSB/ 12. Therefore, when the input amplitude equalsA=A_FS/ 2, the maximum SNR of an N-bit ADC is

_ ( ) N 10 10 10 ( ) / 2 3 20 20 20 2 2 / 12 6.02 N+1.76dB IN signal RMS RMS LSB V A

SNR log log log

V V       = _ _= _ _= _ _       = ⋅ Ｑ (2.8)

, and it decreases from this best value for reduced input signal levels [8].

Signal-to-Noise＋Distortion Ratio (SNDR)

The signal to noise plus distortion ratio (SNDR) is often used to measure the performance of an ADC. When a single frequency sinusoidal signal is applied to the ADC system, the fast Fourier transform (FFT) of the system output generally contains a tone at the fundamental (input) frequency. Due to distortion, the output also contains signal tone including aliasing at all harmonics of the input frequency. As a result, the SNDR of the ADC is defined as the ratio of the signal power at the fundamental frequency to the total power of non-ideal effects, including all harmonic distortions (HD) and all of the noise sources presented at the output, which is expressed as below

_ ( )

10

_ ( ) _ ( )

20 IN signal RMS

Total noise RMS Total HD RMS

V SNDR log V V   = _{ +} _   dB (2.9)

Furthermore, we can derive the effect number of bits (ENOB) to observe how the actual resolution influenced by the combined non-ideal effects to what extent, which

is calculated by the value of SNDR

1.76

6.02 SNDR

ENOB= − (2.10)

Spurious-Free Dynamic Range (SFDR)

The spurious free dynamic range is defined as the ratio of the fundamental signal component to the largest distortion component being usually at 3rd harmonic in a specified frequency range and expressed as

₁₀ _ ( ) _ ( ) 20 IN signal RMS Max HD RMS V SFDR log V   = _ _   dB (2.11)

Finally, we can easily get much more understanding among SNR, SNDR, and SFDR by the FFT spectrum plot illustrated in Figure 2.5, where S is the fundamental frequency of the input signal, D are the harmonic distortion components, and N is the noise floor.

Figure 2.5 The power spectrum with the signal, distortions and noise

Furthermore, SNR and SNDR in Figure 2.5 are respectively depicted as SNR S SNDR S

N N D

= =

Dynamic Range (DR) and Effective Resolution Bandwidth (ERB)

Dynamic range (DR) is a measure of the range of input sinusoidal signal amplitudes, which is also a useful performance benchmark. We apply a single frequency signal to the ADC and vary its amplitude, the definition of dynamic range is the ratio of the input signal level with maximum SNR to the input signal with 0dB SNR, as shown in Figure 2.6(a). SNR with 0dB means that the input signal is too indistinct to be recognized and is the minimum detectable power. If the noise power is independent of the signal level, the dynamic range is equal to the SNR at full scale. Nevertheless, in most conditions, the noise power increases as the signal level increases. In general, the actual maximum SNR is less than the defined dynamic range [5][8]. Figure 2.6(a) also indicates that the harmonic distortions increases as the increasing signal level, and then the value of SNR is severely degraded by distortions.

0 dB SNR (dB) Dynamic Range VIN(dB) Performance here is limited by noise

Performance here is limited by harmonic distortion Peak SNR SNDR (dB) 1K10K ERB 100M 0 dB Input Frequency (Hz) (a) (b)

Figure 2.6 (a) Dynamic range (b) Effective resolution bandwidth

Figure 2.6(b) shows that SNDR gradually decreases as the input signal frequency increases. The maximum input frequency that can sustain efficient SNDR dropping about 3dB is called the effective resolution bandwidth (ERB). This bandwidth is limited by Nyquist Sampling Theorem to avoid aliasing.

Static Characteristics:

Offset Error

ADCs have an Input-Output transfer characteristic of quantization that approximates a straight line, and it progresses from low-to-high in uniform steps ideally. However, the practical transfer steps might be not uniform ideally. The imperfections cause errors or non-linearity performance in ADCs. In Figure 2.7, an error which causes the actual steps to shift horizontally from their ideal positions by a constant amount is called the offset error.

Figure 2.7 Offset error for quantization

Gain Error

Gain error or scale factor error, seen in Figure 2.8, is the difference between the slope of a straight line drawn through the midpoints of the actual transfer steps and the ideal slope of 1 [9].

Ideal Actual Analog Input Digital Output Gain Error

Figure 2.8 Gain error for quantization

Differential Non-Linearity (DNL) and Missing Code

Each width of quantization steps may not equal to one LSB (1LSB = AFS/2N) due to the non-idealities in ADCs. Then, the differential non-linearity (DNL) is defined as the value of each step width deviating from the ideal step width as Figure 2.9

Figure 2.9 DNL for quantization

ADCs possessing a DNL that is equal to -1LSB are guaranteed to have a missing code, as illustrated in Figure 2.10. The step width corresponding to Codek is completely missing; thus, the value of DNLk is -1LSB.

Figure 2.10 Missing code for quantization

On the contrary, DNL larger than +1LSB is not guaranteed to have a missing code, though in all probability a missing code will occur.

Integral Non-Linearity (INL)

The integral non-linearity (INL) is defined as the total deviation of the middle point of step from the ideal value that ADCs tend to approximate. Unlike the DNL, INL can be any values and can be expressed in Figure 2.11, where Vmd_n is the middle point of the n-th step, and Vid_k is the ideal middle point value of this step. From another view-point, INLn equals to the summation of DNL0 to DNLn.

0 n i i DNL =

∑

Figure 2.11 INL for quantization

and ADCs main non-linear effects including DNL, INL as well as Missing Code will cause the non-monotonic characteristic and enhance distortions.

2.3 ADC Architectures Overview

A/D converters can be classified into two types of Nyquist-rate and Over-sampling. According to the speed and accuracy for different applications, the architectures of Nyquist-rate ADCs can be roughly divided into three categories: low-to-medium speed, medium speed, and high speed, as shown in Table 2.1. Choosing each of them has different trade-off among speed, resolution, power and area for the best solution [10][11]. Generally, the Over-Sampling architecture of the ADC is adopted for high resolution (16-bit above) design [10]. In this section, the architectures of Flash, Two-Step and Pipelined will be discussed for their close relationship.

Table 2.1 A/D Converter Architectures

2.3.1 Flash ADC

converters. For N-bit resolution, the input signal of a Flash ADC is simultaneously fed to 2N comparators in parallel, each of the comparators samples the input signal and compares the signal to its corresponding reference value, as shown in Figure 2.12. The series of reference voltages are generated equally spaced by dividing a resistor string connected between +VREF and –VREF and are applied to one input of each comparator. Any comparator connected to a resistor string node where the reference of each comparator is larger than the input signal will have outputs of 1, while those connected to nodes with reference voltages less than the input will have outputs of 0, and the level of the interface between 0s and 1s would indicate the value of the signal. The set of 2N comparator outputs is commonly referred to as a thermometer code since it looks quite similar to the mercury bar in a thermometer and is encoded to N-bit binary code word with an encoding circuit. Besides, the NAND gates called as the pre-encoder are also designed to remove the bubble error usually occurring near the transition point of the thermometer code. As seen from the Figure 2.12, the process of the input sampling and quantizing are operation in parallel. Thus, the Flash ADC can be capable of very high speed (high throughput and small latency) and its conversion time is only limited by the speed of the comparators.

The most main drawback to the Flash ADC is the huge requirement of hardware which grows exponentially with the increasing resolution, especially the comparators mentioned earlier. For high resolution, the large amounts of comparators take up a large area and consume much power, while the Interpolating and Folding technique can overcome them. Besides, such many comparators have large input capacitive loading limiting the conversion speed and are sensitive to offsets affecting the accuracy. For these reasons, ADCs with resolution higher than 8-bit we rarely adopt the Flash architecture.

VREF VIN Thermometer Code Over Range -VREF 2N Comparators Pre-Encoder (2N-1) to N Encoder N-Bit Binary Digital Ouput

Figure 2.12 N-bit Flash ADC

2.3.2 Two-Step ADC

In order to solve the problems of chip area and power making Flash architectures impractical for higher resolution, the Two-Step (or Sub-Ranging) architecture [14][15] is adopted adequately and its block diagram is shown in Figure 2.13(a). It consists of a front-end S/H, a coarse MSB Sub-ADC of Flash type, a Digital-to-Analog converter (DAC), a Subtractor, and a fine LSB Sub-ADC of Flash type. As implied by the name, the conversion of this ADC architecture takes two steps for total N-bit resolution.

First, the S/H circuit samples the input signal and the first (N/2)-bit most significant bits (MSBs) are generated through the coarse Flash ADC. Subsequently, the DAC converts the first (N/2)-bit digital code back to an analog signal subtracted from the sampled input signal and is known as the residue. This residue is then

amplified by 2N/2 and is fed to the fine Flash ADC, so the last (N/2)-bit least significant bits (LSBs) are also determined. Therefore, final total N-bit resolution is achieved by combining (N/2)-bit MSBs and (N/2)-bit LSBs, and the conversion process is shown in Figure 2.13(b).

S/H

Coarse

Flash ADC DAC

Fine Flash ADC Output Latch VIN -bit -bit + -N-bit Digital Output

∑

N 2 N 2 00 01 10 11 VREF -VREF VIN 00 01 10 11 VREF -VREF Subtract and Expand by 24/2 Coarse Conversion Fine Conversion 01 MSBs 10 LSBs 4-bit Resolution : 0110 (a) (b) MSBs LSBs

Figure 2.13 (a) N-bit Two-Step ADC (b) Coarse and Fine Conversions

When compared with the Flash ADC, the Two-Step ADC has more potential for high resolution due to fewer numbers of the comparators. For total N-bit resolution, the Two-Step ADC only requires2 2⋅ N/ 2comparators, therefore, the chip area and power consumption are greatly saved than the Flash ADC. However, the speed of the Two-Step ADC is slower than the Flash ADC due to the larger latency delay, although the throughput rate approaches that of the Flash ADC.

2.3.3 Pipelined ADC

Pipelined architecture combines the characteristics of Flash and Two-Step architectures. In actuality, the Pipelined ADC could divide the number of conversions

into many steps relative to the Flash and Two-Step ADCs, and the quantization is distributed along a Pipelined signal chain resulting in an effective architecture for high-resolution and high-speed applications. By the idea of the Two-Step architecture, it is spread to a multi-stage architecture to construct the Pipelined ADC that has features of improving the throughput rate and tolerating the comparator offsets [16][17][18]. The block diagram of the Pipelined ADC is shown in Figure 2.14.

∑

Figure 2.14 N-bit Pipelined ADC with multi-stage

Figure 2.14 consists of a cascade of M low-resolution stages and the operation of each stage generating K-bit output codes is similar to the Two-Step ADC. The last Pipelined stage is followed by a Flash ADC providing P-bit. The input signal is first sampled by the front-end S/H circuit and then the held output is fed to stage 1. For the subsequent stages, their input signal is the amplified output residue from the previous stage and it repeats the same of above operations until all stages have executed completely. The S/H circuit in each stage allows each of the stages to operate concurrently; that is, at any time, in odd or even stages of the Pipelined ADC begin processing a new sample as soon as its residue is sampled by the following stage. Thus, the throughput rate is independent of the number of stages in the Pipelined

ADC. On the contrary, the conversion time for any given sample is proportional to the number of stages. This is because the signal must work its way through all of the stages before the complete output word is generated; that is, the total N-bit (M*K+P) digital code is finally obtained by adding the output code of each stage during some period of latency. Another feature of the Pipelined ADC is that the requirements of comparators in each stage can be relaxed by using inter-stage gain amplifiers and digital error correction. If the requirement of resolution is increased, the circuit complexity grows approximately linear compared with exponential growth in Flash and Two-Step ADCs. Furthermore, the effect of the mismatches being a limitation to resolution can be eliminated by calibration techniques. Therefore, the architecture of Pipelined ADC has good compromise between resolution and speed.

2.3.4 Key Circuit Components of Pipelined ADC

The block diagram of a typical Pipelined ADC has been shown in Figure 2.14. In this architecture, the core of circuit components is the operational amplifier (Op-amp). The front-end S/H mainly composed of the op-amp relaxes the timing requirements of next stage, which can accurately sample high- frequency input signals. The inter-stage gains from these amplifiers diminish the effects of non-idealities in all stages following the first stage. Because the accuracy requirement will lessen stage by stage, the dependency of accuracy on the most significant stage is stringent, even though a slight error in the first stage will propagate through the converter and result in a much larger error at the end of the conversion; that is, the op-amps in the first several stages primarily dominate the accuracy and the conversion speed of the Pipelined ADC. Besides, the S/H and MDAC circuits which equally require the components such as comparators, switches, or passive devices like capacitors also dominate the speed and

accuracy of the whole ADC.

2.4 Summary

The basic concepts of the analog-to-digital conversion and the performance metrics characterizing ADCs were introduced in this chapter. Then, three types of high speed ADC architectures were described explicitly and the Pipelined ADC was chosen in summary for better compromise among resolution, speed, chip area and power consumption than other ADCs. In general, the multi-bit /stage and multi-stage architecture can reduce non-ideal effects from the back-end Pipelined stages by deciding more bits in the front-end stages, but the stage gain amplifiers are the primary source of power consumption and the significant limitation to signal processing speed.

Chapter 3

System Analysis of The Pipelined

Analog-to-Digital Converter

3.1 Introduction

In this chapter, we will concentrate more detail on the Pipelined ADC. The basic principle including mathematical description and circuit structure are described. As mentioned earlier, the Pipelined ADC has the capability of tolerance to comparator offset due to the digital error correction, and the redundancy algorithm of 1.5-bit/stage structure is introduced as well. We also build the behavior model to analyze the characteristics of the Pipelined ADC. Furthermore, error sources which are classified into two causes of offset and non-linearity in each section of the Pipelined ADC are pointed out, where the capacitor-mismatch effect belonging to the non-linear error is avoidless and causes the most damage to the accuracy of Pipelined ADC. Therefore, a linearity-improving technique of capacitor-mismatch calibration is proposed to enhance the accuracy of the capacitor-ratio, reducing the distortion due to non-linearity effects.

3.2 Signal Processing of the Pipelined Stage

A prototype of Pipelined ADC introduced in section 2.3.3 consists of M similar cascaded stages and each stage resolves K bits. To develop a general view, we first concern a single stage. Figure 3.1(a) shows a conversion stage representing the i-th stage and it consists of an S/H circuit, a sub-ADC, a sub-DAC and a residue amplifier.

∑

Figure 3.1 (a) A single K-bit Pipelined stage (b) Vi toVi+1 residueplot

The analog input Vi is sampled and is compared with the reference voltages

Vi_REF of the Sub-ADC, then a rough digital code Di representing input level presents.

The sub-ADC with Y comparators generates Y+1 possible codes and it is followed by a reconstructing sub-DAC, which recovers code Di to a level of analog value Vi_DA. The analog level of Vi_DA depending on the value of Di can be one of (Y+1) possible voltages and is then subtracted from the sampled input value Vi. That is, the (Y+1) possible digital words for Di are the function of Vi and can be represented as integers: 0 for (00..0 ), 1 for (00..1),……up to Y for (11..1) [19]:

_ _ _ _ 0, [0] 1, [0] [1] . . , [ 1] i i REF i i REF i i REF i i REF i for V V for V V V D Y for V Y V <   _{≤ <}   =    − <  (3.1)

The residue signal (Vi-Vi_DA(Di)) is then amplified by the residue amplifier with a gain of Gi and the output is noted as Vi+1:

1 [ _ ( )]

i i i i DA i

V₊ = ×G V −V D (3.2) This amplification enables the residue signal to recover the full-scale range for next stage conversion. Furthermore, inverting of (3.2) gives Vi as the function of Vi+1:

1 _ ( ) i i i DA i i V V V D G + = + (3.3)

( 1) _ 1 2 _ 1 ( ) ( ) i DA i i i i DA i i i i V D V V V D G G G + + + + = + + (3.4)

Assuming there are total P stages, then (3.4) can be expanded to

( 1) _ 1 ( 2) _ 2 _ _ 1 1 1 ( ) ( ) ( ) ( ) i DA i i DA i P DA P i i DA i i i i i i P V D V D V D V V D Q G G G G G G + + + + + + − = + + + ⋅⋅⋅⋅⋅⋅⋅+ + ⋅⋅⋅⋅ ( 3 . 5 )

, where Q=VP+1/(GiGi+1…GP) represents the quantization error and it degrades as the number of converter stages (P) or the gain of the inter-stage amplifiers (Gi) increase.

Figure 3.1(b) illustrates how the residue value of each stage generates in the corresponding input range and the slopes of transfer curves equal the gain of Gi. This residue plot implies that the input signal is folded after quantization and amplified 2K for the same conversion range of the next stage. Figure 3.2 takes 4 stages with 1-bit/stage architecture for example and it is similar for the K-bit/stage utilization.

Figure 3.2 The 1-bit/stage example (a) transfer curve (b) trace diagram

First, the sampled signal VIN of stage_1 is located at node t1 in Figure 3.2(a), and the y-axis value of t1 is known as the output of stage_1, which is also the input of stage_2. Furthermore, the node t2 to t4 can be observed in the same principle recursively. When the input of each stage is larger than reference of 0, the resolved output code is 1; on the other hand, the resolved output code is 0. The trace diagram

of Figure 3.2(b) shows the signal processing stage by stage. The scale-up action for the residue signal can answer the conversion of next stage and can reduce the required number of reference voltages [20]. After the scale-up, the subtraction is required to prevent the scaling signal from exceeding the maximum range of references, which would cause the miss of decision levels. Generally, the transfer function corresponding to different input range of each stage can be expressed as

VOUT = ⋅2k VIN − ⋅D VREF (3.6)

, where D = 0 or 1 depends on the input range in this 1-bit/stage example; if k equals 4, then D = 0 or 1,…, or 15. Note that the Sub_DAC executes the amplification and the subtraction described in (3.6). Therefore, a circuit combining functions of the D/A, the subtraction, and the amplification is called the Multiplying-DAC (MDAC) and will be discussed in detail later.

The Pipelined ADC mainly operates in two phase of non-overlapping clock for conversion. One of two phase is operated for sampling the input signal, and the other is employed for holding and amplifying the residue voltage at the output. MDACs of consecutive stages operate concurrently in opposite phase to obtain high throughput rate, as illustrated in Figure 3.3.

The A/D phase shown at the latter half of sampling cycle is for the quantization of the Sub-ADC in each stage, and the quantized code of each stage is produced at different time. For a complete prototype of M-stage Pipelined ADC where the last stage only consists of comparators is shown in Figure 3.4. Since the K-bit codes resolved from each stage are not simultaneous, output buffers with different delay for each stage are required to synchronously merge K-bit/stage into a complete N-bit word at the ADC output. If there are more stages, the latency period before completely merging K-bit digital codes from different stages is longer. Therefore, the Pipelined ADC may be inappropriate for applications where the larger latency is not tolerated. Finally, the logic for digital error correction is usually employed to relax the requirements of each stage and it will be introduced explicitly in the section of 3.4.

S/H VIN Stage 1 Stage 2 Stage M-1 K-bit Flash ADC Stage M Output Buffer Digital Error Correction

K-bit (MSB) K-bit K-bit K-bit (LSB)

DN-1 D0

Clock Generator

Figure 3.4 M-stage Pipelined ADC with K-bit/stage architecture

3.3

Error Sources Consideration in One Stage

T he 2-bit/stage residue transfer curve and conversion characteristic of the Pipelined ADC are shown in Figure 3.5. Ideally, the transition voltages are located at -1/2VREF, 0, and 1/2VREF, where 2VREF represents the full-range of the signal. The plot shown in Figure 3.5 is linear [21] without errors consideration, however, there

exists imperfections in actual circuit implementation.

The primary error sources in a Pipelined ADC are presented by the non-idealities of the Sub-ADC and Sub-DAC, as well as that of the S/H. These non-idealities limiting ADCs performance mainly include offset errors and gain errors in S/H circuits or residue amplifiers, the non-linearity of Sub-ADC and Sub-DAC, and op-amp settling-time errors.

VREF -VREF -VREF 0 VREF Vi+1 DOUT 0 (a) (b) -VREF/2 VREF/2 00 01 10 11

-VREF -VREF/2 0 VREF/2 VREF

00 01 10 11 VIN Vi

Figure 3.5 Ideal 2-bit/stage (a) residue transfer curve (b) conversion characteristic

3.3.1 Non-idealities in the Sub-ADC

The non-idealities in the Sub-ADC are mainly the comparators offsets, which leads to a decision-level shift of the Sub-ADC. When the close values of two inputs are compared, the comparators may make a wrong decision and a wrong reference voltage will be subtracted from the input if the offset errors exist, which result in the threshold level of the Sub-ADC to shift. For the 2-bit/stage example, this effect of threshold-level shift is shown in Figure 3.6 and can be tolerated to a certain extent by adopting digital error correction technique which will be discussed in detail later. The

offsets are sometimes caused by the residue amplifier and can reflect on the transfer function (3.2) as follows: 1 1 [ _ ( ) _ ] _ ( ) _ i i i i i DA i i os i i DA i i os i V V G V V D V V V D V G + + = × − − => = + + (3.7)

The input V1 of the first stage can be expressed as

2 _ 2 3_ 3 _ 1 1_ 1 1 1 2 1 2 1 ( ) ( ) ( ) ( ) DA DA P DA P DA P V D V D V D V V D Q O G G G G G G ₋ = + + + ⋅⋅⋅⋅⋅⋅⋅+ + + ⋅⋅⋅⋅ (3.8)

Therefore, the entire ADC system has a dc offset of

_{1_} 2 _ 3_ _ 1 1 2 1 2 1 os os P os os P V V V O V G G G G G G ₋ = + + + ⋅⋅⋅⋅⋅+ ⋅⋅⋅⋅ (3.9)

Furthermore, the amplified residue must equal the conversion range of the next stage, and we can observe that if the deviation in the residue characteristic exceeds or is within the maximum output range, it separately results in missing decision level (i.e. wide code) and missing code, which can not be compensated by digital error correction. Besides, the transition magnitudes of residue transfer curve are constant in spite of offset errors with deviation.

Figure 3.6 2-bit/stage with offsets (a) residue transfer curve (b) conversion

3.3.2 Non-idealities in the Sub-DAC

VREF -VREF -VREF 0 VREF Vi+1 DOUT 0 (a) (b) -VREF/2 VREF/2 00 01 10 11

-VREF -VREF/2 0 VREF/2 VREF

00 01 10 11 VIN Vi ideal actual VREF -VREF -VREF 0 VREF Vi+1 DOUT 0 (c) (d) -VREF/2 VREF/2 00 01 10 11

-VREF -VREF/2 0 VREF/2 VREF

00 01 10 11 VIN Vi ideal actual

Figure 3.7 Residue transfer curve and conversion characteristic of 2-bit/stage

with gain error (a) (b) larger and (c) (d) smaller than 4

The non-idealities in the Sub-DAC, which combines the functions of S/H, subtraction, and amplification, include offsets, gain error, and non-linearity. In the Pipelined ADC popularly using the switch-capacitor technique, these error sources are mainly from charge-injection, capacitor-mismatches, the finite op-amp gain and bandwidth. The offset errors of the Sub-DAC only contribute a constant offset value to the ADC. On the contrary, the gain error and the non-linearity of the Sub-DAC

determine the performance of linearity in the whole ADC. The gain errors in each stage result from two causes: one is the capacitor-mismatch between the sampling capacitors and the feedback capacitors in the MDAC, and the other is the limited DC gain of the operational amplifier. For a given plot of the Pipelined stage with gain error is shown in Figure 3.7, and we can observe that the gain errors in the residue transfer curve will cause the output range to be larger or smaller than the conversion range of the following stage. As a result, wide codes and missing codes occur separately.

The non-linearity of the Sub-DAC produce differences in the transition magnitudes of residue transfer curve and is the most stringent issue for the Pipelined ADC. It involves various parts of non-linearity factors in MDACs and can be seen in Figure 3.8. This effect results in both wide code and missing code, which make the conversion characteristic as a zigzag line. To overcome these non-linearity errors, various analog or digital calibration techniques [22][23][24][25][26] are employed to improve the linearity of the conversion characteristic.

Figure 3.8 2-bit/stage with non-linearity in MDAC (a) residue transfer curve (b)

3.4 Digital Error Correction with Stages Redundancy

We can realize that the Pipelined ADC is highly sensitive to non-idealities of threshold offsets, gain errors, and the non-linearity discussed in last section. To build the Pipelined ADC with a large tolerance to components non-idealities, the redundancy of stages is introduced in this section by making the sum of the individual stage resolution greater than the total resolution. When the redundancy is removed by digital error correction algorithm, it can be adopted to eliminate the effects of the

Sub-ADC non-linearity and inter-stage offsets on the overall linearity. In many previous implementations adopting digital error correction algorithm do

both addition and subtraction to correct errors. Since subtraction is equivalent to addition with negative offsets, the required correction logic can be simplified through the introduction of offsets that reduce the requirement for the correction logic doing subtraction. As mentioned in section 3.2, the comparator offset and stage-gain error may cause the residue to exceed the conversion range of the next stage, even more out of range in subsequent stages, and thus determine wrong output codes [27]. In order to solve this over-range problem, we can increase the input range of each stage beyond the normal output range of the previous stage or reduce the inter-stage gain respect to the original design [28]. Two approaches of digital error correction algorithms mentioned above are shown in Figure 3.9.

The residue transfer curve of approach A implies that there are two extra comparators comparing in two input ranges of top and bottom; that is, the input range can be increased by designing the number of comparators Y>Gi-1, where Y=Gi-1 in normal design. This approach can be verified to have an over-range capability of ± 2VREF /Gi, which means the tolerable range of comparator offset.

Figure 3.9 Two types of digital error correction for 2-bit/stage

Approach B reduces the inter-stage gain and adopts one redundant comparator instead of the normal design. In this case, Y=Gi-2, and this approach is like a redundant signed digit (RSD) algorithm [16][17][18] as well as the architecture of K.5-bit/stage, where K=1, 2, 3….etc. Furthermore, approach B can be verified to have an over-range capability of ±2VREF /2Gi.

As a summary, the reduced inter-stage gain algorithm is adopted in this thesis for the reason of fewer comparators, which consume less power and area, as well as the reason for high speed requirement.

To illustrate the digital error correction of approach B in more detail, we take a 2-bit/stage for example and Figure 3.10 shows the block diagram.

∑

∑

∑

Figure 3.10 Block diagram of one stage with offset in ADC and DAC

First, when the inter-stage gain is reduced to 2, the residue transfer plot is compressed between the output range of 1/2VREF and -1/2VREF, as shown in Figure 3.11(a). Even if the comparator offset shown in Figure 3.11(b) occurs, the residue output range is still within VREF and –VREF, and then the following stage will correct the output codes by addition or subtraction operation.

Figure 3.11 Residue plot with inter-stage gain of 2 (a) without offsets (b) with offsets

Second, since subtraction is equivalent to addition with offset, we can intentionally model a maximum offset of 1/2 LSB (VREF/4) to both Sub-ADC and Sub-DAC. This adding offset uniformly shifts the location of the decision levels to the