Accuracy Requirements of One Pipelined Stage

To achieve the desired conversion rate, resolution, and linearity, each Pipelined stage must be designed carefully such that non-ideal effects do not excessively degrade the overall performance. Therefore, the accuracy requirements of one stage are all critical to the ADC performance.

4.2.1 Op-amp Requirements

In the Pipelined ADC, the accuracy requirement of each stage is different because the resolved resolution decreases down stage by stage. For example, an N-bit ADC with the effective resolution of n-bit/stage, the first stage has to achieve N-bit accuracy and is the most significant for whole ADC linearity. However, the next stage meets only N-n bits accuracy requirement, which is further reduced n-bit/stage for the following stages. Although more errors are accumulated in latter stages, the reduced stage resolution for accuracy means that design constraints in latter stages are more relaxed; that is, in terms of this viewpoint, the constraints of op-amp gain accuracy, op-amp bandwidth, op-amp settling time, capacitor matching (DAC accuracy), and thermal noise are more relaxed in latter stages.

Figure 4.1 Operation of adjacent Pipelined stages

In Figure 4.1, the adjacent Pipelined stages are depicted that the stage_i is in the amplification mode, while stage_i+1 is in the sample mode. For a given total resolution of N bits, the per-stage resolution of n, and op-amp non-idealities, the relationship between the input and output of stage_i can be known as

( ) constant for the SC configuration), and A represents the finite op-amp gain.

F

Because the i-th stage resolves n-bit, the ideal inter-stage gain Gi can be known as (2 1)

, where Equation (4.4) depends on the matching of capacitors.

In order to achieve total N-bit linearity for the first stage where the accuracy is significantly demanded, the finite gain error in the inter-stage amplification should be theoretically less than 1/2LSB for safe design, and the finite gain error is defined as

_{actual ideal} 1 , then combine (4.5) and (4.6), the limit of finite op-amp gain is yielded as following

1 1 1

If Cop-amp is ignored, Equation (4.7) equals 2^N+1+n and is the minimum requirement of A for the first stage. In practice, the op-amp gain should be much larger than this value since errors caused by other sources such as incomplete amplifier settling and capacitor-mismatch are not taken into account.

After realizing that how the accuracy is limited by the finite op-amp gain, the error caused by the finite settling time is further defined. We first consider Figure 4.2 [37], the speed constraints influencing the accuracy include the slew time of large signal and the settling time of small signal. The slew time is related to the bias current and load capacitance of the op-amp, as well as the signal level; while the settling time depends on the unity-gain frequency (f^μ) and phase-margin of the op-amp, the settling error must be less than 1/2LSB to achieve N-bit resolution

^/ 1 1 2 2

settle

T

e^{− τ} < ⋅ N (4.9) According to (4.9), we can obtain the required minimum unity-gain frequency f^μ

( 1) 2 ( 1) 2

, where Tsettle is the allowed settling time and is usually 75%~90% of half conversion

period [28] ( 1

In general, the margin of 10%~25% is conserved for the non-overlapping of Φ_s and Φh, as well as for the slew time of a slew-rate limited op-amp. Therefore, total unstable time in Figure 4.2 can be estimated by

_{unstable slew settle} V^step ( 1) 2

T T T N ln

SR τ

= + = + + ⋅ ⋅ (4.11) We can observe from Equation (4.10) and (4.11) that more resolution for N and n, the larger bandwidth f^μ and Tsettle are required to sustain the speed and accuracy of the Pipelined ADC.

4.2.2 Capacitor Requirements

In the Pipelined ADC, the required matching of sampling and feedback capacitors in MDACs are determined by the required DAC accuracy. Generally, the capacitors CS and CF are not equal exactly due to the process variation.

We assume that the value of capacitors deviates by ΔC, which makes Equation (4.12) sets the requirement of the MDAC in the first stage, where ΔC/C for each capacitor must be less than 1/2^N to ensure that ΔVDAC is less than 1LSB.

1 2^N C

∆ <C (4.13) In addition to above deterministic errors, there are also random errors which

mainly result from the thermal noise KT/C in SC circuits. Assuming this random error much less than 1LSB to maintain sufficiently SNR for N-bit accuracy requirement.

^{2 ,1 1}

(

)

total 2N LSB

σ << = (4.15) Notice that the noise contribution is reduced stage by stage due to the accumulated inter-stage gain. Therefore, the constraint of thermal noise mainly from ON-resistances of the switches and op-amp is most stringent for the first stage, and is relaxed down the subsequent stages.

As we know, larger capacitors tend to have better matching property and less KT/C contribution than smaller capacitors. However, smaller capacitors provide less loading and faster settling for enabling high speed. That is, we can reduce the sampled thermal noise by increasing the size of sampling capacitors, nevertheless, the power consumption also increases and output settling is more limited at the same time.

As a result, there exists a tradeoff when determining the capacitor size. In the design of ADCs, thermal noise power is necessarily designed smaller than the power of the quantization noise which had been shown to be VLSB2

/12. Thus, this sets a lowest limit for the capacitor value of C as follows [38].

4 ₂12 ²

combined effects of quantization noise and thermal noise can be set an upper bound as prototyped ADC. These circuits which include the operational amplifiers in the front-end S/H and MDACs, comparators in 1.5-bit and 2-bit Flash ADCs, even the switches, are overviewed with the general analysis and design techniques.

All analog circuits are fully differential, which have advantages of reducing the even-order harmonic distortions, the substrate noise, common-mode disturbances, charge-injection and clock-feedthrough effects, and have larger dynamic range.

4.3.1 Input-Stage Sample-and-Hold Circuit

The S/H of input-stage dominates the speed and linearity of whole Pipelined ADC. The speed means sampling rate, while linearity means characteristics such as signal-to-noise ratio. Most CMOS S/H circuits are based on the switched-capacitor technique. Therefore, before introducing the S/H with precharging technique, we first concern the switched-capacitor technique which is critical for the design of the ADC.

4.3.1.1 Switched-Capacitor Technique

The switched-capacitor (SC) technique is recently pervasive in highly integrated,