Chapter 5 Testing Setup and Measurement Results
5.3 Measurement Results
First, the measured 10-bit output data of this testing ADC is captured and stored by the logic analyzer. Figure 5.8(a) and (b) show the presented 10-bit codes and the decimal-recovered chart when applying a differential sinusoidal input signal.
(a) (b)
Figure 5.8 Measured results of (a) 10-bit codes (b) decimal-recovered sine wave
From the measured time-domain results shown in Figure 5.8, the frequency-domain showing linearity is calculated by collecting 65536 samples of the input signal and performing a 65536-point fast Fourier transform (FFT). At the sampling rate of 80MHz with 1MHz sinusoidal input, Figure 5.9(a) and (b) show the linearity comparison of capacitor-swapping off and on illustrated in the section 4.3.3.
When we apply logic 0 to this testing ADC, the operated conventional work shows peak SFDR of 43.2dB and peak SNDR of 33.57dB in Figure 5.9(a); when we apply logic 1, the capacitor-swapping operation of MDACs is enabled, hence, the better peak SFDR of 50dB and peak SNDR of 42.73dB is shown in Figure 5.9(b) than the conventional work.
(a) (b)
Figure 5.9 Comparison of FFT spectrum between (a) conventional operation and (b) capacitor-swapping operation
From Figure 5.9, we can know that harmonic distortions are mainly caused by the non-linearity effects of actual circuits. The worst reason is that the DC gain of op-amps at the highest output swing is no longer large enough to meet the required specification. Besides, the charge injection of signal-dependent error and the drift of common-mode which will accumulate stage by stage are also the possible reasons.
Finally, even-order harmonics should be suppressed for the differential topology while the 2nd harmonic is larger than the 3rd harmonic in the measured FFT spectrums. We find that this phenomenon results from the mismatch of input differential signals, which is because the applied input signal from the instrument has slight distortion and imperfect differential property, and furthermore the process variation of input differential devices also leads to the match issue, even though the layout skill of common-centroid had been used. In Figure 5.10, the measured SNDR with different sampling frequencies and input frequencies Fin are shown, and the maximum operation frequency is 100MHz with capacitor-swapping operation.
Figure 5.10 The measured SNDR against the sampling frequency
5.4 Summary
Table 5.1 summarized the measured results of this ADC with the innovative MDAC.
Parameters Measured Results
Process TSMC 0.18μm CMOS Mixed-Signal
Supply Voltage 1.8 V
Input Range ±0.6V Fully differential
Sampling Frequency 80 MHz
SNDR@FIN=1MHz (Capacitor-Swapping) 42.73 dB
ENOB (Capacitor-Swapping) 6.81 bits
SNDR@FIN=1MHz (No Capacitor-Swapping) 33.57 dB
ENOB (No Capacitor-Swapping) 5.28 bits
Chip Size 1.87mm2
Power Dissipation 88mW
Table 5.1 Summary of measured results of this testing chip
Chapter 6
Conclusions
6.1 Conclusions
Among numerous architectures of CMOS ADC, the Pipelined ADC is the most popular solution for its capability of medium-accuracy/high-speed or high-accuracy/
high-speed. Furthermore, the CMOS and SC implemented Pipelined ADC makes the integration of digital/analog circuits on the same chip with the same supply voltage to be easy, even for the SoC. In this thesis, a 10-bit, 100MS/s Pipelined ADC with 1.8V power supply had been designed, laid-out, fabricated, and measured completely.
There are many non-idealities in actual circuit implementations and we consider these effects with design. The front-end S/H with precharged technique is employed for reducing requirements of the op-amp; the 1.5-bit/stage architecture with the digital error correction is adopted for tolerating comparators offsets. With the innovative technique of capacitor-mismatch calibration, the role of the feedback capacitor in MDACs is no longer fixed, which averages out the capacitor-mismatch errors and improves overall ADC linearity. All approaches mentioned above are desired for less power consumption and die area, higher conversion speed and resolution accuracy.
This testing chip was fabricated by TSMC 0.18um 1P6M CMOS process technology. For 1MHz input signal frequency, the measured SNDR is 44dB at 60MHz sampling rate, 42.7dB at 80MHz sampling rate, and 37.88dB at 100MHz sampling rate. The measured results of the maximum conversion rate are worse than the simulation, because there are many extra parasitic capacitors that the post-layout extraction didn’t extract out, and the measuring skills are not good enough, as well as
other reasons like the instruments issue and the high frequency effects that need to discover and discuss. Furthermore, when measuring the chip, the applied input signal itself already has distortions due to instruments and devices interference, which is especially sensitive to the signal wire of clock. Therefore, when designing the PCB, we must consider and take care of the problem of clock disturbances to the input signal, which is more severe for higher frequency of clock or input signal.
6.2 Future Works
Nowadays, the trend of Pipelined ADC design is toward the direction of higher resolution, faster speed, lower power consumption, and smaller chip area. As the scaling process technology, the reduced supply voltage brings benefits to digital circuits whereas makes the design of analog circuits more difficult.
For higher resolution accuracy, although a wide variety of calibration methods had been proposed and we can develop to implement, few of them can be operated with high conversion rate exceeding 100MHz due to an extra clock cycle for calibration.
For faster conversion speed, a method of time-interleaved which can compensate the speed constraint of the op-amp can be adopted by combining more parallel channels instead of single channel, while matching issues, such as timing skew in multiple channels are the indispensable problem to increase the sampling rate much greatly.
Finally, with the reduced supply voltage, we have to do more efforts to achieve high accuracy and low power at the same time. In order to reduce total power consumption, scaling down of the capacitors stage by stage will be necessary.
Therefore, the design spec. combining high speed and high resolution of an ultra low power ADC will become the most significant topic and have more challenges for the future work.
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