Chapter 1 Introduction
1.2 Thesis Organization
This thesis is organized into six chapters and is described as following.
Chapter 1 briefly introduces the analog-to-digital converters and this thesis.
Chapter 2 begins with the concepts of analog-to-digital conversion and performance metrics used to characterize ADCs. Then, several high-speed ADC architectures are introduced and the evolution of them is described. Finally, the Pipelined architecture is chosen and we focus on it in summary.
Chapter 3 concentrates on the characteristics of the Pipelined ADC, which is described in detail from its operation principle to the actual implementation of each stage including 1.5-bit/stage architecture with digital error correction. Furthermore, the behavioral models simulations of a Pipelined ADC are built to obtain the requirement of design, and we analyze the effects of circuit components non-idealities.
Finally, the proposed technique of capacitor-mismatch calibration is introduced, and it was applied in our design to prevent overall resolution from degrading due to the capacitor-mismatch effect.
Chapter 4 illustrates the design and implementation of the Pipelined ADC with capacitor-mismatch calibration technique, where key circuit components will be introduced in detail. Among them are the operational amplifier, the bootstrapped switch, the comparator, the input stage sample-and-hold circuit (S/H), the 1.5-bit/stage circuit, the 2-bit flash ADC, and digital circuits including clock generator.
The transistor level simulation results of each circuit are presented, and the simulation
of whole Pipelined ADC, as well as its layout and floor plan are also shown at the end of this chapter.
Chapter 5 presents the measurement environment, including component circuits on the DUT (device under test) board and the required instruments. Finally, the measured results of the prototype chip described in Chapter 3 and Chapter 4 are shown and summarized.
Finally, Chapter 6 is the conclusion for this work. Some suggestions and improved recommendations are proposed for the future work.
Chapter 2
Fundamentals and Architectures of Analog-to-Digital Converters
2.1 Introduction
In this chapter, we first introduce the concepts of analog-to-digital conversions and discuss some fundamental issues in the design of data converters, which are the performance metrics to characterize ADCs. Second, some of the prominent ADC architectures for high-speed applications are the surveyed subjects and each of them has different trade-off among speed, resolution, power and area. At the end of this chapter, we summarize and focus on the most appropriate architecture to meet our target specification.
2.2 The Concept and Performance Limitations of A/D Converters
In signal transmission systems linking between the nature world and the digital processors, data converters including ADC and DAC are the devices translating the analog signals into digital codes or performing the reverse operation.
Figure 2.1 shows an overall signal transmission system [4]. The original analog signal (a) is filtered by an anti-aliasing filter (b) to remove any high-frequency components that may cause an effect known as aliasing. Then, the signal is converted into a digital form (d) by the analog-to-digital conversion (c) separated into two operations: sampling and quantization. Sampling operation transforms the continuous
and infinite valued signal into a corresponding discrete time signal, while quantization operation quantizes the discrete time signal to have a certain digital code level for each discrete period, which is generally expressed as conversion period. However, some ADC architectures, such as Flash ADC, can execute sampling and quantization simultaneously to achieve very high throughput rates.
Figure 2.1 Signal characteristics caused by data conversion
2.2.1 Quantization and Error
The analog-to-digital conversion tends to quantize the sampled input analog signal into an N-bit digital word, which is known as the total resolution. That is, the full range of analog signal defining as VFS is divided into several smaller sub-ranges (segments) according to the numbers of quantization steps 2N, and these sub-ranges are uniform in size ideally. Figure 2.2 illustrates the ideal conversion transfer curve of an N-bit ADC. During the conversion process, the value of signal in which segment range is decided and sends a set of corresponding output digital word representing the sampled input signal [5]. Furthermore, the quantization step size of each sub-range are also referred to as one least significant bit (LSB), and VLSB is the difference of two transition voltages defined as
2
FS
LSB N
V =V (2.1)
, and the transition voltages can be written as
2 ,
FS
tn N
V =V ⋅n n∈
{
0,1, 2,..., 2N}
(2.2)By the way, if the circuit is operated in fully differential, then VFS=2VREF, where VREF
is the analog reference signal applied to ADCs.
Figure 2.2 Ideal conversion characteristic of a N-bit ADC
Since the analog input signal is continuous-valued and the digital output is discrete-valued, this signal ambiguity produces what is known as quantization error, Qe, is defined as the difference between the actual analog input and the value of the quantized staircase given in voltage. In Figure 2.3(a), we take an ideal 3-bit ADC conversion for example and shift the transfer curve like Figure 2.2 to the left by 1/2 LSB [4], showing in Figure 2.3(b). The midpoints of the staircase curve defining Vstaircase can be calculated by
2
FS
staircase N LSB
V = ⋅D V = ⋅D V (2.3)
, where the quantization error can be generated by subtracting the value of the staircase from the dashed line, and Qe is represented as
e IN staircase
Q =V −V (2.4) The result can be seen in Figure 2.3 (c), where a sawtooth waveform is centered about zero.
Figure 2.3 (a) An Ideal 3-bit AD quantizer (b) Transfer curve (c) Quantization error centered about zero
As mentioned in Figure 2.3, quantization errors even occur in ideal A/D converters. Clearly, the average of Qe is zero and is limited to ±0.5VLSB, therefore, we can model these errors as being equivalent to an additive noise source and find its power. We assume that the quantization error Qe is a random variable uniformly distributed between ±0.5VLSB. The probability density function (PDF) for such an error signal will be a constant value, as shown in Figure 2.4. Hence, the quantization noise power (variance) PQ can be calculated by
0.5 2
2 2
0.5
( ) 1
12
LSB LSB
V LSB
Q Q
LSB V
P q f q dq q dq V
V
∞
−∞ −
=
∫
=∫
= (2.5), and the R.M.S value of the quantization noise equals VLSB/ 12.
Figure 2.4 Assumed probability density function of the quantization error Qe
Finally, we can conclude that the quantization noise power is independent of the sampling frequency, fs; on the contrary, it is proportional to the size of VLSB. The size of VLSB is halved and the noise power decreases by 6 dB for each additional bit-resolution in the A/D converter.
2.2.2 ADC Performance Metrics
In this section, some commonly used definition indicating the performance of the analog-to-digital converters are introduced as below, which can be separated into dynamic characteristics and static characteristics [4][6][7].
Dynamic Characteristics:
Resolution
The “ideal” resolution of ADCs is defined as the numbers of distinct analog input sub-ranges corresponding to the different output digital words. For a fixed full-scale analog input range, an N-bit resolution implies that the converter can resolve 2N distinct input segments, and the high resolution can resolve smaller sub-ranges of signals than the low resolution. Nevertheless, the “actual” resolution is generally degraded by either noise or non-linearity in ADCs, so it is also treated as effective number of bits (ENOB) of the ADC output digital bits.
Signal-to-Noise Ratio (SNR)
A sinusoidal input signal is usually used to characterize a data converter. The signal to noise ratio (SNR) means the ratio of the signal power to the noise-floor power at ADCs output, and the relationship is expressed as
_ ( )
We assume that the sampled sinusoidal input has the form as
VIN( )k = Asin 2
(
πf kTi⋅ s)
(2.7), and it decreases from this best value for reduced input signal levels [8].
Signal-to-Noise＋Distortion Ratio (SNDR)
The signal to noise plus distortion ratio (SNDR) is often used to measure the performance of an ADC. When a single frequency sinusoidal signal is applied to the ADC system, the fast Fourier transform (FFT) of the system output generally contains a tone at the fundamental (input) frequency. Due to distortion, the output also contains signal tone including aliasing at all harmonics of the input frequency. As a result, the SNDR of the ADC is defined as the ratio of the signal power at the fundamental frequency to the total power of non-ideal effects, including all harmonic distortions (HD) and all of the noise sources presented at the output, which is expressed as below
_ ( ) actual resolution influenced by the combined non-ideal effects to what extent, which
is calculated by the value of SNDR
1.76
6.02
ENOB= SNDR− (2.10)
Spurious-Free Dynamic Range (SFDR)
The spurious free dynamic range is defined as the ratio of the fundamental signal component to the largest distortion component being usually at 3rd harmonic in a specified frequency range and expressed as
10 _ ( )
_ ( )
20 IN signal RMS
Max HD RMS
SFDR log V V
= dB (2.11)
Finally, we can easily get much more understanding among SNR, SNDR, and SFDR by the FFT spectrum plot illustrated in Figure 2.5, where S is the fundamental frequency of the input signal, D are the harmonic distortion components, and N is the noise floor.
Figure 2.5 The power spectrum with the signal, distortions and noise
Furthermore, SNR and SNDR in Figure 2.5 are respectively depicted as S S
SNR SNDR
N N D
= =
+ (2.12)
Dynamic Range (DR) and Effective Resolution Bandwidth (ERB)
Dynamic range (DR) is a measure of the range of input sinusoidal signal amplitudes, which is also a useful performance benchmark. We apply a single frequency signal to the ADC and vary its amplitude, the definition of dynamic range is the ratio of the input signal level with maximum SNR to the input signal with 0dB SNR, as shown in Figure 2.6(a). SNR with 0dB means that the input signal is too indistinct to be recognized and is the minimum detectable power. If the noise power is independent of the signal level, the dynamic range is equal to the SNR at full scale.
Nevertheless, in most conditions, the noise power increases as the signal level increases. In general, the actual maximum SNR is less than the defined dynamic range [5][8]. Figure 2.6(a) also indicates that the harmonic distortions increases as the increasing signal level, and then the value of SNR is severely degraded by distortions.
0 dB
Figure 2.6 (a) Dynamic range (b) Effective resolution bandwidth
Figure 2.6(b) shows that SNDR gradually decreases as the input signal frequency increases. The maximum input frequency that can sustain efficient SNDR dropping about 3dB is called the effective resolution bandwidth (ERB). This bandwidth is limited by Nyquist Sampling Theorem to avoid aliasing.
Static Characteristics:
Offset Error
ADCs have an Input-Output transfer characteristic of quantization that approximates a straight line, and it progresses from low-to-high in uniform steps ideally. However, the practical transfer steps might be not uniform ideally. The imperfections cause errors or non-linearity performance in ADCs. In Figure 2.7, an error which causes the actual steps to shift horizontally from their ideal positions by a constant amount is called the offset error.
Figure 2.7 Offset error for quantization
Gain Error
Gain error or scale factor error, seen in Figure 2.8, is the difference between the slope of a straight line drawn through the midpoints of the actual transfer steps and the ideal slope of 1 [9].
Ideal Actual
Analog Input Digital
Output
Gain Error
Figure 2.8 Gain error for quantization
Differential Non-Linearity (DNL) and Missing Code
Each width of quantization steps may not equal to one LSB (1LSB = AFS/2N) due to the non-idealities in ADCs. Then, the differential non-linearity (DNL) is defined as the value of each step width deviating from the ideal step width as Figure 2.9
Figure 2.9 DNL for quantization
ADCs possessing a DNL that is equal to -1LSB are guaranteed to have a missing code, as illustrated in Figure 2.10. The step width corresponding to Codek is completely missing; thus, the value of DNLk is -1LSB.
Figure 2.10 Missing code for quantization
On the contrary, DNL larger than +1LSB is not guaranteed to have a missing code, though in all probability a missing code will occur.
Integral Non-Linearity (INL)
The integral non-linearity (INL) is defined as the total deviation of the middle point of step from the ideal value that ADCs tend to approximate. Unlike the DNL, INL can be any values and can be expressed in Figure 2.11, where Vmd_n is the middle point of the n-th step, and Vid_k is the ideal middle point value of this step. From another view-point, INLn equals to the summation of DNL0 to DNLn.
0 n
i i
DNL
∑
=Figure 2.11 INL for quantization
Finally, DNL and INL are expressed in the unit of least significant bits (LSBs),
and ADCs main non-linear effects including DNL, INL as well as Missing Code will cause the non-monotonic characteristic and enhance distortions.
2.3 ADC Architectures Overview
A/D converters can be classified into two types of Nyquist-rate and Over-sampling. According to the speed and accuracy for different applications, the architectures of Nyquist-rate ADCs can be roughly divided into three categories:
low-to-medium speed, medium speed, and high speed, as shown in Table 2.1.
Choosing each of them has different trade-off among speed, resolution, power and area for the best solution [10][11]. Generally, the Over-Sampling architecture of the ADC is adopted for high resolution (16-bit above) design [10]. In this section, the architectures of Flash, Two-Step and Pipelined will be discussed for their close relationship.
Table 2.1 A/D Converter Architectures
2.3.1 Flash ADC
The Flash ADC [12][13] is the standard approach for realizing very-high-speed
converters. For N-bit resolution, the input signal of a Flash ADC is simultaneously fed to 2N comparators in parallel, each of the comparators samples the input signal and compares the signal to its corresponding reference value, as shown in Figure 2.12.
The series of reference voltages are generated equally spaced by dividing a resistor string connected between +VREF and –VREF and are applied to one input of each comparator. Any comparator connected to a resistor string node where the reference of each comparator is larger than the input signal will have outputs of 1, while those connected to nodes with reference voltages less than the input will have outputs of 0, and the level of the interface between 0s and 1s would indicate the value of the signal.
The set of 2N comparator outputs is commonly referred to as a thermometer code since it looks quite similar to the mercury bar in a thermometer and is encoded to N-bit binary code word with an encoding circuit. Besides, the NAND gates called as the pre-encoder are also designed to remove the bubble error usually occurring near the transition point of the thermometer code. As seen from the Figure 2.12, the process of the input sampling and quantizing are operation in parallel. Thus, the Flash ADC can be capable of very high speed (high throughput and small latency) and its conversion time is only limited by the speed of the comparators.
The most main drawback to the Flash ADC is the huge requirement of hardware which grows exponentially with the increasing resolution, especially the comparators mentioned earlier. For high resolution, the large amounts of comparators take up a large area and consume much power, while the Interpolating and Folding technique can overcome them. Besides, such many comparators have large input capacitive loading limiting the conversion speed and are sensitive to offsets affecting the accuracy. For these reasons, ADCs with resolution higher than 8-bit we rarely adopt the Flash architecture.
VREF
VIN
Thermometer Code
Over Range
-VREF
2N Comparators
Pre-Encoder
(2N-1) to N Encoder
N-Bit Binary Digital Ouput
Figure 2.12 N-bit Flash ADC
2.3.2 Two-Step ADC
In order to solve the problems of chip area and power making Flash architectures impractical for higher resolution, the Two-Step (or Sub-Ranging) architecture [14][15]
is adopted adequately and its block diagram is shown in Figure 2.13(a). It consists of a front-end S/H, a coarse MSB Sub-ADC of Flash type, a Digital-to-Analog converter (DAC), a Subtractor, and a fine LSB Sub-ADC of Flash type. As implied by the name, the conversion of this ADC architecture takes two steps for total N-bit resolution.
First, the S/H circuit samples the input signal and the first (N/2)-bit most significant bits (MSBs) are generated through the coarse Flash ADC. Subsequently, the DAC converts the first (N/2)-bit digital code back to an analog signal subtracted from the sampled input signal and is known as the residue. This residue is then
amplified by 2N/2 and is fed to the fine Flash ADC, so the last (N/2)-bit least
Figure 2.13 (a) N-bit Two-Step ADC (b) Coarse and Fine Conversions
When compared with the Flash ADC, the Two-Step ADC has more potential for high resolution due to fewer numbers of the comparators. For total N-bit resolution, the Two-Step ADC only requires2 2⋅ N/ 2comparators, therefore, the chip area and power consumption are greatly saved than the Flash ADC. However, the speed of the Two-Step ADC is slower than the Flash ADC due to the larger latency delay, although the throughput rate approaches that of the Flash ADC.
2.3.3 Pipelined ADC
Pipelined architecture combines the characteristics of Flash and Two-Step architectures. In actuality, the Pipelined ADC could divide the number of conversions
into many steps relative to the Flash and Two-Step ADCs, and the quantization is distributed along a Pipelined signal chain resulting in an effective architecture for high-resolution and high-speed applications. By the idea of the Two-Step architecture, it is spread to a multi-stage architecture to construct the Pipelined ADC that has features of improving the throughput rate and tolerating the comparator offsets [16][17][18]. The block diagram of the Pipelined ADC is shown in Figure 2.14.
∑
Figure 2.14 N-bit Pipelined ADC with multi-stage
Figure 2.14 consists of a cascade of M low-resolution stages and the operation of each stage generating K-bit output codes is similar to the Two-Step ADC. The last Pipelined stage is followed by a Flash ADC providing P-bit. The input signal is first sampled by the front-end S/H circuit and then the held output is fed to stage 1. For the subsequent stages, their input signal is the amplified output residue from the previous stage and it repeats the same of above operations until all stages have executed completely. The S/H circuit in each stage allows each of the stages to operate concurrently; that is, at any time, in odd or even stages of the Pipelined ADC begin processing a new sample as soon as its residue is sampled by the following stage.
Thus, the throughput rate is independent of the number of stages in the Pipelined
ADC. On the contrary, the conversion time for any given sample is proportional to the number of stages. This is because the signal must work its way through all of the stages before the complete output word is generated; that is, the total N-bit (M*K+P) digital code is finally obtained by adding the output code of each stage during some period of latency. Another feature of the Pipelined ADC is that the requirements of comparators in each stage can be relaxed by using inter-stage gain amplifiers and digital error correction. If the requirement of resolution is increased, the circuit complexity grows approximately linear compared with exponential growth in Flash and Two-Step ADCs. Furthermore, the effect of the mismatches being a limitation to resolution can be eliminated by calibration techniques. Therefore, the architecture of Pipelined ADC has good compromise between resolution and speed.
2.3.4 Key Circuit Components of Pipelined ADC
The block diagram of a typical Pipelined ADC has been shown in Figure 2.14. In this architecture, the core of circuit components is the operational amplifier (Op-amp).
The front-end S/H mainly composed of the op-amp relaxes the timing requirements of
The front-end S/H mainly composed of the op-amp relaxes the timing requirements of