Operational Amplifier

The core component in front-end S/H stage and 8 subsequent stages of the Pipelined ADC is the operational amplifier, which actually has some limitations such as finite DC gain, finite bandwidth, stability, and linearity to be considered and analyzed in ADC design. For analog circuits, speed and accuracy are two of the most significant properties, and are dominated by the settling behavior of the op-amp. Fast settling requires high unity-gain bandwidth to achieve, whereas accurate settling requires high DC gain to support. Nevertheless, realization of an op-amp with high DC gain has been a difficult problem without sacrificing high unity-gain bandwidth in low-voltage CMOS process.

Architectures of the op-amp can be roughly classified into two of single-stage and multi-stage, and different architectures having their own ascendancy among above limitations are adopted for suitable purposes. A multi-stage architecture may have large DC gain and high swing for different stages functionality, however, it is not suitable for high-speed application since there is at least one pole in each stage, which decreases the bandwidth and stability of the feedback system. Popular architectures of single-stage such as telescopic and folded-cascode are usually designed for high- speed requirements, which are also capable of high gain due to cascode stage with large output impedance. Although the operation speed of telescopic op-amp is fastest, the output swing is severely restricted by a large amount of cascoded transistors, especially in low-voltage process. Therefore, a folded-cascode architecture which slightly improves small output swing and input common mode range in telescopic architectures and is more stable with lager bandwidth than multi-stage architectures due to only one dominant pole, is commonly adopted in high speed circuits. The performance such as speed and gain of the folded-cascode op-amp may be not the best

in all kinds of architectures, nevertheless, it can almost meet circuits requirements in all aspects for its good balance among gain, speed, and output swing.

As shown in Figure 4.12, a folded-cascode op-amp with PMOS input differential pair is adopted in the S/H stage as well as 8 Pipelined stages, and the fully-differential architecture has advantages of higher immunity to “environmental” noise, reducing even-order harmonic distortion, and doubling of the output swing.

M1

Figure 4.12 Fully-differential folded-cascode op-amp with gain boosting

In Figure 4.12, a gain enhancement method is employed without adding additional stages or stacking more cascode devices to increase the DC gain for higher resolution accuracy. This method is called gain-boosting [47][48][49] and is impedance. The small signal model in Figure 4.13(b) proves the enhanced impedance ROUT as follows

_{a a o}¹ ( _{a m}² _GS²)_o² _{1 2 2 1}

Figure 4.13 (a) Impedance boosting with feedback (b) Small signal model

Therefore, the open-loop gain of the fully-differential folded-cascode op-amp with gain boosting can be represented as

A=G_m×R_OUT (4.36) , where the transconductance Gm is approximately equal to gm1 and output impedance ROUT enhanced by boosting amplifiers of AGBN and AGBP can be calculated as

(

)

(

) (

)

OUT GBP m mb o o GBN m mb o o o

R ≈A g +g r r   A g +g r r r  (4.37) Assuming total output capacitance and resistance are CL and ROUT respectively, the frequency response of this folded-cascode op-amp is given by

( ) 1

From the unity-gain frequency, we can find the dominant pole as follows

1

, which locates at the output of the op-amp. Because of the single-stage topology, the second pole is far away from the unity-gain frequency, which should be designed with five to ten times of the sampling frequency. It is also worth noting that there are non- dominant poles at the “folding point”, i.e., the sources of M8 and M9, which are more far away from the origin than the architecture of NMOS input differential pair due to the effective small-signal gm of NMOS instead of PMOS. Total effect capacitance on the source of M8 contains CGS8, CSB8, CGD1, CDB1, CGD10 and CDB10, where CGD10 and CDB10 are significant to be considered because M10 must be wide enough to carry a large current with small overdrive voltage [39].

However, the output common-mode (CM) of the fully-differential architecture must be well defined, which is quite sensitive to devices mismatch and power-supply variations. Hence, a common-mode feedback (CMFB) circuit which can sense and compensate the error of output CM level is required for proper control. Figure 4.14 shows the implemented CMFB, which is designed with SC architecture to allow larger output swing and have no additional parasitic poles in the CM loop.

Φ1

In Figure 4.14, VCMREF is the desired output common-mode voltage, usually being half of the supply voltage. This circuit is operated by two non-overlapping phase ofΦ1 and Φ2, whereΦ2 is the feedback period of the op-amp. Capacitors C2

generate the average of the output voltages, which is used to create control voltage VCMFB for the op-amp current source of M10 and M11, and the desired DC voltage of VCMREF-VBIAS across C2 is determined by capacitors C1. If there are variations in CM voltages of VOUT+ and VOUT-, VCMFB coupling this variation senses error and returns VOUT+ and VOUT- to the desired CM level through the functionality of negative feedback. Furthermore, all switches are realized by CMOS transmission gates with minimum length to reduce charge injection effects, and capacitors C1 might be between one-quarter and one-tenth the sizes of capacitors C2 [10].

Figure 4.15 shows the simulation of the fully-differential folded-cascode op-amp, including open-loop gain and phase margin of AC response. Table 4.1 shows simulation results of five process corners.

TT process corner

◦Supply voltage:1.8

◦DC gain︰81dB

◦Phase margin︰61.5°

◦Unity gain freq.︰842MHz

@2pF load capacitor

Figure 4.15 AC response simulation of the op-amp

TT SS FF FS SF

DC Gain(dB) 81 79.7 80.4 83.3 82.5

PhaseMargin(deg) 61.5 65.2 63.4 63.3 64.3

Unity GB(MHz) 842 796 822 813 810

Table 4.1 Simulation of the op-amp in five process corners