Chapter 4 Design and Simulation of The Pipelined ADC With
4.7 Layout and Floor Plan
(a)
(b)
(c)
Figure 4.29 (a) Layout (b) Floor plan (c) Die photograph of the whole chip
The layout of this experimental prototype chip is shown in Figure 4.29(a), which occupies die area of 1.365mm × 1.368mm and consumes total power of 88mW. In the layout, we use the mirror symmetry to enhance the rejection of common mode noises in the fully differential circuits. Analog circuits are separated from the digital circuit, which are powered from the separated power supply. Figure 4.29(b) and (c) are the die photograph and floor plan respectively. Table 4.3 summarizes the simulation results of this prototype ADC.
Parameters Simulation Results
Process TSMC 0.18μm CMOS Mixed-Signal
Supply Voltage 1.8 V
Input Range ±0.6V Fully differential
Resolution 10 bits
Operation Frequency(max) 100 MHz
DNL(max)/INL(max) -0.55 LSB /-0.7 LSB
SNDR@FIN=1MHz 59.15 dB
ENOB@FIN =1MHz 9.53 bits
Chip Size 1.87mm2
Power Dissipation 88mW
Table 4.3 Simulation summary of this prototype ADC
4.8 Summary
In this chapter, the design process of the whole ADC, including circuit optimization, simulation, and layout are illustrated in detail. However, some effects can not be revealed in Hspice simulation; that is, after fabrication of the chip, matching property of input differential pairs and capacitors may be lost due to process variation, and there also exists a problem of parasitic capacitance due to metal wires.
Furthermore, when measuring the chip, noises from outside environment should be considered, which is treated as thermal noise and can not be known in simulation results of Hspice.
Chapter 5
Testing Setup and Measurement Results
5.1 Introduction
The Pipelined ADC with capacitor-mismatch calibration had been fabricated by TSMC 0.18um 1P6M CMOS Mixed-Signal process. In this chapter, the testing environment including the printed circuit board (PCB) and required instruments for measurement are shown. Finally, the measurement results are also presented and summarized.
5.2 PC Board Design and Testing Setup
Figure 5.1 Testing setup on PCB
First of all, the design of PCB is important, which also influences the performance of the testing chip. The scheme of testing setup used to evaluate the ADC performance in this work is depicted in Figure 5.1, which mainly consists of the
power supply regulator, the reference and bias voltage generator, the signal generator, the clock generator, and the logic analyzer.
The supply voltages 1.8V for both analog and digital parts of this testing chip are generated by the regulator shown in Figure 5.2, which is named as the LM317 adjustable regulator [52][53][54]. The input voltage of this regulator is connected to a 9V battery for smaller noise disturbance, and the output voltage is specified with 1.8V, which is adjusted by the resistor R1 as
1 1
2
1.25 1
OUT ADJ
V R I R
R
= ⋅ + + ⋅
(5.1) , where IADJ is the DC current that flows out of the adjustment terminal ADJ of the regulator.
Figure 5.2 Power supply regulator with bypass filter
Figure 5.3 Photograph of the testing ADC on PCB
Furthermore, the output of the regulator should connect different sizes of capacitors to bypass noises. The required DC voltages including bias, common-mode voltage, and reference voltages are generated through small resistors dividing 1.8V at regulator output. Figure 5.3 shows the photo of the PC board with the testing chip.
After completing PCB design, we then apply all signal sources to this testing ADC. The single-ended input signal is provided by the function generator, Agilent 33250A, which is shown in Figure 5.4(a). A single to differential device called SPLITTER is used to generate differential signals. Two DC couple devices called BIAS TEE are connected with two outputs of SPLITTER to add DC bias on differential signals. Figure 5.4(b) and (c) show the SPLITTER and BIAS TEE respectively. The required clock signal is generated by a pulse/pattern generator, Agilent 81130A, which is shown in Figure 5.5. The 10-bit output data is primarily captured and stored with 65536 points in the logic analyzer, Agilent 16702B, which is a window based instrument and is shown in Figure 5.6. Finally, the stored data is processed and analyzed by the Matlab program in the personal computer.
(a) (b) (c)
Figure 5.4 (a) Function/arbitrary waveform generator (b) SPILLTER (c) BIAS TEE
Figure 5.5 Pulse/pattern generator Figure 5.6 Logic analyzer
Figure 5.7 presents the pins configuration and assignments of this experimental
11 Vrefp In Reference voltage＞Vcm 12 Vrefn In Reference voltage＜Vcm 13 VDDA In Analog power supply
5.3 Measurement Results
First, the measured 10-bit output data of this testing ADC is captured and stored by the logic analyzer. Figure 5.8(a) and (b) show the presented 10-bit codes and the decimal-recovered chart when applying a differential sinusoidal input signal.
(a) (b)
Figure 5.8 Measured results of (a) 10-bit codes (b) decimal-recovered sine wave
From the measured time-domain results shown in Figure 5.8, the frequency-domain showing linearity is calculated by collecting 65536 samples of the input signal and performing a 65536-point fast Fourier transform (FFT). At the sampling rate of 80MHz with 1MHz sinusoidal input, Figure 5.9(a) and (b) show the linearity comparison of capacitor-swapping off and on illustrated in the section 4.3.3.
When we apply logic 0 to this testing ADC, the operated conventional work shows peak SFDR of 43.2dB and peak SNDR of 33.57dB in Figure 5.9(a); when we apply logic 1, the capacitor-swapping operation of MDACs is enabled, hence, the better peak SFDR of 50dB and peak SNDR of 42.73dB is shown in Figure 5.9(b) than the conventional work.
(a) (b)
Figure 5.9 Comparison of FFT spectrum between (a) conventional operation and (b) capacitor-swapping operation
From Figure 5.9, we can know that harmonic distortions are mainly caused by the non-linearity effects of actual circuits. The worst reason is that the DC gain of op-amps at the highest output swing is no longer large enough to meet the required specification. Besides, the charge injection of signal-dependent error and the drift of common-mode which will accumulate stage by stage are also the possible reasons.
Finally, even-order harmonics should be suppressed for the differential topology while the 2nd harmonic is larger than the 3rd harmonic in the measured FFT spectrums. We find that this phenomenon results from the mismatch of input differential signals, which is because the applied input signal from the instrument has slight distortion and imperfect differential property, and furthermore the process variation of input differential devices also leads to the match issue, even though the layout skill of common-centroid had been used. In Figure 5.10, the measured SNDR with different sampling frequencies and input frequencies Fin are shown, and the maximum operation frequency is 100MHz with capacitor-swapping operation.
Figure 5.10 The measured SNDR against the sampling frequency
5.4 Summary
Table 5.1 summarized the measured results of this ADC with the innovative MDAC.
Parameters Measured Results
Process TSMC 0.18μm CMOS Mixed-Signal
Supply Voltage 1.8 V
Input Range ±0.6V Fully differential
Sampling Frequency 80 MHz
SNDR@FIN=1MHz (Capacitor-Swapping) 42.73 dB
ENOB (Capacitor-Swapping) 6.81 bits
SNDR@FIN=1MHz (No Capacitor-Swapping) 33.57 dB
ENOB (No Capacitor-Swapping) 5.28 bits
Chip Size 1.87mm2
Power Dissipation 88mW
Table 5.1 Summary of measured results of this testing chip
Chapter 6
Conclusions
6.1 Conclusions
Among numerous architectures of CMOS ADC, the Pipelined ADC is the most popular solution for its capability of medium-accuracy/high-speed or high-accuracy/
high-speed. Furthermore, the CMOS and SC implemented Pipelined ADC makes the integration of digital/analog circuits on the same chip with the same supply voltage to be easy, even for the SoC. In this thesis, a 10-bit, 100MS/s Pipelined ADC with 1.8V power supply had been designed, laid-out, fabricated, and measured completely.
There are many non-idealities in actual circuit implementations and we consider these effects with design. The front-end S/H with precharged technique is employed for reducing requirements of the op-amp; the 1.5-bit/stage architecture with the digital error correction is adopted for tolerating comparators offsets. With the innovative technique of capacitor-mismatch calibration, the role of the feedback capacitor in MDACs is no longer fixed, which averages out the capacitor-mismatch errors and improves overall ADC linearity. All approaches mentioned above are desired for less power consumption and die area, higher conversion speed and resolution accuracy.
This testing chip was fabricated by TSMC 0.18um 1P6M CMOS process technology. For 1MHz input signal frequency, the measured SNDR is 44dB at 60MHz sampling rate, 42.7dB at 80MHz sampling rate, and 37.88dB at 100MHz sampling rate. The measured results of the maximum conversion rate are worse than the simulation, because there are many extra parasitic capacitors that the post-layout extraction didn’t extract out, and the measuring skills are not good enough, as well as
other reasons like the instruments issue and the high frequency effects that need to discover and discuss. Furthermore, when measuring the chip, the applied input signal itself already has distortions due to instruments and devices interference, which is especially sensitive to the signal wire of clock. Therefore, when designing the PCB, we must consider and take care of the problem of clock disturbances to the input signal, which is more severe for higher frequency of clock or input signal.
6.2 Future Works
Nowadays, the trend of Pipelined ADC design is toward the direction of higher resolution, faster speed, lower power consumption, and smaller chip area. As the scaling process technology, the reduced supply voltage brings benefits to digital circuits whereas makes the design of analog circuits more difficult.
For higher resolution accuracy, although a wide variety of calibration methods had been proposed and we can develop to implement, few of them can be operated with high conversion rate exceeding 100MHz due to an extra clock cycle for calibration.
For faster conversion speed, a method of time-interleaved which can compensate the speed constraint of the op-amp can be adopted by combining more parallel channels instead of single channel, while matching issues, such as timing skew in multiple channels are the indispensable problem to increase the sampling rate much greatly.
Finally, with the reduced supply voltage, we have to do more efforts to achieve high accuracy and low power at the same time. In order to reduce total power consumption, scaling down of the capacitors stage by stage will be necessary.
Therefore, the design spec. combining high speed and high resolution of an ultra low power ADC will become the most significant topic and have more challenges for the future work.
Bibliography
[1] http://www.nova.net.tw/2006channel/2006award-1.php
[2] 高小文, “低電壓 (1.5V) 8 位元 50MS/s 類比數位轉換器使用 0.35um 1P4M CMOS 製程”, 國立清華大學電子工程研究所碩士論文, 2002.
[3] “Data Converters,” Analog and Mixed Signal Center, TAMU.
[4] R. J. BAKER, “CMOS Circuit Design, Layout, and Simulation,” IEEE, Inc., 2005.
[5] R. V. D Plassche, “Integrated Analog-to-Digital and Digital-to-analog Converters,”
Kluwer Academic Publishers, 1994.
[6] “Defining and Testing Dynamic Parameters in High-Speed ADCs,” Maxim Integrated Products.
[7] “INL/DNL Measurements for High-Speed Analog-to-Digital ADCs,” Maxim Integrated Products.
[8] B. Razavi, “Principles of Data Conversion System Design,” IEEE Press, 1995.
[9] Joao Goes, Joao C. Vital, and Jose Franca, “Systematic Design for Optimization of Pipelined ADCs,” Kluwer Academic Publishers, Boston, 2001.
[10] D. A. Johns and K. Martin, “Analog Integrated Circuit Design,” John Wiley & 0.18-um CMOS Using Averaging Termination,” IEEE J. Solid-State Circuits, Vol.37, No.12, pp. 1599-1609, Dec. 2002.
[14] A. G. F Dingwall and V. Zazzu, “An 8-MHz CMOS subranging 8-bit A/D Converter,” IEEE J. Solid-State Circuits, Vol. SC-20, pp. 1138-1143, Dec. 1985.
[15] B. Razavi and B. A. Wooley, “A 12-b 5-Msample/s Two-Step CMOS ADC,”
IEEE J. Solid-State Circuits, Vol. 27, No. 12, pp. 1667-1678, Dec. 1992.
[16] S. H. Lewis and P. R. Gray, “A Pipelined 5-Msamples/s 9-bit Analog-to-Digital Converter,” IEEE J. Solid-State Circuits, Vol. SC-22, pp. 954-961, Dec. 1987.
[17] S. H. Lewis, H. S. Fetterman, G. F. Gross, Jr., R. Ramachandran, and T. R.
Viswanathan, “A 10-b 20-Msample/s Analog-to-Digital Converter,” IEEE J. Solid-State Circuits, Vol. 27, No. 3, pp. 351-358, March 1992.
[18] T. B. Cho and P. R. Gray, “A 10 b, 20 Msample/s, 35 mW Pipeline A/D Converter,” IEEE J. Solid-State Circuits, Vol. 30, No. 3, pp.166-172, March 1995.
[19] Jieh-Tsorng Wu, “Pipelined Analog-to-Digital Converters in Data-Conversion ICs,” NCTU, Department of Electronics Engineering, April 2007.
[20] 劉智民, “使用改良型電容之八位元高速導管式類比數位轉換器”, 國立台 ADC,” IEEE J. Solid-State Circuits, Vol. 29, No. 4, pp. 509-515, April 1994.
[27] W. C. Song, H. W. Choi, S. U. Kwak, and B. S. Song, “A 10-b 20-Msample/s
Considerations on Low-Voltage Low-Power Data Converters,” IEEE Trans.
Circuits Syst. I, Vol. 42, pp. 853-863, Nov. 1995.
[32] 鄭光偉, “一伏十位元 CMOS 導管式類比數位轉換器”, 國立台灣大學電機工 程研究所碩士論文, 2002.
[33] U.-K. Moon and B.-S. Song, “Background Digital Calibration Techniques for Pipelined ADC,” IEEE Trans.Circuits Syst. I, Vol. 44, pp. 102-109, Feb. 1997.
[34] J. Ming and S. H. Lewis, “An 8-bit 80-Msample/s Pipelined Analog-to-Digital
Converter With Background Calibration,” IEEE J. Solid-State Circuits, Vol. 36, Interstage-Gain and Capacitor-Mismatch Errors in Pipelined ADCs,” ISCAS, pp.
1035-1038, 2006.
[41] M. Dessouky and A. Kaiser, “Input Switch Configuration Suitable for Rail-to- Rail Operation of Switched Opamp Circuits,” Electron. Lett., Vol. 35, No. 1, pp. 8-10, Jan. 1999.
[42] J. Steensgaard, “Bootstrapped Low-Voltage Analog Switches,” in Proc. IEEE Int. Symp. Circuits and Systems, Vol. 2, pp. 29-32, May 1999.
[43] Y.-I. Park, S. karthikeyan, F. Tsay, and E. Bartolome, “A low power 10-bit, 80 MS/s CMOS pipelined ADC at 1.8V power supply,” IEEE Custom Integrated Circuits Conf., pp. 580-583, 2001.
[44] C.-C. Hsu and J.-T. Wu, “A CMOS 33-mW 100-MHz 80-dB SFDR Sample-and- Hold Amplifier,” IEICE Trans. Electron., Vol. E85-C, No. 1, pp. 2122-2128, Jan. 2002.
[45] H. Ishii, K. Tanabe, and T. Iida, ”A 1.0V 40mW 10b 100MS/s Pipeline ADC in 90nm CMOS,” IEEE Custom Integrated Circuits Conf., 2005.
[46] Jieh-Tsorng Wu, “Switched-Capacitor Circuits in Data-Conversion ICs,” NCTU, Department of Electronics Engineering, March 2007.
[47] K. Bult and Govert J. G.. M. Geelen, “A Fast-Settling CMOS Op Amp for SC Circuits with 90-dB DC Gain,” IEEE J. Solid State Circuits, Vol. 25, No. 6, pp.
1379-1384, Dec. 1990.
[48] K. Nakamura and L. R. Carley, “An Enhanced Fully Differential Folded-Cascode Op Amp,” IEEE J. Solid-State Circuits, Vol. 27, No. 4, pp. 563-568, April 1992.
[49] K. Gulati and H.-S. Lee, “A High-Swing CMOS Telescopic Operational
Amplifier,” IEEE J. Solid State Circuits, Vol. 33, No. 12, pp. 2010-2019, Dec. 1998.
[50] B.-M. Min, P. Kim, F. W. Bowman, and D. M. Boisvert, “A 69-mW 10-bit 80-MSample/s Pipelined CMOS ADC,” IEEE J. Solid State Circuits, Vol. 38, No.12, pp. 2031-2039, Dec. 2003.
[51] Jieh-Tsorng Wu, “Comparators and Offset Cancellation Techniques in Data- Conversion ICs,” NCTU, Department of Electronics Engineering, March 2007.
[52] Data Sheet of “LM317 1.2V to 37V Voltage Regulator”, 勝特力電子.
[53] 何俊達, “應用雙倍取樣技術之 10 位元 200 百萬赫茲互補式金氧半導管式 類比數位轉換器”, 國立交通大學電信工程研究所碩士論文, 2006.
[54] 張家瑋 “10 位元 80 百萬赫茲導管式類比數位轉換器和 CMOS 能階參考電 路”, 國立交通大學電信工程研究所碩士論文, 2006.