The Current Generators of Proportional to Absolute
Temperature and Bandgap Reference for
The Current Generators of Proportional to Absolute
Temperature and Bandgap Reference for Temperature Sensor
Student Ming-Chih Liu
Advisor Dr.Herming Chiueh
A Thesis
Submitted to Department of Communication Engineering College of Electrical Engineering and Computer Science
National Chiao Tung University in partial Fulfillment of the Requirements
for the Degree of Master of Science
in
Communication Engineering July 2004
i
260 ×200
ii
The Current Generators of Proportional to Absolute
Temperature and Bandgap Reference for Temperature
Sensor
Student: Ming-Chih Liu Advisor: Dr. Herming Chiueh
Department of Communication Engineering National Chiao Tung University
Hsinchu 30050, Taiwan
Abstract
This thesis describes the design and implementation of proportional to absolute temperature (PTAT) and bandgap reference (BGR) current generators, which are
portable with deep sub-micron process and fabricated by TSMC 0.25 m technology. The proposed circuits consist of PTAT current generator, BGR current generator, power-on-reset (POR) circuit and curvature corrected circuit. The temperature error
of proposed PTAT current does not exceed one degree, and the maximum temperature coefficient of proposed BGR is about 30ppm per one degree. The POR circuit replaces start-up circuit to reduce the power dissipation about 9%, and the curvature corrected circuit improves the accuracy of BGR in low temperature. The overall power dissipation of proposed design is 550 W, and the area is 260 m×200 m
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Acknowledgements
I would like to thank my advisor, Dr. Herming Chiueh, for his guidance. He gives me not only skill and knowledge on research but also concentrations and working chances on life which let me grow quickly. To me he's like a teacher and a friend all in one. Besides, I also would like to thank him spending so much time to examine my thesis because it is really a large work.
I would like to thank other mates of the laboratory and classmates of the university. They bring me a happy life when I am in graduated.
Finally, I would like to thank my parents, Pandean and myself. They give me many supports in spirit and material so that I can get this degree.
This research is supported by National Science Council grant NSC-92-2215-E- 009-042 and NSC-92-2218-E-009-014.
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Content
Chapter 1 Introduction...1
1.1 Motivation...1 1.2 Organization...3Chapter 2 Background ...4
2.1 Emitter Base Junction Voltage of Bipolar Junction Transistors...4
2.1.1 Bipolar Junction in CMOS Technology...5
2.1.2 The Principle of Emitter Base Junction voltage of BJT...5
2.2 Proportional to Absolute Temperature (PTAT) ...7
2.2.1 The Principle of proportional to Absolute temperature ...7
2.2.2 PTAT Circuit Architecture ...8
2.2.3 Start-up Circuits...10
2.3 Bandgap Reference (BGR) ...12
2.3.1 The Principle of Bandgap Reference...12
2.3.2 Bandgap Reference Circuit Architecture ...13
2.4 Non-Ideal Effect of PTAT & BGR and Their Cancellation Techniques ...15
2.4.1 Offset Voltage Due to Device Mismatches ...15
2.4.2 The Non-Linearity of EBJ Voltage in BJTs ...19
2.4.3 Curvature Corrected Techniques...19
2.4.4 Offset Cancellation Technique...20
2.5 Summary...23
Chapter 3 Proposed Design...24
3.1 Design Issues of PTAT & BGR Circuits...24
3.2 Circuit Architecture of Proposed Design ...25
3.2.1 Basic circuits of proposed PTAT and BGR...25
3.2.2 Power-on-Reset Circuits ...27
3.2.3 Curvature Corrected Circuits ...28
3.3 Overall Circuits and Design Considerations...31
3.4 Summary...32
Chapter 4 Simulation and Experimental Results ...35
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4.1.1 Op-Amp Simulation...38
4.1.2 Basic PTAT and BGR Current Simulation...39
4.1.3 Power-on-Reset Circuits Simulation...42
4.1.4 Curvature Corrected Circuit Simulation ...44
4.2 Layout Descriptions ...46
4.3 Measurement Setup...47
4.4 Experimental Results ...50
4.5 Summary...54
Chapter 5 Conclusion and Future Works...55
5.1 Conclusions...55
5.2 Future Works...55
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List of Figures
Figure 1.1.1 The Block Diagram of Temperature Sensor ...1
Figure 2.1.1 Substrate Vertical PNP Transistor in CMOS Technology ...5
Figure 2.1.2 Collector Currents of BJT Versus Absolute Temperature T ...6
Figure 2.2.1 PTAT Voltage Versus Absolute Temperature T...8
Figure 2.2.2 PTAT Voltage Using Self-Biasing Circuit ...8
Figure 2.2.3 PTAT Voltage Using Operational Amplifier...9
Figure 2.2.4 The Two Stage Operational Amplifier...9
Figure 2.2.5 PTAT Circuit with Start-Up Circuit...10
Figure 2.2.6 PTAT Circuit with Start-Up Circuit...11
Figure 2.2.7 PTAT Circuit with Start-up Circuit...11
Figure 2.3.1 Block Diagram of Bandgap Reference...12
Figure 2.3.2 Bandgap Reference Circuit (I)...14
Figure 2.3.3 Bandgap Reference Circuit (II) ...14
Figure 2.3.4 Bandgap Reference Circuit (III)...15
Figure 2.4.1 Offset Voltage in Self-Biasing Circuit by Mismatches...17
Figure 2.4.2 Offset Voltage in Op-Amp by Mismatches ...18
Figure 2.4.3 The EBJ Voltage versus Temperature...19
Figure 2.4.4 Curvature Correction versus Non-Curvature Correction ...20
Figure 2.4.5 The Block Diagram of Chopper Circuit ...20
Figure 2.4.6 Chopper Op-Amp ...21
Figure 2.4.7 (a) The Block Diagrams of Chopper Op-Amp ...21
Figure 2.4.7 (b) Spectrum Analysis of Chopper Op-Amp ...22
Figure 3.2.1 Proposed PTAT and BGR Architecture ...26
Figure 3.2.2 Power on reset circuit ...28
Figure 3.2.3 Curvature Corrected Circuit of VEB...29
Figure 3.2.4 curvature corrected VEB...30
Figure 3.2.1 Equivalent Op-Amp model...31
Figure 3.4.1 Overall circuits of proposed design...34
Figure 4.1.1 Chip Design Flow...36
Figure 4.1.2 Op-Amp Open loop Gain ...38
Figure 4.1.3 Op-Amp Phase Response ...38
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Figure 4.1.5 Basic PTAT Current Error ...40
Figure 4.1.6 Basic BGR Current Error ...41
Figure 4.1.7 Bandgap Reference Current Versus Supply Voltage ...41
Figure 4.1.8 Simplified POR circuit ...42
Figure 4.1.9 The Transient Response of POR Circuit...43
Figure 4.1.10 The Transient Response of PTAT Circuit ...43
Figure 4.1.11 Non Corrected Reference Current Versus Corrected One ...45
Figure 4.1.12 Non Corrected Reference TC versus Corrected One...46
Figure 4.2.1 The Layout of Overall Circuits...47
Figure 4.3.1 The Block Diagram of Measurement Environment ...48
Figure 4.3.2 The PCB Board of Overall Circuits...49
Figure 4.3.3 The Measurement Environment ...49
Figure 4.4.2 Measurement Results of PTAT current...52
Figure 4.4.3 Wider Transistor Layout Methods ...53
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List of Tables
Table 4.1.1(a) MOSFET sizing...37
Table 4.1.1(b) BJT sizing...37
Table 4.1.1(c) Resistor sizing...37
Table 4.1.2 The power Dissipation of POR and Start-up Circuit...44
Table 4.1.3 Characteristics of Resistors in Our Design ...44
Table 4.2.1 Characteristics of Chip simulation...47
Table 4.4.1 The DC Bias of Chip...51
1
Chapter 1 Introduction
1.1 Motivation
CMOS technologies have evolved significantly in last few years, allowing the transistors density on a chip to increase and reducing the cost of overall chip [1]. Large gate counts and high operating frequencies allied with the high performance systems led to considerable increases in temperature of overall chip. However, the overheated chips will reduce the reliability and cause parameter mismatch to impact the performance [1][2]. For these reason described above, low cost and high performance temperature sensors shown in Figure 1.1.1 are gradually required in modern VLSI systems in order to detect the temperature of overall chip [3]. In this thesis, two important blocks in temperature sensor, Proportional to absolute temperature (PTAT) circuits and bandgap reference (BGR) circuits, are implemented
by TSMC 0.25 m technology and the details in our design will be described in first two chapters.
Figure 1.1.1 The Block Diagram of Temperature Sensor
PTAT is the circuit which generates signal proportional to absolute temperature and its functionality is to detect the temperature in temperature sensor. BGR is the circuit which generates a biasing signal independent of temperature and supply voltage is
Reference Signals
PTAT Signals
ADC
ADC
Clock
Ibias
Iref
Itemp
Output
bitstreams
2
provided to another block of temperature sensor, analog-to-digital convert (ADC), to
convert analog PTAT input signals to digital one.
When analog signal is converted to digital one, the addition and minus operation of signals will be used. For voltage mode signals, to achieve these operations will cost more transistors [3]. However, current mode signals only uses one transistor to achieve these operations. The current mode signal is adopted in our design.
The PTAT and BGR current generators have been proposed [3][4], and implemented in 0.7um and 0.6um process, however, there are still some challenges for PTAT and BGR circuits as following:
(1) Additional power dissipation by start-up circuits (2) Compatible with deep sub micron process. (3) High accuracy of BGR signals
For (1), the demand for low power VLSI increases, the power consumption of start-up circuits of BGR will make the power consumption of overall BGR not be scaled down [5]. A simple power-on-reset (POR) circuit will be introduced to replace
the start-up circuit to make the power consumption for starting up be zero. If the power consumption caused by start-up circuit can be eliminated, the power dissipation in PTAT and BGR can be lowered by a factor of supply voltage scaled down.
For (2), as process technologies are scaled down into the deep sub micron eras, the current generators of PTAT and BGR are necessary designed using new deep sub-micron process to integrate with other digital cores in System-on-Chip.
For (3), the accuracy of BGR is especially important for ADC block of temperature sensors [6]. For increasing the accuracy of temperature sensor, adding curvature corrected circuits is necessary. Many curvature corrected circuits have been proposed [7][8]. Their correction approaches are adding a proportional to temperature resistance in the tail of BGR cells, but increase the complexity of the circuits. For reducing the complexity, a simpler curvature corrected circuit will be presented here.
In this thesis, PTAT and BGR circuits are implemented by single-poly-five-mental (1P5M) TSMC 0.25um process, and proposed a simple curvature corrected circuit for
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1.2 Organization
In Chapter 2, the background of PTAT and BGR are discussed. First, Emitter-Base-Junction (EBJ) voltage is introduced and the temperature dependence of
it is also derived. Second, several architectures of conventional PTAT and start-up circuits are introduced. Third, the ones of BGR are also introduced, too. Then, some non-ideal effects are in consideration of BGR and PTAT. Finally, summery ends this chapter.
Chapter 3 introduces our proposed design, and explains the revolution of our proposed design consisting of PTAT, BGR, curvature correction, and POR circuit used to start up PTAT and BGR. Then, some design considerations are discussed and explained. Finally, summary of our proposed design are described.
Chapter 4 introduces simulation and experiment results. First, the Hspice simulation of basic PTAT and BGR is shown, so are POR and curvature corrected circuits. Second, layout consideration and measurement setup are described. Finally, the experiment results and discussion are shown.
Chapter 5 is the conclusion and future work of this thesis which describes the summary of this proposed circuit.
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Chapter 2 Background
This chapter provides the background that completely reviews the Proportional to absolute temperature (PTAT) and Bandgap reference (BGR).
PTAT is the circuit which generates voltage or current signal proportional to absolute temperature. There are two ways to achieve proportional to absolute temperature signals; the first one is to operate MOS in weak inversion region, and the second one is to use the difference between two terminals of bipolar junction transistors (BJT) emitter base junction (EBJ) voltage. The first method is difficult
because the operation region of MOS in weak inversion is quite narrow. If any variation in the circuit is introduced, the operation region may drift to another one. From above discussion, the second way is adopted in our design.
BGR which generates a biasing signal independent of temperature and supply voltage is key elements in analog and mixed-mode circuit. They determine the overall accuracy in many data acquisition systems. The accuracy of temperature sensor is also mainly dependent on the quality of its reference signals.
In this chapter, first, EBJ voltage of BJT is reviewed, because the PTAT of our design which will be mentioned in the chapter 3 is implemented by the difference between EBJ voltage of two BJTs. Second, the principles of PTAT and BGR are introduced and several architectures of PTAT and BGR are also described. Third, non-ideal effects of PTAT and BGR are considered, and the techniques for reducing these effects are also described.
Before understanding the principles of PTAT and BGR, the characteristics of EBJ voltage of BJTs must be understood as section 2.1 which illustrates the details of EBJ voltage of BJTs.
2.1 Emitter Base Junction Voltage of Bipolar Junction
Transistors
In this section, the EBJ voltage of BJTs will be described. As described above, BJT is a necessary part in PTAT and BGR, but MOSFETs are also used in PTAT and BGR. This indicates that both BJT and CMOS technologies must be used simultaneously in PTAT and BGR, but this solution costs too much and degrades the
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performance of overall circuits. It is possible to fabricate BJTs in modern CMOS process, and such types of BJT are called “parasitic BJT”. By using parasitic BJTs, PTAT and BGR can be integrated on the same die. Since parasitic BJTs are utilized in proposed design, following section describes the types and their characteristics of CMOS parasitic BJTs.
2.1.1 Bipolar Junction in CMOS Technology
There are two types of parasitic BJT in CMOS technology, which is described as following:
(1) Lateral BJTs. (2) Vertical BJTs
For (1), the quality of the lateral bipolar junction transistor depends on the IC fabrication, and the leakage current toward substrate is large (via the vertical BJT).
The vertical BJT shown in Figure 2.1.1 seems to be the best choice for integrator PTAT. The quality of this transistor is comparable to transistors in standard CMOS process, so vertical BJT will be adopted for our proposed design in later chapter and its EBJ voltage will be explain in later section. The main disadvantage of vertical BJT is lack of a free collector terminal, because the collector must be terminated to the most negative voltage.
c
Figure 2.1.1 Substrate Vertical PNP Transistor in CMOS Technology
2.1.2 The Principle of Emitter Base Junction voltage of BJT
The EBJ voltage of BJT is simple and sensitive to temperature. It is widely used as a temperature sensing element in embedded temperature sensor. The temperature dependence of EBJ voltage is discussed in this section.
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Figure 2.1.2 Collector Currents of BJT Versus Absolute Temperature T
As shown in Figure 2.1.2, the collector and base are connected so that early effect can be ignored. When the applied bias current is constant, the EBJ voltage decreases almost linearly to absolute temperature. The approximation is shown as following:
0
( ) 1.27
EB
V T = −K T (2-1) where K0 is a constant about 2mV/K. It depends on the bias current and technology
parameters. T represents the absolute temperature.
To understand the dependence on temperature of EBJ voltage, A detail mathematical equation is derived
( ) ln C ln C EB T S S I kT I V T U I q I = = (2-2) where Is represents the reverse saturation current of P-N junction, T is the absolute temperature, k is the Boltzmann’s constant, and q is the electron charge. In this equation, VEB seems to be proportional to absolute temperature. However, Is and Ic
are strongly dependent on absolute temperature, VEB is not proportional to absolute
temperature. The saturation current Is can be related to the device structure by
2 ' ' S i I =B n T
µ
(2-3) m C I =GT (2-4) where ni is the intrinsic minority carrier concentration, ’ is the average electronmobility in the base, and G is temperature independent quantity, However, ni and ’
7 0 2 3exp( G ) i T V n DT U = − (2-5) ' CT n
µ
= − (2-6)where C and D are temperature independent quantities. VG0 is the bandgap voltage of
silicon extrapolated to 0oK. When a reference temperature is specified, the overall temperature dependence of EBJ voltage can be derived from Eq.2-3 to Eq.2-6.
0 ( ) (1 ) ( ) (4 ) ln EB G EB r r r r T T kT T V T V V T n m T T q T = − + − − − 0(1 ) ( ) (4 )(ln ln ) G EB r r r r T T kT V V T n m T T T T q = − + − − − − (2-6) where Tr is reference temperature. For T is very close to Tr, then
2 3 2 3 1 1 1 ln 1 ( r) ( r) ( r) r r r T T T T T T T T T T ≈ + − − − + − (2-7) From Eq.2-6 and 2-7, Eq.2-8 can be obtained
0 0 0 1 2 3 0 1 2 3 ( ) (1 ) ( ) (4 )(ln ln ) ( 1) ( ( ) ) (4 )ln (4 )[1 ( ) ] EB G EB r r r r i i G EB r G r r r i r G T T kT V T V V T n m T T T T q T kT kT V V T V n m T n m i T T T q q T V AT A T A T ∞ = = − + − − − − − = + − + − − − − − + − ≈ + + + So, 2 3 0 1 2 3 ( ) EB G V T ≈V +AT A T+ +A T (2-8) Typically, A1 is negative number, V T is negative TC and almost perfectly EB( ) complementary to absolute temperature because slope of V T versus temperature EB( ) is current dependent.
After understanding the characteristics of EBJ voltage of BJT, the principle of PTAT and BGR based on BJT devices can be introduced in following sections.
2.2 Proportional to Absolute Temperature (PTAT)
After finishing introducing parasitic BJTs and the characteristics of them, the principle of PTAT using BJT device is introduced as following:
2.2.1 The Principle of proportional to Absolute temperature
As illustrated in Figure 2.2.1, when both transistors are at the same temperature T, the difference of two EBJ voltage can be derived form Eq.2-2 as :
8 1 2 1 2 2 1 ln( C S ) ln( ) PTAT EB EB C S kT I I kT M V V V q I I q N = − = = (2-9) where M is emitter area ratio, and N is current source ratio. They have no temperature dependence, and only depend on devices geometry and current source ratio.
Figure 2.2.1 PTAT Voltage Versus Absolute Temperature T
From above equation, VPTAT is directly proportional to absolute temperature T.
The ratio kT/q is called the thermal voltage and equals to approximately 26mV at room temperature (T=300K). The TC of VPTAT signal yields approximately 200uV/K
for n being 10. This amplification factor, n, is set by the ratio of N and M.
2.2.2 PTAT Circuit Architecture
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Figure 2.2.3 PTAT Voltage Using Operational Amplifier
There are two ways to achieve voltage addition and minus. The first one is using self-biasing circuit, and the second one is using operational amplifier (Op-Amp).
Figure 2.2.2 is a PTAT voltage generated by self-biasing circuit. If M1~M4 are identical, the source voltage of M1 and M2 will be equal. The current through R1 will be proportional to absolute temperature. By using current mirror of M4 and M5, Vo be PTAT voltage. Figure 2.2.3 is also a PTAT voltage generated by operation amplifier. The topology of the operational amplifier is as following:
Figure 2.2.4 The Two Stage Operational Amplifier
A two stage Op-Amp is shown in the Figure 2.2.4. If the open loop gain of the Op-Amp is large enough, the gate voltage of M1 and M2 will be almost equal. Then, the drain voltage of M2 and M3 of the Figure 2.2.3 will be equal. The PTAT current is
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mirrored by M1, and Vo will also be PTAT voltage. For reducing output loading effects, A voltage buffer can be added at the output, but additional offset and drift will be introduced.
2.2.3 Start-up Circuits
For the PTAT circuits shown in Figure 2.2.2 and Figure 2.2.3, they both have a second trivial steady state condition, cutoff ,when the currents of all branches are equal to zero. To prevent the PTAT circuit from settling to the wrong steady state condition (zero current state), a start-up circuit is necessary in all practical PTAT circuits. For the PTAT in the Figure 2.2.5, a start-up circuit is added to explain how the start-up circuit works.
Figure 2.2.5 PTAT Circuit with Start-Up Circuit
In Figure 2.2.5, M5~M9 and R3 form a start-up circuit. When the current of M4 is zero, the gate voltage of M8 is zero. The drain voltage of M8 is VDD, and M6 is on
to force M5 to generate current. The PTAT circuit will move its operation region from zero current state region to normal operation one. However, adding start-up circuit will introduce a disadvantage which consumes some additional power in overall PTAT circuits, because M7-R3 branch of start-up circuit is always on. There is another start-up circuit which reduces the static power dissipation. In Figure 2.2.6, adding a capacitance starts up the PTAT circuit. When the current of M4 is zero, the supply noise will cause a signal path from VDD to Gnd, and forces the circuit to enter normal
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Figure 2.2.6 PTAT Circuit with Start-Up Circuit
The advantage of this start-up circuit is consuming no additional power, when the PTAT circuit enters normal operation region. It use only one capacitor, but the value of this capacitance must be large enough to ensure to establish signal path from VDD and Gnd. The capacitor may have very large area. For improving this
disadvantage, the capacitor can be replaced by a diode-connected NMOS. For a diode-connected NMOS, it serves capacitor asC . In general, a MOS has smaller area gs
than a resistor and better match. With lower and lower supply voltage, however, the PTAT in Figure 2.2.7 will fail to start up itself, because power supply may not provide enough start-up voltage. The VDD must be obeyed:
3 5 2 1
DD GS GS GS EB
V ≥V +V +V +V (2-10)
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2.3 Bandgap Reference (BGR)
As described in previous section, BGR which generates a biasing signal independent of temperature and supply voltage is key elements in analog and mixed-mode circuit. To achieve the independence of temperature, a positive temperature coefficient (TC) signal and a negative one are both required to make the
overall TC be equal to zero. After having been familiar with PTAT signal and EBJ voltage of BJTs, PTAT signal has positive TC and EBJ voltage has negative one. In the following sub-section, the two components are described to achieve BGR.
2.3.1 The Principle of Bandgap Reference
Conceptually, to achieve a BGR, it is necessary to accomplish one of the two possible functions shown in Figure 2.3.1.
Figure 2.3.1 Block Diagram of Bandgap Reference
The first function is the signal generator of negative TC and the second one is the signal generator of positive temperature. By linear combination of these two signal, the TC of BGR signal could be zero.
For EBJ voltage of BJT, it is negative TC from Eq.2-8, but suffers from the high order nonlinearity of temperature. For PTAT signal, the difference between two terminals of BJT EBJ voltage, it has positive TC from Eq.2-9 with exact linearity. From Eq.2-8, Eq.2-9 and Figure 2.3.1, the BGR signal is derived as following:
( ) ( ) bg T EB V T =αU +βV T (2-11) 2 3 0 1 2 3 ln( ) [ G ] kT M V AT A T A T q N α β ≈ + × + + +
V
EBnegative
TC generator
V
PTATpositive
TC generator
+
BGR
signal
Zero TC
13 2 3 0 [ ln( ) 1] 2 3 G k M V A T A T A T q N β α β β β ≈ + + × + + (2-12) By adjusting and to cancel the one order term of absolute temperature, and Eq.2-13 can be obtained.
2 3
0 2 3
( )
bg G
V T ≈βV +βA T +βA T (2-13) Because
β
A2 and βA3 are far less than unity, then Eq.2-14 is obtained.0
( )
bg G
V T ≈βV (2-14) so, from Eq.2-14, V Tbg( ) is almost temperature independent signal. BGR circuit can be implemented according to this equation.
2.3.2 Bandgap Reference Circuit Architecture
In section 2.3.1, the principles of BGR have been introduced. In this section, our block diagram of BGR will be realized to transistor level circuits. Because CMOS technology is more popular and lower cost, MOS transistor is used to achieve self-biasing and Op-Amp in our design. In this section, three circuit architectures of BGR are introduced and shown in Figure 2.3.2 to Figure 2.3.4. The BJTs which appear in these Figures are parasitic substrate vertical BJT and compatible to CMOS technology. In Figure.2.3.2, the BGR is achieved by self-biasing circuit. M1~M4 are assumed to be identical, then
1 2 Q Q Q I =I = and I VS2=VS1 1 1 ( 2 3) 2 Q EB Q EB I R V+ =I R +R +V 1 2 3 1 ln ( ) Q k N I T B T q R R R = = + − (2-15) 2 3 2 ( ) ( ) bg Q EB V T =I R +R +V 2 3 0 [ 1 1] 2 3 G V A B T A T A T ≈ + + × + + (2-16) From Eq.2-8 and Eq.2-15, Eq.2-16 can be obtained. Because A1 is a negative
real number and B1 is positive one, A B1+ 1 can be adjusted to be equal to zero.
Eq.2-16 will be as:
2 3
0 2 3 0
( )
bg G G
V T ≈V +A T +A T ≈V (2-17) Because A2 and A3 are far less than unity, the circuit in Figure 2.3.2 can be a
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Figure 2.3.2 Bandgap Reference Circuit (I)
In Figure.2.3.3, the BGR is achieved by three resistors and one operational amplifier. If the Op-Amp is ideal and the Emitter-Base area ratio of M2 to M1 is P, then 1 2 G G V =V and 2 2ln Q kT I P qR = Eq.2.8 can be obtained as following:
2 3 2 2 ( ) bg Q EB V = R +R I +V 3 0 1 2 [ (1 )(ln ) ] G k R V P A T q R ≈ + + + (2-18) bg
V is a BGR voltage from Eq.2-18, if 3 1 2
(1 )(ln )
k R P A
q +R + is zero.
Figure 2.3.3 Bandgap Reference Circuit (II)
In Figure 2.3.3, three resistors are used in this BGR, but resistors usually are far larger area than MOS transistors and more difficult to match in IC technology. In
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Figure 2.3.4, two transistors are replaced by two transistors so that the area of overall circuit can be reduced. If the Op-Amp is ideal and M1 and M2 are identical, the derivation of Vbg is as following: 2 ln Q kT I P qR = 2 2 2 bg Q EB V =R I +V 0 [ ln 1] G k V P A T q ≈ + + (2-19) bg
V is a BGR voltage from Eq.2-18, if adjusting ln 1
k
P A
q + to be zero.
Figure 2.3.4 Bandgap Reference Circuit (III)
2.4 Non-Ideal Effect of PTAT & BGR and Their Cancellation
Techniques
In previous section, the principles of PTAT and BGR are introduced and all conditions in of these circuits are assumed to be ideal, but there are two non-ideal effects including offset vltage due to device mismatches and the non-linearity of EBJs.
In this section, these non-ideal effects are described and the methods for reducing them are also introduced.
2.4.1 Offset Voltage Due to Device Mismatches
Our study of PTAT circuits in previous sections has mostly assumed the circuits are perfectly symmetric, in other words, the two sides exhibit identical properties and
16
bias currents. In reality, however, nominally-identical devices suffer from a finite mismatch due to uncertainties in each step of manufacturing process. Also, MOS devices exhibit threshold voltage mismatch because from Eq.2-15:
2 dep TH MS F ox Q V C = Φ + Φ + (2-15) whereΦ is the difference between the work function of the poly-silicon gate MS
and the silicon substrate, F ln sub
i
kT N q n
Φ = , Nsub is the doping concentration of the
substrate, Qdep is the charge in the depletion region, and Cox is gate oxide
capacitance per unit area, so VTH is a function of the doping levels in the channel and
the gate, and these level vary randomly from one device to another.
For analyzing the effect of device mismatches, we observe that mismatches between µ,Cox, W, L, and VTH result in mismatches between drain current (for given
VGS) or gate-source voltage (for given drain current) . Intuitively, we expect that as W
and L increase, their relative mismatches, W
W ∆ and L L ∆ , respectively decrease, so Large devices suffer from less mismatches.
For mismatches between µ,Cox, W, L, and VTH will result in DC offset in
Op-Amps and self-biasing circuit. We first discuss the offset voltage of self-biasing shown in Figure 2.4.1 result from M1~M4 mismatches. For IQ1 must be equal to
2
Q
I and eliminating channel length effect, it can be assumed that
3 4 4 SD SD SG V =V =V and VDS2=VDS1=VGS1 3 34 1 34 2 TH TH TH V =V + ∆V and 4 34 1 34 2 TH TH TH V =V − ∆V 1 12 1 12 2 TH TH TH V =V + ∆V and 2 12 1 12 2 TH TH TH V =V − ∆V 1 12 12 1 12 12 1 ( ) ( ) ( ) 2 W W W L = L + ∆ L and 2 12 12 2 12 12 1 ( ) ( ) ( ) 2 W W W L = L − ∆ L 3 34 34 3 34 34 1 ( ) ( ) ( ) 2 W W W L = L + ∆ L and 4 34 34 4 34 34 1 ( ) ( ) ( ) 2 W W W L = L − ∆ L 3 1 3 1 4 2 4 2 OV OV TH TH OV OV TH TH OS V +V +V +V =V +V +V +V +V then
17 3 4 1 2 3 4 1 2 OS OV OV OV OV TH TH TH TH V =V −V +V −V +V −V +V −V 12 34 3 4 1 2 3 4 1 2 2 2 2 2 ( ) ( ) ( ) ( ) Q Q Q Q TH TH P P N N I I I I V V W W W W K K K K L L L L = ∆ + ∆ + − + −
Figure 2.4.1 Offset Voltage in Self-Biasing Circuit by Mismatches Assume these MOSFETs are square law devices, then
34 12 12 34 12 34 12 34 12 34 12 34 34 12 12 34 ( ) ( ) [1 ] [1 ] [ ] 2 ( ) ( ) m m OV OV OS TH TH m m W W g g V V L L V V V W W g g L L ∆ ∆ + ≈ + ∆ + + ∆ + + (2-16)
Second, the offset voltage of Op-Amp is discussed in Figure 2.4.2. The offset voltage of an Op-Amp is composed of two components:
(1) Systematic offset. (2) Random offset.
The systematic offset voltage is caused by unequal drain voltage of M3 and M4, and it can be resolved by transistor sizing as following:
3 4 5 3 4 5 6 6 7 6 6 7 ( ) ( ) ( ) ( ) ( ) 2( ) W W W L L L W W W L L L = = (2-17) The random offset voltage is caused by mismatches of transistors, and can be reduced by choosing longer channel devices. For analyzing it, some condition must be assumed as following:
18 3 4 4 SD SD SG V =V =V and VDS2=VDS1=VGS1 3 34 1 34 2 TH TH TH V =V + ∆V and 4 34 1 34 2 TH TH TH V =V − ∆V 1 12 1 12 2 TH TH TH V =V + ∆V and 2 12 1 12 2 TH TH TH V =V − ∆V 1 12 12 1 12 12 1 ( ) ( ) ( ) 2 W W W L = L + ∆ L and 2 12 12 2 12 12 1 ( ) ( ) ( ) 2 W W W L = L − ∆ L 3 34 34 3 34 34 1 ( ) ( ) ( ) 2 W W W L = L + ∆ L and 4 34 34 4 34 34 1 ( ) ( ) ( ) 2 W W W L = L − ∆ L
Figure 2.4.2 Offset Voltage in Op-Amp by Mismatches
1 2 OS SG SG V ≡V −V |VD3=VD4 1 2 1 2 1 2 1 2 2 2 ( ) ( ) D D TH TH P P I I V V W W K K L L = − + − (2-18) Because 1 3 3 3 3 ( ) 2( ) N D K OV TH I W V V L = + and 2 4 4 4 4 ( ) 2( ) N D K OV TH I W V V L = +
Then Eq.2-18 will be as following:
34 12 12 12 34 34 12 34 12 34 12 12 34 ( ) ( ) [ ] 2 ( ) ( ) OV m OS TH TH m W W V L L g V V W W V g L L ∆ ∆ ≈ ∆ + + + (2-19) From Eq.2-16 and Eq.2-18, the approximant equation of offset voltage is derived.
19
For reducing the offset voltage, larger devices can be chosen or layout carefully.
2.4.2 The Non-Linearity of EBJ Voltage in BJTs
In contrast to the PTAT voltage, which is highly linear function of temperature, the signal related to the EBJ voltage shows a slight non-linearity. This non-linearity has already discussed in Eq.2-8 and plots it in Figure 2.4.3 as following:
Figure 2.4.3 The EBJ Voltage versus Temperature From Eq.2-6, it can be rewriten as following
' 0 ( ) ln EB G V T =V +AT BT T+ (2-20) 0 1 2 i G i i V AT ∞ AT = = + + (2-21) Where A and B are negative number, and A is very small. i
2.4.3 Curvature Corrected Techniques
Curvature correction is a technique which makes circuit to generate lnT T term to cancel BT Tln term in Eq.2-20 or to generate Ti term to cancel
i
A in Eq.2.21. It is more difficult to achieve in circuit devices for the first method, so the second method is used. In Eq.2.21, the second order term of temperature is only cancelled. After canceling the second order term, more stable TC BGR voltage can be obtained as Figure 2.4.4.
20
Figure 2.4.4 Curvature Correction versus Non-Curvature Correction
2.4.4 Offset Cancellation Technique
As mentioned in section 2.4.1, offset voltage results from devices mismatches in Op-Amps and self-baising circuits. The offset voltage reduces the accuracy of PTAT and BGR voltage. At low frequencies, however, flicker noise also degrades the accuracy of the reference signal, so offset cancellation techniques is required to overcome these problems. One of the offset cancellation techniques is chopper technique suited, because it is used to process continuous time signals. The block diagram of chopper circuit is described as Figure 2.4.5
21
Offset voltage and low frequency noise of Op-Amp will reduce accuracy of PTAT and BGR, so chopper circuit will be used to combat the effect of them. A chopper Op-Amp is presented in Figure 2.4.6, and there are two non-overlapped clock waveforms 1 and 2. When 1 is high and 2 is low, the Op-Amp is operated in normal mode. When 1 is low and 2 is high, the Op-Amp is operated in chopper mode and the Op-Amp can be equivalent to multiplying -1 at the input node and output node. its spectrum analysis is shown in Figure 2.4.7.
Figure 2.4.6 Chopper Op-Amp
22
23
From Figure 2.4.7, the chopper technique modulates offset voltage and flicker noise to high frequency band and filters it by low pass filter, so the chopper technique can reduce offset voltage and flicker noise.
The offset voltage and high order temperature dependence of EBJ voltage are introduced, and the circuits which reduce their effect are also presented. When designing PTAT and BGR, these non-ideal effects must be taken care to increase the performance of PTAT and BGR.
2.5 Summary
In this chapter, the principles of PTAT and BGR have been shown and several circuit architectures and mathematics description of them are presented. However, PTAT and BGR suffer from nonlinearities due to the EBJ voltage and offset voltage, and the non-ideal effects can be reduced by curvature correction and chopper technique.
In next chapter, PTAT and BGR of our design is proposed and designed to improve their performance in some aspects and all the details will be described later. Based on these backgrounds, it is quite useful for us to get guidelines in our proposed design.
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Chapter 3 Proposed Design
In Chapter 2, backgrounds of PTAT and BGR have been described. In this chapter, our new design of PTAT and BGR will be proposed. The main advantage of our proposed design is replacing start-up circuit by POR circuit to make power consumption of start-up to be zero, and the secondary advantage is realizing our design in deep sub-micron process and adding curvature circuit to improve the accuracy of BGR.
This chapter will propose our new design, and the order of sections arranges as following: First, the disadvantages of conventional PTAT and BGR in deep sub-micron processes are discussed and their operations are also explained. Second, our new design is proposed to overcome the problems caused by deep sub-micron processes. Third, the design considerations of our design are explained. Finally, the summary of our design is presented.
3.1 Design Issues of PTAT & BGR Circuits
As process technologies are scaled down into the deep sub-micron eras, conventional BGR and PTAT are not suited for deep sub-micron processes.
First, because the demand for battery operated portable increases, conventional PTAT and BGR circuits are not suited for low power requirement. As described in section 2.2.3, start-up circuits of PTAT and BGR in non-zero current state will still consume additional power. The additional power consumed by start-up circuits will become a serious bottleneck in low power systems, as the processes are scaled down to nanometer scale.
Second, the older CMOS devices followed the “square-law” MOSFET model, but the newer devices are not. An older MOSFET that can be modeled well using the level 1 model yields simulation results that match hand-calculations and provides immediate feedback to the designer to know the operation of all transistors. The level 1 model can accurately model with Lmin>5µm. However, the MOSFETs in deep
sub-micron processes (Lmin<0.5µm), the error of level 1 square-law model is
generally above 100%, this appears that the analog circuit design will be more and more difficult in shorter channel technologies.
25
Third, the accuracy and stability of BGR signals are very important in ADC and they influence the output bit-steams of ADC, so a curvature correction circuit is necessary in BGR circuits to increase the accuracy of temperature sensor.
Finally, for PTAT and BGR in voltage mode, the addition and minus of voltage signals must use Op-Amps and self-biasing circuits (more transistors). This will increase the complexity of circuit architecture and waste power. But the addition and minus of current signals use only one transistor (switch) to achieve them, the complexity and area of the circuit will be reduced if the current output of PTAT and BGR is adopted in our proposed design .
For these reasons described above, new PTAT and BGR must be designed to solve these problems and be integrated with thermal-aware VLSI systems in deep sub-micron processes.
3.2 Circuit Architecture of Proposed Design
This section presents our proposed design, and consists three parts described as following:
3.2.1 Basic circuits of proposed PTAT and BGR
As described in section 2.2, two architecture of PTAT circuit are introduced as following:
(1) PTAT based on self-biasing circuit. (as Figure 2.2.2) (2) PTAT based on operational amplifier. (as Figure 2.2.3)
The first architecture is simpler than second one, but from Eq.2.16 and Eq.2.19, the first one has larger offset voltage than the second one. The offset voltage is a very important error source in PTAT and BGR design, so the first architecture is chosen for our proposed design.
In section 2.3, three circuit architectures of BGR are introduced as following: (1) BGR using self-biasing circuit. (as Figure 2.3.2)
(2) BGR using an Op-Amp and three resistors. (as Figure 2.3.3) (3) BGR using an Op-Amp and one resistor. (as Figure 2.3.4)
The first architecture has large offset voltage from Eq.2-16 and Eq.2-19. The second one has three resistors and has larger area than the other ones, so the third one is chosen for our proposed design.
26
Figure 3.2.1 Proposed PTAT and BGR Architecture
Figure 3.2.1 shows the proposed circuit architecture of PTAT and BGR. The M3~M9 form an operation amplifier (Op-Amp). If the open loop gain of Op-Amp is large ,the drain voltage of M1 and M2 will be almost the same. The voltage drop cross R will be PTAT voltage.
The analog interface consists of M43~M47, an Op-Amp, and Rbe. The design of the Op-Amp is similar to M3~M9. The use of analog interface is to convert voltage signals of PTAT and BGR to current ones. First, the current cross R is PTAT current and mirrored to M47 as output PTAT current. Second, to generate a BGR current, a negative TC current must be first generated. For an EBJ voltage of BJTs, it is a negative TC voltage and connected to a source follower as input. Because the voltage gain of source follower is close to unity, an Op-Amp is added with negative feedback and the gain of source follower becomes to Eq.3-1
48 48 48 48 1 1 1 m V m mb o be A g A A g g r R × ≈ ≈ × + + + (3-1) The voltage cross Rbe is negative TC voltage and the current cross Rbe is too. Now, the equation of the BGR current is derived as following:
43 44 ref I =I +I 43 44 43 45 44 2 45 2 45 2 ( ) ( ) ( ) ( ) W W L I L I W W L L = +
27 43 44 2 43 44 45 2 45 2 ( ) ( ) ( ) ( ) EB EB be W W V V L L W R W R L L ∆ = + (3.2) By Eq.2-8 and Eq.2-9, rewrite Eq.3-2 as follow:
43 44 43 0 44 45 1 2 45 2 ( ) 1 ( ) ( ) ln ( ) ( ) i ref G i be i W W kT L L I V AT M W R W qR L L ∞ = ≈ + + 43 43 44 43 0 1 43 43 44 43 45 45 2 45 2 45 45 2 45 ( ) ( ) ( ) ( ) 1 { ln } ( ) ( ) ( ) ( ) G i i be be be i W W W W V A k L L L M T L AT W R W R W qR W R L L L L ∞ = = + + × + (3.3)
Form Eq.3-3, the 43
43 (W ) L and 44 44 (W )
L can be adjusted to cancel the TC of the first
order, so BGR current is obtained. Another advantage of this architecture is the output reference current can be programmable by adjusting the 45
45
(W )
L .
3.2.2 Power-on-Reset Circuits
As describe in section 2.2.3, BGRs have two stable operating states, given by zero current state and normal bandgap state. To avoid a stable off state, a start-up circuit is usually used. When start-up circuits are used, the main issue is that introducing additional power by some branches being on. The power consumption of start-up circuits should be zero when the BGR circuit is in normal operation. Another issue in start-up circuits is stability. When the next stage of closed loop circuit is start-up circuit, the potential for oscillation is greatly increased.
The POR circuit is shown in Figure 3.2.2, and the basic principle of POR circuit is the use of two RC circuits (Mpor1, Mpor3, C1 and C3) with different time constants. For our proposed design, the time constant of node A is smaller than the one of node B. when a battery is inserted into the system, node A approaches VDD
28
Figure 3.2.2 Power on reset circuit
This is accelerated by positive feedback transistors (Mpor7 and Mpor8) acting as a latch, and the output of the POR circuit feeds the gate of Mpor4. Because the node A has faster speed to charge its voltage to VDD than node B, the voltage of the node D
will be from high to low. In the process of discharging, the Mpor4 will start up the PTAT circuit. When the voltage of the node D discharge to zero, the POR circuit will be all off and consumes no power. By the way, it shows that the POR circuit is better power performance than start-up circuits.
Another advantage of this POR circuit is that the resistors are implemented by MOS operated in triode region. For this reason, the area of overall chip area can be reduced and the equivalent value of resistors are more accurate to make the RC time constant be precision.
3.2.3 Curvature Corrected Circuits
As mentioned in section 3.2.1, the first order TC of BGR current is adjusted to zero, but the high order TC terms of Iref still exist. These high order TC terms must be canceled to improve the linearity of BGR current. From Eq.3-3, the BGR current after canceling the first order TC can be obtained as following:
43 43 0 43 43 45 45 2 45 45 ( ) ( ) 1 ( ) ( ) G i ref i be be i W W V L L I W W AT R R L L ∞ = ≈ + (3.4) The goal of curvature correction is to minimize the terms of high order TC. There are three approaches of curvature corrected:
29
(1) Make the process parameter 4 n m− − be zero. (See Eq.2-7 and 2-8) (2) Generate a lnT T term to compensate reference signals. (See Eq.2-6)
(3) Approximate the lnT T by the T . (See Eq.3-4) 2
Figure 3.2.3 Curvature Corrected Circuit of VEB
In the first method, the 4 n m− − is strong dependent of process, it is impossible to make 4 n m− − in every process be zero. In the second method, to implement the lnT T function in the circuit is very difficult. In consideration of
circuit complexity and cost, the third approach is adopted. The circuit approach of implementing T correction is adding a proportional to temperature resistance in the 2
tail of BGR cells. Figure 3.2.3 is a curvature corrected circuit of our proposed design and is similar to the left part of Figure 3.2.1. The difference between them is adding two resistors in Figure 3.2.3.
The two resistors, R2 and R3, are proportional to absolute temperature and described as following:
2( ) 2( )0 R2 ( 0)
R T =R T +TC × −T T
R T3( )=R T3( )0 +TCR3× −(T T0) (3.5)
30
Figure 3.2.4 curvature corrected VEB
From Eq.2-21 and Eq.3-5, the emitter current of BJT be I PTAT and derive the
corrected VEB equation.. 0 1 2 i EBC G i i V V AT ∞ AT IR = = + + + 2 0 1 2 0 3 [ ( )] i G i PTAT R i V AT A T ∞ AT I R TC T T = = + + + + × + × − 2 0 1 2 0 1 3 [ ( )] i G i R i k V AT A T AT T R TC T T qR ∞ = = + + + + × × + × − 2 0 1 0 2 1 1 3 ( ) ( R) i G R i i kR k TC V A TC T T A T AT qR qR ∞ = × = + − + × + + + (3.6)
For A2 be negative and TCR be positive, 2 1 R k A TC qR + × can be adjusted to be zero, then 0 1 0 1 3 ( ) i EBC G R i i k R V V A TC T T AT q R ∞ = = + − × + × + (3.7) Because the T term is cancelled, the EBJ voltage is more linear, so the BGR 2
signal is more stable. Because the VEB1 and VEB2 are both cancel the TC of second
order term, the current cross R1 is still PTAT current. By this curvature correction, it will not affect other functionalities in our proposed design.
Now, the corrected Iref can be derived as following:
43 44 ref
I
=
I
+
I
43 43 44 43 43 44 45 45 2 45 45 2 43 43 2 43 43 2 2 45 45 3 45 45 0 1 2 2 0 1 ( ) 1 ( ) 1 ( ) ( ) ( ) ( ) ( ) ( ) { [ ] ln } ( ) ( ) ( ) i R i be be i G R be be be W W L L T A mTC T AT W R W R L L W W W V A R TC T k L L L M W R W R W R qR L L L ∞ = × + + + − = + + + (3.8) From Eq.3-8, our BGR current can be more accuracy by adding two resistors31
with temperature dependence.
After explaining the principle of our proposed design, design consideration of our design will be introduced.
3.3 Overall Circuits and Design Considerations
After the overall circuits of our design have been proposed, some consideration of our proposed design will be described in this section.
First, Op-Amp circuits are discussed. There are two Op-Amps in our proposed design, and the two stage Op-Amp is chosen here. In general, the open loop gain of the Op-Amp is proportional to (gmro)2, and it can be adjusted by these parameters (gm
and ro) to increase open loop gain. A trick which must be taken care is that the
minimum channel length of MOSFETs in our Op-Amp can be not chosen, because the
o
r is proportional to channel length.
Another consideration of the Op-Amp is phase margin. In Figure 3.2.1, the next stage of Op-Amp1 is a common source (CS) amplifier. For Miller effect of CS
amplifier, the first pole and second pole of the Op-Amp will be closer and more unstable. Because of this consideration, larger phase margin in our Op-Amp must be designed and chosen as 60 degree in our design. Our Op-Amp can be simplified to equivalent model as Figure 3.3.1 and Cc can be designed from the constrain of Op-Amp phase margin. Eq.3-9 is the equation between Cc and phase margin.
Figure 3.3.1 Equivalent Op-Amp model
5 1 2 9 1 ( ) 0.577 m o o m g Cc C C g = × × + (3.9) Where Co1 and Co2 are the first stage and the second stage output capacitance.
32
In the BGR design, the offset voltage of Op-Amp is very critical error source. For reducing it as possible, the transistor sizing rule of Eq.2-17 must be obeyed. it can be rewriten as following: 7 8 3 7 8 3 9 9 4 9 9 4 ( ) ( ) ( ) ( ) ( ) 2( ) W W W L L L W W W L L L = = (3.10) Increasing the emitter area ratio of Q1 and Q2 can also reduce the effect of offset voltage in Op-Amp, because the larger ratio of Q1 and Q2, the larger value of ∆VEB.
Second, the design of curvature corrected circuit is discussed. In Figure 3.1.5, three resistors R1, R2 and R3 are used. For the value of R1, it should be independent of temperature. However, the materials of resistors in the process always have dependence of temperature, the lowest TC material is chosen for R1 and proportional to temperature resistance is chosen for R2 and R3,. In the analog interface of our design, Rbe, which also is independent of temperature is used. the same material of Rbe will be chosen as R1.
Finally, the POR circuit design is discussed. As described in previous section, the RC1 constant must be smaller than RC2. To achieve small value of RC1, the 1
1
( POR )
POR
W L
is designed to be larger and operate Mpor1 in triode region to reduce the equivalent resistance of MPOR1. Because the behavior of the POR circuit is digital circuit, we can
use the minimum channel length to increase the performance here. Another constrain of the POR circuits is the RC1 must be smaller than the half chopper interval to keep chopper circuits to work normally.
3.4 Summary
In this chapter, our new design of PTAT and BGR suit for deep sub-micron process are proposed and the output signal is current signals. Replacing the start-up circuits by POR circuits and a simple method of curvature correction are proposed, too. Using the POR circuits can reduce power consumption of overall circuits, and make our PTAT and BGR suit for low power or thermal-aware system under a tendency towards deep sub-micron process. Adding curvature corrected circuits can compensate the nonlinearities of EBJ voltage and increase the accuracy of BGR signals. Finally, some design consideration of our proposed design is explained to
33
achieve better performance. The overall circuits of our proposed design are shown in Figure 3.4.1.
In next chapter, simulation and experimental results will be shown. By reliable design flow and tool, our design is realized by TSMC 0.25um 1P5M technology. Measurement setup is also described. Finally, some discussion of experimental results is described.
34
35
Chapter 4 Simulation and Experimental Results
In the previous chapter, our proposed designs have been presented and the design principles of them have been familiar with. In this chapter, the proposed design will be simulated and implemented by TSMC 0.25um 1P5M technology. The design flow used to achieve the proposed design is shown in Figure 4.1.1 can be followed. First, all functionalities of our circuits are simulated by Hspice. Second, adjusting the parameters in the proposed design optimizes performance. Third, convert the schematic of our design to layout. Finally, “Design Rule Check” (DRC) and “Layout
VS Schematic” (LVS) must be checked to verify process design rule and check our
layout to be the same as our schematic.
First, our Hspice simulation of all modules will be shown. It consists of PTAT, BGR, POR circuits, and curvature corrected circuits. Second, our layout of overall circuits and layout considerations is shown. Third, the measurement environment and testing setup is described. Finally, our experimental results will be shown.
4.1 SPICE simulation
Before simulating our design, all transistor sizing must be derived. All of them are described in Table 4.1.1. All transistor sizing can be derived by TSMC spice model, Kirchoff’s Voltage Law (KVL), and Kirchoff’s Voltage Law (KCL). It is
somewhat difficult work to calculate all transistor sizing by spice model of BSIM3 Level 49, so a simpler model as level 2 can be used, then transistor size can be somewhat tuned. By the way, all transistors’ size is obtained.
36
Figure 4.1.1 Chip Design Flow
Motivation
Circuit design of modules
Hspice simulation
Modify design and re-simulation
Overall circuit simulation (Hspice)
Layout
DRC and LVS
Measure considerations
Finish
DRC and LVS ERROR DRC and LVS OKOptimize
design
Debug
37
MOSFET Transistors Sizing (W/L)
M1, M2 2 M3, M4, M23, M24 2 M5, M6, M25, M26 8 M7, M8, M27, M28 2 M9, M29 4 M43 12.5 M44 10 M45 8 M46 2 M47 4 Mpor1, Mpor2 16 Mpor3 2 Mpor4 4 Mpor5, Mpor6 8 Mpor7, Mpor8 2
Table 4.1.1(a) MOSFET sizing
PNP Bipolar junction transistors Emitter area
Q1 25 mµ 2 Q2 25µm2× 8 Table 4.1.1(b) BJT sizing Resistors value R1 4K (low TC) R2 90 (high TC) R3 90 (high TC) R4 7K (low TC)
38
4.1.1 Op-Amp Simulation
Volts dB (lin) -25 -20 -15 -10 -5 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80Frequency (log) (HERTZ)
10 100 1k 10k 100k 1x 10x 100x 1g 10g
b..problem ptat
Figure 4.1.2 Op-Amp Open loop Gain
Volts Phase (lin)
-180 -160 -140 -120 -100 -80 -60 -40 -20 0 20 40 60 80 100 120 140 160 180
Frequency (log) (HERTZ)
10 100 1k 10k 100k 1x 10x 100x 1g
10g b..problem ptat
Figure 4.1.3 Op-Amp Phase Response
Our Op-Amp simulation is described in Figure 4.1.2 and Figure 4.1.3 Figure 4.1.2 show open loop gain of Op-Amp, and the open loop gain is around 78 dB. Figure 4.1.1 shows the phase response of Op-Amp, and the phase margin is around 60o. In general, to achieve the virtual short circuit of the input nodes, the open loop gain needs at least 60dB. For our proposed design, the open loop gain is large enough to achieve virtual short circuit at two input nodes. For stability, it have been explained how to choose phase margin as 60o in section 3.3. The 60o phase margin of our
39
4.1.2 Basic PTAT and BGR Current Simulation
After ensuring the Op-Amp to satisfy our requirements, the simulation of basic PTAT and BGR shown in Figure 3.2.1 are presented.
Figure 4.1.4 shows the basic PTAT current and reference temperature current. The PTAT current is the drain current of M47, and the reference temperature current is regression analysis of PTAT current. The range of PTAT current is over 23.4uA to 24.8uA. To satisfy our specification of temperature error, the error of PTAT current must be known. By subtract PTAT current from reference temperature current, the PTAT current error can be approximately estimated.
Figure 4.1.5 shows the approximation error of PTAT current, the range of temperature error is over -1oC to 1oC. The error sources of PTAT current consist of nonzero TC of resistors and nonzero offset voltage. In Figure 4.1.4, there is an assumption that the transistors in the PTAT circuit are all matched. The temperature error of simulation is caused by nonzero TC of resistors, because the resistors all have temperature dependence in the IC processes.
Figure 4.1.6 shows the simulation of basic BGR current, and the range of current is over 112.43uA to 112.505uA. From Eq. 3-3, it shows that the output reference current is inverse proportional toR . Unfortunately, thebe R has nonzero TC to be
introduce the additional error of reference current. The material of R is P+ poly be
without silicide, and the TC of this material is 764ppm/K. The TC of this BGR current is around 30ppm/oC over 25oC to 125oC, because the resistance model of the process ensures accuracy over this range.
To find the minimum supply voltage of the BGR current, Figure 4.1.7 shows the output reference current with the supply voltage varied from 0V to 3.3V. The simulation result shows that the minimum supply voltage of the proposed BGR current is 2.3V. If the supply voltage is lower than 2.3V, the BGR current will not normally work.
40 Result (lin) 23.4u 23.6u 23.8u 24u 24.2u 24.4u 24.6u 24.8u
Temperature (lin) (DEG_C)
20 40 60 80 100 120
problem ptat
Figure 4.1.4 PTAT Current versus Reference Temperature Current
Result (lin) -900m -800m -700m -600m -500m -400m -300m -200m
Temperature (lin) (DEG_C)
20 40 60 80 100 120
problem ptat
Figure 4.1.5 Basic PTAT Current Error
Reference Temperature Current PTAT Current
41 Result (lin) -112.505u -112.5u -112.495u -112.49u -112.485u -112.48u -112.475u -112.47u -112.465u -112.46u -112.455u -112.45u -112.445u -112.44u -112.435u -112.43u
Temperature (lin) (DEG_C)
20 40 60 80 100 120
problem ptat
Figure 4.1.6 Basic BGR Current Error
Result (lin) 0 10u 20u 30u 40u 50u 60u 70u 80u 90u 100u 110u
Voltage X (lin) (VOLTS)
0 1 2 3
problem ptat
42
4.1.3 Power-on-Reset Circuits Simulation
As described in section 2.2.3 and section 3.1.4, to prevent the PTAT circuit from settling to the wrong steady state condition (zero current state). A start-up or POR circuit is necessary in all practical PTAT circuits. However, start-up circuit consumes additional power caused by a branch being on. For less power consumption, a POR circuit is used. The simulation of POR circuit is shown that it can start up overall circuit and reduce power dissipation. The simplified POR circuit is shown in Figure 4.1.8.
Figure 4.1.8 Simplified POR circuit
Figure 4.1.9, and Figure 4.1.10 show the simulation of POR circuit. when the power supply is on, the voltage of node A, B, C, and D are shown in Figure 4.1.9. The node A and node B both charge from 0V to VDD, but the node A has less RC time
constant than node B. The node A has faster speed to reach VDD, so node C will latch
to VDD and node D will latch to 0V as described in Figure 4.1.9.
Now, let us check whether the PTAT circuits started up or not. In this Hspice simulation, the initial condition of EBJ voltage is first set to be zero. Then, the transient response is observed as Figure 4.1.10. The EBJ voltage indeed settles to the voltage of normal operation, but there is an overshoot in the transient. This is because the POR circuit consists of a latch, and that will reduce stability. For using POR circuits as start-up circuits, there is a trade off between stability and power dissipation.
43 Voltages (lin) 0 500m 1 1.5 2 2.5 3
Time (lin) (TIME)
0 200n 400n 600n 800n 1u problem ptat
Figure 4.1.9 The Transient Response of POR Circuit
Voltages (lin) 0 100m 200m 300m 400m 500m 600m 700m 800m 900m 1000m 1.1 1.2
Time (lin) (TIME)
0 200n 400n 600n 800n 1u
problem ptat
Figure 4.1.10 The Transient Response of PTAT Circuit A
B C
