IEEE MICROWAVE AND WIRELESS COMPONENTS LETTERS, VOL. 15, NO. 10, OCTOBER 2005 685
A Compact 2.4/5.2-GHz CMOS Dual-Band
Low-Noise Amplifier
Liang-Hung Lu, Member, IEEE, Hsieh-Hung Hsieh, Student Member, IEEE, and Yu-Shun Wang
Abstract—This letter presents a fully integrated 2.4/5.2-GHz dual-band low-noise amplifier (LNA) for WLAN applications. By switching the input transconductance and the output capacitance, the narrow-band gain and impedance matching are achieved at the 2.4-GHz and the 5.2-GHz frequency bands. Using a standard 0.18- m CMOS process, a compact dual-band LNA with a chip size comparable to a single-band one is realized in the proposed topology for a minimum hardware cost. The fabricated circuit exhibits gains of 10.1 dB and 10.9 dB, and noise figures of 2.9 dB and 3.7 dB at the two frequency bands, respectively.
Index Terms—Cascode amplifier, CMOS RF, dual-band, impedance matching, low-noise amplifier (LNA), multimode, source degeneration.
I. INTRODUCTION
I
N THE past few years, wireless local-area networks (WLANs) have been deployed all over the world as office and home communication infrastructures. The increasing de-mand has motivated the introduction of new WLAN standards such as IEEE 802.11a and IEEE 802.11g to meet various application requirements. However, the diversification of the WLAN standards poses significant challenges in the design of the RF front-ends. It is desirable to have a system that can sup-port multistandard operations while maintaining a competitive hardware cost.One of the technical bottlenecks for a multistandard trans-ceiver is the implementation of the low-noise amplifier (LNA) which can operate at two distinct frequency bands. Conven-tional dual-band architectures adopt two single-band LNAs in parallel [1]–[4], resulting in a high implementation cost due to the large chip area. Efforts have been made to realize a compact dual-band LNA by switched capacitors [5], [6], switched induc-tors [7], [8], and concurrent dual-band technique [9], [10]. How-ever, most of the techniques still require additional inductors and excess chip area to provide the dual-band operation. In this letter, a novel circuit topology for the 2.4/5.2-GHz dual-band LNA is presented in a standard 0.18- m CMOS process. By employing the proposed matching technique, the required LNA performance can be achieved at different frequency bands with a minimum hardware cost.
Manuscript received March 11, 2005; revised June 20, 2005. This work was supported in part by the National Science Council of Taiwan, R.O.C., under Grants 93-2220-E-002-003 and 93-2220-E-002-009, by the National Chip Im-plementation Center (CIC), and by the Radio Frequency Technology Center, National Nano Device Laboratories (NDL). The review of this letter was ar-ranged by Associate Editor F. Ellinger.
The authors are with the Department of Electrical Engineering and Graduate Institute of Electronics Engineering, National Taiwan University, Taipei 10617, Taiwan, R.O.C. (e-mail: lhlu@cc.ee.ntu.edu.tw).
Digital Object Identifier 10.1109/LMWC.2005.856845
Fig. 1. Complete schematic of the proposed dual-band LNA.
Fig. 2. Micrograph of the fabricated dual-band LNA.
Section II describes the design of the proposed dual-band LNA. Experimental results are shown in Section III and con-clusions are given in Section IV.
II. LNA TOPOLOGY ANDCIRCUITDESIGN
In order to implement the 2.4/5.2-GHz dual-band LNA with a minimum chip area, a switching-type circuit topology with a novel matching technique is proposed. Fig. 1 shows the com-plete schematic of the dual-band LNA with all on-chip compo-nents. The LNA includes a source-degenerated cascode ampli-fier with switched transistors and capacitors for the band selec-tion. The input stage is composed of , , , , ,
686 IEEE MICROWAVE AND WIRELESS COMPONENTS LETTERS, VOL. 15, NO. 10, OCTOBER 2005
Fig. 3. Measurement results of the switching-type dual-band LNA. (a)S . (b) S . (c) S . (d) Noise figure.
, and , and the output matching network consists of ,
, , , , and .
The circuit design starts with a single-band LNA at 5.2 GHz. When the LNA operates at the 5.2-GHz band, all of the switches - are open. In this case, is used as the input tran-sistor with a gate bias provided by through . The input impedance of the LNA at the higher frequency band can be ex-pressed as
(1) where and are the transconductance and the gate capacitance of , respectively, and is the operating fre-quency at this band. The values of , , , and the aspect ratio are determined to satisfy the required noise and impedance matching in a way similar to a conventional source-degenerated LNA design, while the output impedance is matched to 50 by the shunt inductor and the series capacitor . When the LNA operates at the 2.4-GHz band, all the switches are closed. A parallel connection of the input transistors and is established in this mode. The resulting input impedance at the lower frequency band is
(2)
where and are the transconductance and the gate capacitance of , respectively, and is the operating fre-quency at the lower band. Note that the gate bias voltage of
and switches to through
the voltage divider and . The transconductance in (2) can be a design parameter independent of the one in (1), providing one more degree of freedom to meet the dual-band matching conditions. As a result, the input matching can be achieved at 2.4-GHz by switching the finger number and the gate voltage of the input transistor without additional on-chip inductors. In consideration of the required chip area, a switched capacitor matching network is adopted at the output. When op-erating at the lower frequency band, capacitors and are included in the matching network by the switches - to provide a 50- output impedance.
In the dual-band LNA design, the switches are realized by NMOS transistors. Since the MOS switches exhibit nonideal characteristics at both on and off states, the influence of the switches on the circuit performance should be carefully inves-tigated. When a MOS switch is on, it is typically modeled as a finite on-resistance between the source and the drain. In gen-eral, the resistance tends to degrade the quality factor of the res-onators, resulting in a higher noise figure and a lower ampli-fier gain. The on-resistance can be minimized by increasing the finger numbers of the switches. However, the excess parasitic capacitance associated with the MOS switches imposes a limi-tation on the transistor sizes. In this design, the MOS switches
LU et al.: COMPACT 2.4/5.2-GHz CMOS DUAL-BAND LOW-NOISE AMPLIFIER 687
TABLE I
PERFORMANCESUMMARY OF THEDUAL-BANDLNA
are optimized to minimize the performance degradation in am-plifier gain and noise figure. The simulation results indicate a 1.5-dB decrease in gain and a 0.7-dB increase in noise figure due to the parasitics of the switches.
III. EXPERIMENTALRESULTS
Using a standard 0.18- m CMOS process, the fully inte-grated dual-band LNA has been designed and implemented for the 2.4/5.2-GHz frequency bands. The micrograph of the fabricated LNA is shown in Fig. 2. On-wafer probing was performed to characterize the -parameters and the noise figure of the LNA at both frequency bands. Fig. 3 shows the measurement results.
When the LNA is operating at the 5.2-GHz band, all the on-chip switches are turned off by the controlled voltage. With a power consumption of 5.7 mW from a 1.8-V supply, the LNA has a 10.9-dB gain and a 3.7-dB noise figure while maintaining an input return loss of 11 dB and an output return loss of 17 dB. The and IIP3 of the LNA are 16 dBm and 5 dBm, respectively.
The LNA operates at the 2.4-GHz band by turning on the on-chip switches - . In this mode, the LNA consumes a dc power of 11.7 mW. According to the measured results, the LNA has a gain of 10.1 dB and a noise figure of 2.9 dB while the input and output return losses are better than 10 dB at 2.4 GHz. The and IIP3 of the LNA are 7 dBm and 4 dBm, re-spectively. The performance of the dual-band LNA is summa-rized in Table I.
IV. CONCLUSION
A novel circuit topology for dual-band LNA is presented in this letter. The input matching conditions are satisfied by switching the finger number and the bias voltage of the input transistor, while the output matching is achieved by a switched capacitor matching network. Using a standard 0.18- m CMOS process, a 2.4/5.2-GHz dual-band LNA was designed and implemented. The fabricated circuit exhibits a 10.1-dB gain and a 2.9-dB noise figure at the 2.4-GHz band, and a 10.9-dB gain and a 3.7-dB noise figure at the 5.2-GHz band. With a negligible increase in chip area compared with a single-band design, the dual-band LNA provides a cost-competitive solution to WLAN applications.
REFERENCES
[1] S. Wu and B. Razavi, “A 900-MHz/1.8-GHz CMOS receiver for dual-band applications,” IEEE J. Solid-State Circuits, vol. 33, no. 12, pp. 2178–2185, Dec. 1998.
[2] J. Tham, M. Margarit, B. Pregardier, C. Hull, R. Magoon, and F. Carr, “A 2.7 V 900-MHz/1.9-GHz dual-band transceiver IC for digital wire-less communication,” IEEE J. Solid-State Circuits, vol. 34, no. 3, pp. 286–291, Mar. 1999.
[3] J. Imbornone, J.-M. Mourant, and T. Tewksbury, “Fully differential dual-band image reject receiver in SiGe BiCMOS,” in Proc. IEEE RFIC
Symp., 2000, pp. 147–150.
[4] W. Titus, R. Croughwell, C. Schiller, and L. DeVito, “A Si BJT dual-band receiver IC for DAB,” in IEEE MTT-S Int. Dig., vol. 1, 1998, pp. 345–348.
[5] W.-S. Wuen and K.-A. Wen, “Dual-band switchable low noise amplifier for 5-GHz wireless LAN radio receivers,” in Proc. IEEE Midwest Symp.
Circuits Systems, vol. 2, 2002, pp. II-258–II-261.
[6] V. Vidojkovic, J. van der Tang, E. Hanssen, A. Leeuwenburgh, and A. van Roermund, “Fully-integrated DECT/Bluetooth multiband LNA in 0.18m CMOS,” in Proc. IEEE Int. Symp. Circuits Systems, vol. 1, 2004, pp. I-565–I-568.
[7] T. K. K. Tsang and M. N. El-Gamal, “Dual-band sub-1 V CMOS LNA for 802.11a/b WLAN applications,” in Proc. IEEE Int. Symp. Circuits
Systems, vol. 1, 2003, pp. 217–220.
[8] Z. Li, R. Quintal, and K. K. O, “A dual-band CMOS front-end with two gain modes for wireless LAN applications,” IEEE J. Solid-State Circuits, vol. 39, no. 11, pp. 2069–2073, Nov. 2004.
[9] H. Hashemi and A. Hajimiri, “Concurrent multiband low-noise ampli-fiers – Theory, design, and applications,” IEEE Trans. Microw. Theory
Tech., vol. 50, no. 1, pp. 288–301, Jan. 2002.
[10] S. Mou, J. Ma, K. S. Yeo, and M. A. Do, “An integrated SiGe dual-band low noise amplifier for Bluetooth, HiperLAN and wireless LAN applications,” in Proc. Eur. Microwave Conf., vol. 1, Oct. 2003, pp. 5–8.
