SCR-based transient detection circuit for on-chip protection design against system-level electrical transient disturbance

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SCR-based transient detection circuit for on-chip protection design

against system-level electrical transient disturbance

Ming-Dou Ker

a,b,⇑

_{, Wan-Yen Lin}

a

_{, Cheng-Cheng Yen}

a a

Institute of Electronics, National Chiao-Tung University, 1001 University Road, Hsinchu, Taiwan

b

Department of Electronic Engineering, I-Shou University, Kaohsiung, Taiwan

a r t i c l e

i n f o

Article history:

Received 18 August 2012

Received in revised form 13 July 2013 Accepted 20 August 2013

Available online 27 September 2013

a b s t r a c t

A new silicon controlled rectifier (SCR)-based transient detection circuit for on-chip protection design against system-level electrical transient disturbance is proposed. The circuit function to detect positive or negative electrical transients during system-level electrostatic discharge (ESD) and electrical fast tran-sient (EFT) tests has been verified in silicon chip. The experimental results in a 0.18-lm CMOS process have confirmed that the new proposed detection circuit can successfully memorize the occurrence of sys-tem-level electrical transient disturbance events. The detection results can be cooperated with firmware design to execute system recovery procedures, therefore the immunity of microelectronic systems against system-level ESD or EFT tests can be effectively improved.

1. Introduction

System-level electrical transient disturbance has become an important immunity issue in microelectronic products which are equipped with CMOS integrated circuits (ICs)[1–6]. With the in-crease of electromagnetic emission sources in a microelectronic system, the environment where the CMOS ICs located has more electrical transient disturbance than before. The microelectronic systems were typically requested to pass the immunity tests, including the system-level electrostatic discharge (ESD) test of IEC 61000-4-2 standard[7]and the electrical fast transient (EFT) test of IEC 61000-4-4 standard[8].

Compared with the component-level ESD tests (where the ob-jects under test are ICs), the system-level ESD test aims to evaluate the robustness of microelectronic products against ESD events. The equivalent circuit of human body model (HBM) in the component-level ESD test is shown inFig. 1(a). The HBM has the charging (en-ergy-storage) capacitor of 100 pF and a discharging resistor of 1.5 kX. The equivalent circuit of ESD gun used in the system-level ESD test is shown inFig. 1(b), where the charging capacitor (dis-charging resistor) is 150 pF (330X) [7]. Thus, comparing to the ESD current in component-level ESD test, the system-level ESD test with the same ESD voltage has much larger peak ESD current (5– 6 times larger) to cause serious damages on electronic products. During the system-level ESD test, the voltage waveforms on the power line of the IC inside the microelectronic system would no

longer maintain their normal voltage levels. The typical under-damped sinusoidal voltage with the amplitude of several tens volts induced by system-level ESD test is shown inFig. 2. In addition, the simpliﬁed circuit diagram of EFT generator is shown inFig. 3with the impedance matching resistor Rmof 50Xand the dc blocking

capacitor Cdof 10 nF, as speciﬁed in the EFT test standard of IEC

61000-4-4. The EFT is a test with repetitive burst string consisting of a number of fast pulses, coupled into power lines, control line, and signal ports of microelectronic system. For EFT pulses with the repetition frequency of 5 kHz, the measured 200-V voltage waveforms on the 50Xload are shown inFig. 4. Due to impedance matching, the measured output voltage pulse peak is half of the EFT voltage pulse. The waveform of a single pulse has a rise time of 5 ns and the pulse duration of 50 ns, as shown in the inset ﬁgure ofFig. 4.

Such ESD/EFT-generated transient voltages are quite large (with the amplitude of several tens to hundreds volts) and fast (with the period of several tens nanoseconds), those could randomly couple to the power, ground, or input/output (I/O) pins of ICs inside the microelectronic system. Such fast transients often cause the micro-electronic system to be upset or frozen after the system-level ESD or EFT tests. It was reported that, the underdamped sinusoidal volt-age waveforms during system-level ESD tests coupled on VDDand

VSS pins of a super twisted nematic (STN) liquid crystal display

(LCD) driver circuit caused abnormal display function of LCD panel

[9]. It was also proven that the EFT-induced transient disturbance can cause electrical-over-stress (EOS) damage in a AC-power equipment[10]. Such high-energy ESD/EFT-induced fast transients caused serious reliability events on CMOS ICs inside the microelec-tronic products[11–18].

http://dx.doi.org/10.1016/j.microrel.2013.08.010

⇑ Corresponding author at: Institute of Electronics, National Chiao-Tung Univer-sity, 1001 University Road, Hsinchu, Taiwan. Tel.: +886 3 5131573; fax: +886 3 5715412.

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The additional noise filter networks, such as the magnetic core, capacitor filter, ferrite bead (FB), transient voltage suppressor (TVS), or RC filters, were often used to improve the immunity of microelectronic products against electrical transient disturbance

[19,20]. However, the additional discrete noise-bypassing compo-nents substantially increase the total cost of microelectronic prod-ucts. Therefore, the chip-level solutions to meet system-level ESD/ EFT speciﬁcations for microelectronic products without using addi-tional discrete noise-decoupling components on the printed circuit board (PCB) are highly desired by IC industry[21–26].

In this work, a new on-chip SCR-based transient detection cir-cuit is proposed to detect the system-level electrical transient

dis-turbance under the system-level ESD or EFT tests[27]. In this new design, the p-type substrate-triggered SCR (P_STSCR) device is used as the storage cell[28–30]to memorize the occurrence of system-level ESD or EFT events. Such a SCR-based circuit design to detect the electrical transient disturbance is ﬁrst reported in the litera-ture. The transient-induced latchup (TLU) measurement[31], sys-tem-level ESD gun [32], and EFT test [33] are used to evaluate the detection function of the new proposed detection circuit. The experimental results with the chip fabricated in a 0.18-

l

m CMOS process have veriﬁed that the new proposed on-chip SCR-based transient detection circuit can successfully detect and memorize the occurrence of electrical transients generated by system-level ESD or EFT tests.

2. Solutions to overcome system-level transient disturbance 2.1. Traditional solution

In order to meet the system-level ESD specifications, there are two main methods[19,20]. One method is to add some discrete noise-bypassing components or board-level noise filters into the microelectronic products to decouple, bypass, or absorb the electri-cal transient voltage (energy) under system-level ESD or EFT tests. As shown inFig. 5, some discrete components (such as the ferrite bead (FB) and RC low-pass filters) are added into the printed circuit board (PCB) of an universal serial bus (USB) product to restrain the electrical transients. The immunity of microelectronic system (equipped with CMOS ICs) against electrical transient disturbance can be significantly enhanced by choosing proper noise filter net-works. The other method is to regularly check the system abnor-mal conditions by using an external hardware timer, such as

Fig. 2. The measured waveforms of transient noise voltage on the power pin of CMOS IC in the equipment under test (EUT) during the system-level ESD test.

Fig. 3. Simpliﬁed circuit diagram of EFT generator[8], which was speciﬁed in IEC 61000-4-4.

Fig. 4. Measured voltage waveforms of EFT pulses on a 50-X load with the repetition rate of 5 kHz and EFT voltage of +200 V.

Fig. 1. Equivalent circuits of (a) human body model (HBM) used in the component-level ESD test, and (b) ESD gun used in the system-component-level ESD test. The charging (energy-storage) capacitors and the discharging resistors are different in these two different ESD test standards.

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watch dog timer. The additional hardware timer is often designed with registers or flip flops as a reference clock for system operation if the main program was locked or frozen due to some fault condi-tions. However, during system-level ESD or EFT tests, the logic states stored in the registers or flip flops of hardware timer would be also destroyed, which still causing malfunction or frozen condi-tion in the system operacondi-tion.

2.2. Hardware/ﬁrmware co-design

It had been reported that the hardware/ﬁrmware co-design can effectively improve the system-level ESD susceptibility of the CMOS IC products[21]. As shown inFig. 6with hardware/ﬁrmware co-design, when ESD-induced transient disturbance coupling to VDD/VSSlines, the detection results (VOUT) from the on-chip

tran-sient detection circuit can be temporarily stored as a system recov-ery index for ﬁrmware check. For example, the output (VOUT) state

of the on-chip transient detection circuit and the ﬁrmware index are initially set to logic ‘‘1’’. When the fast electrical transient hap-pens, the on-chip transient detection circuit can detect the fast electrical transient and then change the output state (VOUT) from

logic ‘‘1’’ to logic ‘‘0’’. The system recovery index is therefore ﬂagged at logic ‘‘0’’, which will inform the ﬁrmware to recover all system functions to a stable state as soon as possible. After the

recovery procedure, the output state of the on-chip transient detection circuit and the firmware index are re-set to logic ‘‘1’’ again for detecting the next electrical transient disturbance events. In IEC 61000-4-2 standard, four classifications of system-level ESD test results have been defined, as listed in Table 1. In order to solve the frozen states caused by system-level ESD test, micro-electronic products can be manually reset by operator interven-tion, which meets the criterion of ‘‘Class C’’ in the standard. However, most microelectronic products are required to automat-ically recover the system functions without operator intervention to meet the ‘‘Class B’’ criterion by IC industry. By cooperating with the on-chip transient detection circuit, a hardware/firmware co-design solution can be provided to release the locked states caused by electrical transient disturbance without additional manual operations.

3. New on-chip SCR-based transient detection circuit

The new SCR-based transient detection circuit is designed to de-tect the positive or negative fast electrical transients during the system-level ESD or EFT tests. Under the normal circuit operation condition (VDD= 3.3 V), the output state of the new proposed

SCR-based transient detection circuit is kept at 3.3 V as logic ‘‘1’’. After the transient disturbance, the output state will transit from

Fig. 5. A traditional solution to overcome the system-level electrical transient disturbance by adding board-level discrete components, such as the ferrite bead (FB) and RC low-pass ﬁlters.

Fig. 6. Hardware/ﬁrmware co-design for system recovery by using the detection results of the on-chip transient detection circuit.

correction of which requires operator intervention. (Manual Recovery)

Class D Loss of function or degradation of performance which is not recoverable, owing to damage to hardware or software, or loss of data.

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3.3 V to 0 V. Therefore, the new proposed SCR-based transient detection circuit can memorize the occurrence of system-level electrical transient disturbance events.

3.1. Silicon controlled rectiﬁer (SCR)

The silicon controlled rectiﬁer (SCR) was traditionally used as the on-chip ESD protection device due to its high ESD robustness within small layout area[34]. The anode of SCR is connected to the P+ and N+ diffusions in N-well (NW), whereas the cathode of SCR is connected to the N+ and P+ diffusions in P-well (PW). The equivalent circuit of the SCR structure is composed of a lateral NPN and a vertical PNP bipolar transistor to form the 2-terminal/ 4-layer PNPN (P+/NW/PW/N+) structure. The original switching voltage of the SCR device is decided by the avalanche breakdown voltage of the N-well/P-well junction. It has been reported that the turn-on mechanism of SCR device is essentially a current trig-gering event[35]. While a current is applied to the base or sub-strate of SCR device, the SCR can be quickly triggered into its latching state. The device cross-sectional view and the layout top view of the p-type substrate-triggered SCR (P_STSCR) are shown inFig. 7(a) and (b), respectively. An extra P+ diffusion is inserted into the P-well of the P_STSCR device structure and connected out as the p-trigger node of the P_STSCR device. The layout param-eters, D and W, represent the distance between the anode and cathode, and the distance between the adjacent well contacts, respectively. In this work, the P_STSCR structure with the layout parameters of D = 0.86

l

m and W = 3.8

l

m in a 0.18-

l

m CMOS process with 3.3-V devices is used as the memory unit to

memorize the occurrence of electrical transient disturbance. The SCR in this work is not used as on-chip ESD protection device, but as the memory unit in the transient detection circuit.

The setup to measure the dc current–voltage (I–V) curves of the fabricated P_STSCR device under substrate-triggered current (Ibias)

is shown inFig. 8. The measured dc I–V curves of the P_STSCR un-der different substrate-triggered currents are shown in Fig. 9. When the substrate-triggered current applied to the p-trigger node is increased from 1 mA to 4 mA, the switching voltage of P_STSCR is reduced from 8.6 V to 1.5 V. With the substrate-triggered cur-rent, the P_STSCR structure can be triggered into the latching state without involving the avalanche junction breakdown.

3.2. SCR-Based transient detection circuit

In the previous works, some on-chip transient detection circuits were reported to detect the electrical transient disturbance under system-level ESD or EFT tests[21–26]. The traditional memory unit used to memorize the occurrence of system-level electrical tran-sient disturbance was the ‘‘latch’’, which was formed by two inverters.

The new proposed on-chip SCR-based transient detection cir-cuit of this work is shown inFig. 10. The P_STSCR device shown inFig. 7is used as the memory unit to memorize of the occurrence of system-level electrical transient disturbance. It has been proven

Fig. 7. (a) Device cross-sectional view and (b) layout top view, of the p-type substrate-triggered SCR (P_STSCR) with the layout parameters of D = 0.86lm and W = 3.8lm.

Fig. 8. Measurement setup of P_STSCR device under different trigger currents.

Fig. 9. The measured I–V characteristics of P_STSCR device under different trigger currents.

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that SCR device can be triggered under system-level ESD or EFT tests, no matter which polarity (positive and negative) of the ESD or EFT voltage is [6]. The anode of P_STSCR is connected to the drain of PMOS (Mpr) device. The gate of PMOS (Mpr) is biased to

VSSby the initial reset signal (VRESET) to set the initial output

volt-age (VOUT2) at 3.3 V. The RC-delay circuit and the inverter are

de-signed to provide the SCR triggering current. Under the system-level ESD or EFT events, the transient voltage has a fast rise time in the order of nanosecond (ns). The voltage level of VX in the

RC-delay circuit is initially biased at VDDand has slower voltage

re-sponse, because the RC-delay circuit is designed with a time con-stant in the order of microsecond (

l

s). When the electrical transient disturbance coupling to the VDDline, the PMOS device

(Mp1) can be turned on by the overshooting voltage at VDDto

con-duct trigger current into the p-trigger node. The SCR device is therefore turned on to pull down the output voltage (VOUT1) level

to the SCR holding voltage of 1.2 V. In the two-inverter buffer stage, the logic threshold voltage of inverter1 (INV_1) is designed at 2.3 V and that of inverter2 (INV_2) is 1.7 V. Therefore, after electrical transient disturbance, the VOUT2of the proposed

detec-tion circuit will be changed from 3.3 V to 0 V to memorize the occurrence of system-level ESD/EFT-induced transient disturbance. The current ﬂowing through the turned-on SCR is limited by the PMOS device (Mp1), which will not cause reliability issue on the

SCR used in the proposed transient detection circuit. The reset function (VRESET) is used to release the turn-on state of SCR device

by turning Mproff, and then reset the output voltage (VOUT2) back

to 3.3 V again for detecting the next system-level transient disturbance.

4. Experimental results

The proposed detection circuit has been designed and fabri-cated in a 0.18-

l

m CMOS process with 3.3-V devices. The

fabricated test chip with the silicon area of 125

l

m 150

l

m for the SCR-based transient detection circuit is shown inFig. 11. 4.1. Transient-induced latchup (TLU) test

To evaluate the system-level ESD immunity of a single IC inside the equipment under test (EUT), a component-level transient-in-duced latchup (TLU) measurement setup was reported with the following two advantages[31]. First, the TLU immunity of a single IC can be evaluated by the measured voltage and current wave-forms through the oscilloscope. Second, with the ability of generat-ing an underdamped sinusoidal voltage, it can be accurately simulated how an IC inside the EUT is disturbed by the ESD-gener-ated transient disturbance during the system-level ESD test.Fig. 12

illustrates such a component-level TLU measurement setup. A charging capacitance of 200 pF is used to store the charges as the TLU-triggering source, VCharge, and then the stored charges are

dis-charged to the device under test (DUT) through the relay. The underdamped sinusoidal voltage generated by TLU measurement is similar to the transient voltage on the power pins of CMOS ICs under the system-level ESD tests. Moreover, a small current-limit-ing resistance of 5Xis recommended to protect the DUT from electrical-over-stress (EOS) damage during the high-current (low-impedance) latching state.

Fig. 13(a) and (b) show the measured VDD, VOUT1, and VOUT2

tran-sient voltage waveforms of the SCR-based trantran-sient detection cir-cuit under the TLU tests with VCharge of +9 V and 1 V,

respectively. As shown inFig. 13(a), under the TLU test with VCharge

of +9 V, VDDbegins to increase rapidly from 3.3 V with

positive-going underdamped sinusoidal voltage waveform. During the TLU test, VOUT1and VOUT2are inﬂuenced simultaneously by the

posi-tive-going underdamped sinusoidal voltage coupled to VDDpower

line. After the TLU test with the VChargeof +9 V, the output voltage

VOUT1of the proposed transient detection circuit is changed from

Fig. 10. The new proposed on-chip SCR-based transient detection circuit. The P_STSCR is used as memory cell to memorize the occurrence of electrical transient disturbance.

Fig. 11. Chip photo of the new proposed on-chip SCR-based transient detection circuit fabricated in a 0.18-lm CMOS process with 3.3-V devices. The silicon area

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3.3 V to 1.2 V (the SCR holding voltage). Through two-inverter buf-fer stage, VOUT2of the proposed detection circuit is pulled down to

0 V. InFig. 13(b), under the TLU test with VChargeof 1 V, VDD

be-gins to decrease rapidly from 3.3 V with negative-going

under-damped sinusoidal voltage waveform. During this TLU test, VOUT1

and VOUT2 are inﬂuenced simultaneously by the negative-going

underdamped sinusoidal voltage. After the TLU test with the VCharge

of 1 V, the VOUT2of the proposed transient detection circuit also

transits from 3.3 V to 0 V.

From the TLU test results, the proposed SCR-based transient detection circuit can successfully memorize the occurrence of elec-trical transients. With positive or negative underdamped sinusoi-dal voltages coupling to VDD power line, the output voltage

(VOUT2) of the proposed SCR-based transient detection circuit can

be changed from logic ‘‘1’’ to logic ‘‘0’’ after TLU tests. 4.2. System-level ESD test

In IEC 61000-4-2, two test modes have been speciﬁed, which are the air-discharge and contact-discharge test modes. The con-tact discharge is applied to the conductive surfaces of the EUT (di-rect application) or to the coupling planes (indi(di-rect application). Contact discharge is further divided into direct discharge to the system under test, and indirect discharge to the horizontal or ver-tical coupling planes.Fig. 14shows the measurement setup of the system-level ESD test standard with indirect contact-discharge test mode. The measurement setup of system-level ESD test consists of a wooden table on the grounded reference plane (GRP). In addition, an insulation plane is used to separate the EUT from the horizontal coupling plane (HCP). The HCP are connected to the GRP with two 470 kXresistors in series[7]. When the ESD gun zaps the HCP, the electromagnetic interference (EMI) coming from ESD gun will be coupled into all CMOS ICs inside EUT. The power lines of CMOS ICs inside EUT will be disturbed by the ESD-coupled energy.

By monitoring in the oscilloscope, the transient responses on the power lines of CMOS ICs can be recorded and analyzed. Before each system-level ESD test, the initial output voltages (VOUT1and

VOUT2) of the proposed detection circuit are all reset to 3.3 V. After

each system-level ESD test, the output voltages (VOUT1and VOUT2)

are monitored to check their ﬁnal voltage levels. Thus, the function of the proposed detection circuit can be evaluated by system-level ESD tests in such a measurement setup.

The measured VDD, VOUT1, and VOUT2waveforms of the proposed

detection circuit under system-level ESD test with the ESD voltage of +0.35 kV zapping on the HCP are shown inFig. 15(a). VDDbegins

to increase rapidly from the normal voltage level of 3.3 V. Mean-while, VOUT1and VOUT2begin to change under such a high-energy

ESD stress. During the fast transient disturbance, VDD, VOUT1, and

Fig. 13. Measured VDDand VOUTwaveforms on the SCR-based transient detection

circuit under TLU tests with the VChargeof (a) +9 V and (b) 1 V.

Fig. 14. Measurement setup for system-level ESD test with indirect contact-discharge test mode[7]to evaluate the detection function of the SCR-based transient detection circuit.

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VOUT2are inﬂuenced simultaneously. Finally, VOUT1is pulled down

to 1.2 V. Through buffer stages, VOUT2of the proposed detection

cir-cuit transits from 3.3 V to 0 V.

The measured VDD, VOUT1, and VOUT2waveforms of the proposed

detection circuit under system-level ESD test with the ESD voltage of 0.2 kV zapping on the HCP are shown inFig. 15(b). During the ESD-induced transient disturbance, VDDbegins to decrease rapidly

from the original voltage level of 3.3 V. Finally, the output voltage (VOUT2) of the proposed transient detection circuit is changed from

3.3 V to 0 V.

Therefore, the new proposed SCR-based transient detection cir-cuit can successfully detect the electrical transients under system-level ESD tests with positive or negative ESD voltages.

4.3. Electrical fast transient (EFT) test

The measurement setup for EFT test combined with attenuation network is shown inFig. 16. EFT generator is connected to the DUT with VDDof 3.3 V through the attenuation network. In order to

sim-ulate the degraded EFT-induced transient disturbance on CMOS ICs inside the microelectronic products, the attenuation network with 40 dB degradation is used in this work. The amplitude of EFT-in-duced transients can be adjusted by the attenuation network.

Fig. 17(a) and (b) show the measured VDD, VOUT1, and VOUT2

tran-sient responses of the proposed detection circuit under the EFT tests with input EFT voltages of +750 V and 400 V, respectively. As shown inFig. 17(a), under the EFT test with positive voltage of +750 V, VDDbegins to increase rapidly from 3.3 V with positive

exponential voltage pulse. During the EFT test, VOUT1and VOUT2

are inﬂuenced simultaneously by the positive exponential voltage pulse coupling to VDDpower line. After the +750-V EFT test, the

Fig. 15. Measured VDDand VOUTtransient voltage waveforms of the SCR-based

transient detection circuit under system-level ESD tests with ESD voltage of (a) +0.35 kV and (b) 0.2 kV.

Fig. 16. Measurement setup for EFT test combined with attenuation network[8].

Fig. 17. Measured VDDand VOUTwaveforms on the SCR-based transient detection

circuit under EFT tests with (a) +750-V and (b) 400-V EFT voltages combined with attenuation network.

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output voltage VOUT1(VOUT2) of the proposed detection circuit

tran-sits from 3.3 V to 1.2 V (0 V). InFig. 17(b), under the EFT test with negative voltage of 400 V, VDDbegins to decrease rapidly from

3.3 V with negative exponential voltage pulse. After the EFT test, the output voltage VOUT2of the proposed detection circuit transits

from logic ‘‘1’’ to logic ‘‘0’’.

From the EFT test results shown inFig. 17(a) and (b), with po-sitive or negative EFT voltages coupled to VDDpower line, the

out-put voltage (VOUT2) of the proposed detection circuit can be

changed from 3.3 V to 0 V. Therefore, the new proposed on-chip SCR-based transient detection circuit can successfully memorize the occurrence of EFT-induced exponential pulse transient disturbance.

5. Conclusion

A new SCR-based transient detection circuit to detect system-level electrical transient disturbance has been implemented in a 0.18-

l

m CMOS process with 3.3-V devices. By using P_STSCR vice and RC-delay circuit, the proposed detection circuit is de-signed to detect fast electrical transients during the system-level ESD or EFT tests. Experimental results in silicon chip have success-fully verified that the proposed detection circuit can successsuccess-fully memorize the occurrence of electrical transients during system-le-vel ESD or EFT tests. With hardware/firmware co-design method, the output state of the proposed SCR-based transient detection cir-cuit can be used as the firmware index to provide an effective solu-tion against the system malfuncsolu-tion caused by system-level electrical transient disturbance.

Acknowledgements

This work was supported in part by National Science Council (NSC), Taiwan, under Contracts of NSC 102-2220-E-009-004 and NSC 101-3113-P-110-004; and partially supported by the ‘‘Aim for the Top University Plan’’ of National Chiao-Tung University and the Ministry of Education, Taiwan.

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[33] Technical speciﬁcation, EMCPro Plus EMC test system, (USA): Thermo Fisher Scientiﬁc Inc.

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