The Impact of Strain Technology on FUSI Gate SOI CMOSFET

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IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 9, NO. 1, MARCH 2009 1

The Impact of Strain Technology on

FUSI Gate SOI CMOSFET

1

2

Wen-Kuan Yeh, Member, IEEE, Jean-An Wang, Ming-Hsing Tsai, Chien-Ting Lin, and Po-Ying Chen

3

Abstract—In this paper, the impact of strain engineering on

4

device performance and reliability for fully silicide gate

silicon-5

on-insulator CMOSFET was investigated. With characterizing

6

device’s electrical property after hot carrier (HC) and positive/

7

negative bias instability voltage stressing, we found similar

en-8

hancement on device performance but different behavior on

9

voltage-stressing-induced device degradation for n/pMOSFETs.

10

Related noise analysis and charge pumping techniques were used

11

to investigate the strain-induced oxide defect which will accelerate

12

device degradation after long-time HC voltage stressing and/or

13

bias instability voltage stressing.

14

Index Terms—Fully silicide (FUSI), hot carrier (HC) and bias

15

instability, strain engineering, tensile-strain and

compressive-16

strain contact etch stop layer (CESL).

17

I. INTRODUCTION

18

A

S THE GATE length of CMOSFET scales is below

19

100-nm regime, increased channel doping is required to

20

suppress short-channel effects that will cause higher ionized

21

impurity scattering and further result in the degradation of

car-22

rier mobility [1]. Thus, a strained technology has been proposed

23

[2]–[7] in enhancing channel carrier mobility to improve device

24

performance particularly for deep-submicrometer MOSFET

25

design. However, extra process steps are always required for

26

these strain technologies; thus, for production issue, simpler

27

strained engineering such as high-strained contact etch stop

28

layer (CESL) that can generate higher strain to induce great

29

carrier mobility enhancement in the channel even at large

ver-30

tical electric fields was introduced. These strained technologies

31

provide extra gain on device characteristic, which have been

32

implemented extensively to improve device performances as

33

device size scaled to 90-nm node and beyond [8]. On the

34

other hand, the aggressive scaling of MOSFETs puts severe

35

constraints on the gate stack; thus, metal gate electrodes are

36

projected to replace poly-Si gate for future CMOS devices

37

in order to achieve equivalent oxide thickness < 1 nm for

38

Manuscript received July 24, 2008; revised October 7, 2008. This work was supported by the National Science Council under Contract NSC 96-2221-E-390-028.

W.-K. Yeh and J.-A. Wang are with the Department of Electrical Engi-neering, National University of Kaohsiung, Kaohsiung 811, Taiwan (e-mail: wkyeh@nuk.edu.tw).

M.-H. Tsai is with the National University of Kaohsiung, Kaohsiung 811, Taiwan.

C.-T. Lin is with the Central R&D Division, United Microelectronics Corpo-ration, Kaohsiung 811, Taiwan.

P.-Y. Chen is with the Department of Information Engineering, I-Shou University, Kaohsiung 840, Taiwan.

Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TDMR.2008.2010622

Fig. 1. Schematic structure view of SOI MOSFET with Ni-FUSI gate.

semiconductor industry requirement [9]. Metal gates have many

39

advantages over poly-Si gates, such as no boron penetration,

40

no polydepletion effects, low resistance, and suppressed re-

41

mote charge scattering [10]. However, for the requirements

42

of circuit design with symmetrical threshold voltage, tunable

43

work function is necessary for nMOSFET (in the range of

44

4.1–4.4 eV) and pMOSFET (in the range of 4.8–5.1 eV). Sev-

45

eral approaches have been proposed, including midgap metal

46

gate [11], dual-metal CMOS integration [12]–[14], and fully

47

silicided (FUSI) metal gate [15]–[19]. FUSI metal gates have

48

some advantages over other metal gates, including tunable

49

work function and CMOS compatible processing. Recently,

50

NiSi FUSI gates have been demonstrated as appropriate gate

51

technologies for n/pMOSFETs [20], [21]. It is a very useful

52

method to improve device performance by combining CESL

53

with FUSI gate technology. However, integrating these strain

54

technologies to enhance device characteristics more efficiently

55

and related investigation of the impact of these strain technolo-

56

gies on reliability (including hot-carrier (HC) voltage stressing

57

and bias-instability inspection) have not been reported yet,

58

particularly for silicon-on-insulator (SOI) devices. It is believed

59

that SOI technology (including partially depleted (PD) SOI,

60

fully depleted SOI, and multigate) with strain engineering is

61

one of the most promising candidates for solving device per-

62

formance and power limitations. In this paper, we investigate

63

the impact of CESL technique on FUSI gate SOI CMOSFET

64

performance and voltage-stressing-induced (including HC and

65

bias instability) device degradation. Related noise analyses, as

66

well as charge pumping techniques, were employed on the

67

inspection of strain-induced defects.

68

II. EXPERIMENTAL

69

Fig. 1 shows the simplified process flow for preparing

70

the FUSI gate SOI MOSFET with high-strain CESL. PD

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Fig. 2. Larger ID happened on SOI nMOSFET with higher tensile CESL

layers. The inset shows similar tendency on Gmbehavior.

SOI CMOSFET samples with a 40-nm-thick Si active layer

72

and a 200-nm-thick buried oxide were fabricated on

oxygen-73

implanted (100) channel orientation SOI substrate. After

shal-74

low trench isolation, a 1.6-nm nitrided gate oxide was grown

75

using rapid thermal oxidation in a NO ambient. Then,

compos-76

ite oxide/SiN spacers and source/drain junctions were formed

77

using arsenic/boron ion implantations, respectively, followed

78

by a low-temperature annealing process. A 90-nm technology

79

was used as a vehicle to demonstrate device performances with

80

a 120-nm-thick poly-Si gate. Followed by polypatterning and

81

source–drain activation (1060-

◦

C spike anneal), a 50-nm-thick

82

Ni was deposited because of its lower thermal budget and

83

better property [8]. For fully Ni-FUSI gate electrode formation,

84

Ni-FUSI with a resistivity of 3.11

× e

−5

Ω

· cm was formed

85

in a two-step process (RTP

1

340

◦

C/RTP

2

520

◦

C). Then, three

86

kinds of SiN film with different strains were deposited to

87

prevent exposing the gate electrode from backend process, and

88

also, low-tensile 38-nm CESL, high-tensile 70-nm CESL, and

89

highly compressive 70-nm CESL were deposited. The

low-90

tensile 38-nm CESL is a standard recipe for 90-nm CMOSFET

91

and is a reference sample compared to other two higher strain

92

SIN films in this paper. After wafer out of these devices, dc

93

measurements were carried out on an HP4156 under various

94

drain voltages (

|V

D

| = 0−1.4 V) and gate voltages (|V

G

| =

95

0 −1.4 V). An HP4145/HP35670A dynamic signal analyzer

96

and a BTA9812 noise analyzer were used to inspect the

low-97

frequency noise spectrum from 10 to 100 kHz. For reliability

98

check, HC voltage stressing, negative bias instability (NBI),

99

and positive bias instability (PBI) inspection were performed up

100

to

|V

G

| = |V

D

| = 1.2 V, V

G

= 2.5 V, and V

G

=

−2.7 V with

101

100-min voltage stressing for n/pMOS, respectively.

102

III. RESULTS AND

DISCUSSION

103

Schematic view of a cross-sectional structure for FUSI gate

104

SOI MOSFET with various CESL processes was shown in

105

Fig. 1. For nMOSFET, channel electron mobility can be

in-106

duced from CESL and increased as the strain of these CESLs

107

was increased. Apparently, device driving capability was

en-108

hanced, particularly with higher tensile CESL for nMOSFET,

109

as shown in Fig. 2. Similar tendency was found in device’s

110

transconductance (G

m

) enhancement, as shown in Fig. 2.

111

Fig. 3. Larger GIDL and subthreshold swing happened on SOI nMOSFET with higher tensile CESL layers. The inset shows similar tendency on CESL-induced gate leakage.

Fig. 4. Larger IDhappened on SOI pMOSFET with more highly

compres-sive CESL layers. The inset shows similar tendency on CESL-induced Gm

characteristic.

However, oxide defects, which are located at Si/SiO

2

interface

112

or bulk oxide (border), were also induced by these higher

113

tensile CESL films, and these defects will degrade the device’s

114

subthreshold swing and increase the gate-induced drain leakage

115

(GIDL) [20], as shown in Fig. 3. Because of these high-tensile

116

CESL-induced defects that are located around the interface of

117

gate oxide and Si substrate, it results in larger gate leakage in

118

nMOSFET, as shown in Fig. 3. For pMOSFET, compressive

119

CESL is useful to enhance the channel hole mobility for device

120

performance improvement. [21] Compared with conventional

121

pMOSFET with low-strain CESL, higher device driving capa-

122

bility can be found in pMOSFET, particularly with more highly

123

compressive CESL film, as shown in Fig. 4, that also increases

124

the device’s transconductance G

m

(inset of Fig. 4). However,

125

more highly compressive CESL has also induced oxide defect

126

in pMOSFET. These induced defects will cause slightly higher

127

device’s subthreshold swing and GIDL (Fig. 5) and larger

128

strain-induced gate leakage, as shown in Fig. 5. In order to in-

129

spect the oxide defect induced by these CESLs, a low-frequency

130

noise spectrum analysis was employed to understand the gate

131

oxide defect generation in Si/SiO

2

interface or border [22],

132

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YEH et al.: IMPACT OF STRAIN TECHNOLOGY ON FUSI GATE SOI CMOSFET 3

Fig. 5. Larger GIDL and subthreshold swing happened on SOI pMOSFET with more highly compressive CESL layers. The inset shows similar tendency on gate leakage.

Fig. 6. With low-frequency noise inspection, higher CESL-induced oxide defect and Dithappened on nMOSFET with higher tensile CESL.

Fig. 7. With low-frequency noise inspection, higher oxide defect and Dit

happened on pMOSFET with more highly compressive CESL.

[23]. Thus, these oxide defects, which will degrade the device’s

133

electrical characteristics including subthreshold swing and gate

134

leakage, can be verified using a low-frequency noise analysis.

135

Apparently, higher noise caused by oxide defects was found

136

particularly in high-tensile CESL nMOSFET and compressive

137

Fig. 8. With charge pumping analysis, higher ICP and Nit happened on

higher CESL strain devices, particularly for compressive pMOSFET.

Fig. 9. For 90-nm SOI nMOSFET, larger HC-induced IDdegradation

hap-pened on device with higher tensile CESL.

Fig. 10. For 90-nm SOI nMOSFET, larger HC-induced Gm degradation

happened on device with higher tensile CESL.

CESL pMOSFET, as shown in Figs. 6 and 7, respectively. In ad-

138

dition, a charge pumping measurement was considered a useful

139

method to inspect defects at the interface of gate oxide and Si

140

substrate [24], [25] which can be used to confirm this CESL-

141

induced device degradation after voltage stressing. Compared

142

with a conventional device with low-strain CESL, higher N

it143

occurred in higher strain device particularly with higher tensile

144

CESL and compressive CESL, as shown in Fig. 8. Thus, higher

145

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Fig. 11. For 90-nm SOI nMOSFET, larger HC-induced subthreshold swing and GIDL happened on higher tensile CESL.

Fig. 12. For 90-nm SOI nMOSFET, larger HC-induced gate leakage hap-pened on device with higher tensile CESL.

Fig. 13. Larger NBI-induced IDdegradation happened on 90-nm pMOSFET

with more highly compressive CESL.

strain CESL will cause higher charge pumping current (I

cp

) in

146

the devices, as shown in Fig. 8. These CESL-induced defects

147

will also affect the reliability of MOSFET. Because of the

148

discrepancy of channel mobility between electrons and holes,

149

we found that, depending on the method of voltage stressing,

150

there is a different behavior in stressing-induced device

degra-151

dation between n/pMOSFETs. In this paper, HC, PBI, and NBI

152

Fig. 14. Larger NBI-induced Gm degradation happened on 90-nm

pMOSFET with more highly compressive CESL.

Fig. 15. Larger NBI-induced subthreshold swing and GIDL degradation happened on 90-nm pMOSFET with more highly compressive CESL.

Fig. 16. For 90-nm SOI pMOSFET, larger NBI-induced gate leakage hap-pened on device with higher tensile CESL.

stressing were used to inspect the voltage-stressing-induced

153

device degradation for nMOSFET and pMOSFET. Because of

154

higher strain-induced gate oxide defect, higher HC voltage-

155

stressing-induced I

D

degradation (ΔI

D

= 94 μA/μm) was

156

found in nMOSFET with high-tensile CESL in comparison

157

with the conventional device (ΔI

D

= 54 μA/μm) with lower

158

tensile CESL, as shown in Fig. 9. A voltage-stressing-induced

159

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TABLE I

SUMMARY FOR THEnMOSFETANDpMOSFET CHARACTERISTICSAFTERHC VOLTAGESTRESSING ANDPBI/NBI, RESPECTIVELY

tensile CESL, as shown in Fig. 10. Due to the strain-induced

161

oxide defect, HC voltage-stressing-induced subthreshold

162

characteristic degradation was found (ΔSS = 9 mV/dec) in

163

high-tensile CESL nMOSFET in comparison with the

conven-164

tional device (ΔSS = 6 mV/dec) with lower tensile CESL, as

165

shown in Fig. 11. Larger HC voltage-stressing-induced

sub-166

strate leakage degradation was also generated in nMOSFET

167

with higher tensile CESL, as shown in Fig. 12. For pMOSFET,

168

HC-induced device degradation is not apparently due to lower

169

impact rate by low channel hole mobility; thus, NBI is more

ef-170

fective to inspect voltage-stressing-induced pMOSFET

degra-171

dation. Fig. 13 shows that higher NBI-induced drain current

172

degradation (ΔI

D

= 24 μA/μm) was found for pMOSFET

173

with highly compressive CESL, in comparison with the

con-174

ventional device (ΔI

D

= 20 μA/μm) with lower strain CESL.

175

It is presumable that gate oxide interface in pMOSFET is

176

very sensitive to gate bias voltage stressing. Thus, the

ap-177

parent voltage-stressing G

m

degradation shown in Fig. 14

178

was also found in pMOSFET with more highly compressive

179

CESL. With these compressive CESL strain-induced oxide

180

defects, it is easy to cause a deterioration of device’s

sub-181

threshold characteristic particularly after NBI voltage

stress-182

ing. Thus, for pMOSFET with highly compressive CESL,

183

NBI-induced subthreshold characteristic degradation was found

184

(ΔSS = 24 mV/dec) in comparison with the conventional

de-185

vice ((ΔSS = 13 mV/dec) with lower strain CESL, as shown

186

in Fig. 15. There is no doubt that serious NBI

voltage-stressing-187

induced gate leakage was also found particularly in pMOSFET

188

with more highly compressive CESL, as shown in Fig. 16.

189

Table I summarizes the device degradation after HC, PBI,

190

and NBI voltage stressing for n/pMOSFETs. It is interesting

191

to note that nMOSFET reliability is sensitive to HC voltage

192

stressing, but pMOSFET’s reliability is sensitive to NBI

volt-193

age stressing. In this paper, higher voltage-stressing-induced

194

device degradation was found in nMOSFET with higher

ten-195

sile CESL particularly after HC voltage stressing. In addition,

196

higher voltage-stressing-induced device degradation was found

197

in pMOSFET with more highly compressive CESL particularly

198

after NBI voltage stressing. For scaled MOSFET with short gate

199

length and thin gate oxide thickness, we found that it is more

200

efficient for device reliability inspection particularly to use HC

201

voltage stressing for nMOSFET and NBI voltage stressing for

202

pMOSFET.

203

IV. CONCLUSION

204

In this paper, we found that high mechanical strain of CESL

205

can enhance carrier mobility, particularly tensile strain for

206

electron and compressive strain for hole. Thus, tensile CESL-

207

induced strain can improve the performance of nMOSFET, and

208

compressive strain is beneficial for pMOSFET. However, we

209

found that these high-strain CESL layers will also induce more

210

oxide and junction defects particularly on device channel re-

211

gion, causing the degradation of device performance including

212

subthreshold swing, GIDL, and gate leakage. We found that

213

there is a different behavior in voltage-stressing-induced device

214

degradation between n/pMOSFETs, depending on the method

215

of voltage stressing. As a result, voltage-stressing-induced de-

216

vice degradation occurred particularly in nMOSFET by HC

217

voltage stressing and pMOSFET by NBI voltage stressing.

218

ACKNOWLEDGMENT

219

The authors would like to thank the UMC staff for their

220

helpful comments.

221

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Wen-Kuan Yeh (M’00) was born in Hsinchu, 326

Taiwan, in 1964. He received the B.S. degree in 327 electronic engineering from Chung Yuan Christian 328 University, Chung-Li, Taiwan, in 1988, the M.S. 329 degree in electrical engineering from National 330 Cheng Kung University, Tainan, Taiwan, in 1990, 331 and the Ph.D. degree in electronics engineering from 332 National Chiao Tung University, Hsinchu, in 1996. 333 In 1996–2000, he was a Member of Research Staff 334 with the Technology and Process Development Divi- 335 sion, United Microelectronics Corporation, Hsinchu, 336 where he researched and developed logic, embedded DRAM, SOI, and 90-nm 337 transistor technology applications. He is currently an Associate Professor with 338 the Department of Electrical Engineering, National University of Kaohsiung, 339 Kaohsiung, Taiwan. His recent work is in the field of SOI and high-frequency 340

devices. 341

Jean-An Wang, photograph and biography not available at the time of 342

publication. 343

Ming-Hsing Tsai, photograph and biography not available at the time of 344

publication. 345

Chien-Ting Lin, photograph and biography not available at the time of 346

publication. 347

Po-Ying Chen was born in Taichung, Taiwan, in 348

1963. He received the B.S. degree in chemical 349 from SooChow University, Taipei, Taiwan, in 1985, 350 the M.S. degree in material science engineering 351 from National Sun-Yat-Sen University, Kaohsiung, 352 Taiwan, in 1989, and the Ph.D. degree in electri- 353 cal engineering from National Chia-Tung University, 354 Sinchu, Taiwan, in 1995. During his graduate stud- 355 ies, he worked on CVD diamond technology and its 356 applications, such as FED emission arrays, diamond- 357 like coating for electrooptical field application, and 358

MS junction for rectification diodes. 359

In 1995, he joined the Taiwan Semiconductor Manufacturing Corporation 360 (TSMC) Research and Development Center, Sinchu, where he was engaged in 361 the VLSI integration circuit project for 0.18-μm Cu interconnect technology. In 362 August 2005, he joined the faculty of the Department of Electrical Engineering, 363 Tung Fan Institute of Technology, as an Associate Professor, working on the 364 design and fabrication of ULSI ICs for wireless communication. In August 365 2007, he joined the faculty of the Department of Information Engineering, 366 I-Shou University, Kaohsiung, as an Associate Professor. He has significant 367 experience in the semiconductor industry from his practice in TSMC on not 368 only process integrity but also manufacturing quality system control. He is the 369 holder of several patents on ULSI advanced technology. His research interests 370 include advanced IC applications, such as nanotechnology. His current research 371 interests include communication technology, including RFID, antenna effect, 372 and microwave communication, and flat-plane-display technology, including 373 the clean process for LCD display planes, OLED process integrity, and field 374

emission display development. 375

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IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 9, NO. 1, MARCH 2009 1

The Impact of Strain Technology on

FUSI Gate SOI CMOSFET

1

2

Wen-Kuan Yeh, Member, IEEE, Jean-An Wang, Ming-Hsing Tsai, Chien-Ting Lin, and Po-Ying Chen

3

Abstract—In this paper, the impact of strain engineering on

4

device performance and reliability for fully silicide gate

silicon-5

on-insulator CMOSFET was investigated. With characterizing

6

device’s electrical property after hot carrier (HC) and positive/

7

negative bias instability voltage stressing, we found similar

en-8

hancement on device performance but different behavior on

9

voltage-stressing-induced device degradation for n/pMOSFETs.

10

Related noise analysis and charge pumping techniques were used

11

to investigate the strain-induced oxide defect which will accelerate

12

device degradation after long-time HC voltage stressing and/or

13

bias instability voltage stressing.

14

Index Terms—Fully silicide (FUSI), hot carrier (HC) and bias

15

instability, strain engineering, tensile-strain and

compressive-16

strain contact etch stop layer (CESL).

17

I. INTRODUCTION

18

A

S THE GATE length of CMOSFET scales is below

19

100-nm regime, increased channel doping is required to

20

suppress short-channel effects that will cause higher ionized

21

impurity scattering and further result in the degradation of

car-22

rier mobility [1]. Thus, a strained technology has been proposed

23

[2]–[7] in enhancing channel carrier mobility to improve device

24

performance particularly for deep-submicrometer MOSFET

25

design. However, extra process steps are always required for

26

these strain technologies; thus, for production issue, simpler

27

strained engineering such as high-strained contact etch stop

28

layer (CESL) that can generate higher strain to induce great

29

carrier mobility enhancement in the channel even at large

ver-30

tical electric fields was introduced. These strained technologies

31

provide extra gain on device characteristic, which have been

32

implemented extensively to improve device performances as

33

device size scaled to 90-nm node and beyond [8]. On the

34

other hand, the aggressive scaling of MOSFETs puts severe

35

constraints on the gate stack; thus, metal gate electrodes are

36

projected to replace poly-Si gate for future CMOS devices

37

in order to achieve equivalent oxide thickness

< 1 nm for

38

Manuscript received July 24, 2008; revised October 7, 2008. This work was supported by the National Science Council under Contract NSC 96-2221-E-390-028.

W.-K. Yeh and J.-A. Wang are with the Department of Electrical Engi-neering, National University of Kaohsiung, Kaohsiung 811, Taiwan (e-mail: wkyeh@nuk.edu.tw).

M.-H. Tsai is with the National University of Kaohsiung, Kaohsiung 811, Taiwan.

C.-T. Lin is with the Central R&D Division, United Microelectronics Corpo-ration, Kaohsiung 811, Taiwan.

P.-Y. Chen is with the Department of Information Engineering, I-Shou University, Kaohsiung 840, Taiwan.

Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TDMR.2008.2010622

Fig. 1. Schematic structure view of SOI MOSFET with Ni-FUSI gate.

semiconductor industry requirement [9]. Metal gates have many

39

advantages over poly-Si gates, such as no boron penetration,

40

no polydepletion effects, low resistance, and suppressed re-

41

mote charge scattering [10]. However, for the requirements

42

of circuit design with symmetrical threshold voltage, tunable

43

work function is necessary for nMOSFET (in the range of

44

4.1–4.4 eV) and pMOSFET (in the range of 4.8–5.1 eV). Sev-

45

eral approaches have been proposed, including midgap metal

46

gate [11], dual-metal CMOS integration [12]–[14], and fully

47

silicided (FUSI) metal gate [15]–[19]. FUSI metal gates have

48

some advantages over other metal gates, including tunable

49

work function and CMOS compatible processing. Recently,

50

NiSi FUSI gates have been demonstrated as appropriate gate

51

technologies for n/pMOSFETs [20], [21]. It is a very useful

52

method to improve device performance by combining CESL

53

with FUSI gate technology. However, integrating these strain

54

technologies to enhance device characteristics more efficiently

55

and related investigation of the impact of these strain technolo-

56

gies on reliability (including hot-carrier (HC) voltage stressing

57

and bias-instability inspection) have not been reported yet,

58

particularly for silicon-on-insulator (SOI) devices. It is believed

59

that SOI technology (including partially depleted (PD) SOI,

60

fully depleted SOI, and multigate) with strain engineering is

61

one of the most promising candidates for solving device per-

62

formance and power limitations. In this paper, we investigate

63

the impact of CESL technique on FUSI gate SOI CMOSFET

64

performance and voltage-stressing-induced (including HC and

65

bias instability) device degradation. Related noise analyses, as

66

well as charge pumping techniques, were employed on the

67

inspection of strain-induced defects.

68

II. EXPERIMENTAL

69

Fig. 1 shows the simplified process flow for preparing

70

the FUSI gate SOI MOSFET with high-strain CESL. PD

(8)

Fig. 2. LargerID happened on SOI nMOSFET with higher tensile CESL layers. The inset shows similar tendency onGmbehavior.

SOI CMOSFET samples with a 40-nm-thick Si active layer

72

and a 200-nm-thick buried oxide were fabricated on

oxygen-73

implanted (100) channel orientation SOI substrate. After

shal-74

low trench isolation, a 1.6-nm nitrided gate oxide was grown

75

using rapid thermal oxidation in a NO ambient. Then,

compos-76

ite oxide/SiN spacers and source/drain junctions were formed

77

using arsenic/boron ion implantations, respectively, followed

78

by a low-temperature annealing process. A 90-nm technology

79

was used as a vehicle to demonstrate device performances with

80

a 120-nm-thick poly-Si gate. Followed by polypatterning and

81

source–drain activation (1060-

◦

C spike anneal), a 50-nm-thick

82

Ni was deposited because of its lower thermal budget and

83

better property [8]. For fully Ni-FUSI gate electrode formation,

84

Ni-FUSI with a resistivity of 3.11

× e

−5

Ω · cm was formed

85

in a two-step process

(RTP

₁

340

◦

C/RTP

₂

520

◦

C

). Then, three

86

kinds of SiN film with different strains were deposited to

87

prevent exposing the gate electrode from backend process, and

88

also, low-tensile 38-nm CESL, high-tensile 70-nm CESL, and

89

highly compressive 70-nm CESL were deposited. The

low-90

tensile 38-nm CESL is a standard recipe for 90-nm CMOSFET

91

and is a reference sample compared to other two higher strain

92

SIN films in this paper. After wafer out of these devices, dc

93

measurements were carried out on an HP4156 under various

94

drain voltages

(|V

_D

| = 0−1.4 V) and gate voltages (|V

_G

| =

95

0 −1.4 V). An HP4145/HP35670A dynamic signal analyzer

96

and a BTA9812 noise analyzer were used to inspect the

low-97

frequency noise spectrum from 10 to 100 kHz. For reliability

98

check, HC voltage stressing, negative bias instability (NBI),

99

and positive bias instability (PBI) inspection were performed up

100

to

|V

_G

| = |V

_D

| = 1.2 V, V

_G

= 2.5 V, and V

_G

= −2.7 V with

101

100-min voltage stressing for n/pMOS, respectively.

102

III. RESULTS AND

DISCUSSION

103

Schematic view of a cross-sectional structure for FUSI gate

104

SOI MOSFET with various CESL processes was shown in

105

Fig. 1. For nMOSFET, channel electron mobility can be

in-106

duced from CESL and increased as the strain of these CESLs

107

was increased. Apparently, device driving capability was

en-108

hanced, particularly with higher tensile CESL for nMOSFET,

109

as shown in Fig. 2. Similar tendency was found in device’s

110

transconductance

(G

_m

) enhancement, as shown in Fig. 2.

111

Fig. 3. Larger GIDL and subthreshold swing happened on SOI nMOSFET with higher tensile CESL layers. The inset shows similar tendency on CESL-induced gate leakage.

Fig. 4. LargerI_Dhappened on SOI pMOSFET with more highly compres-sive CESL layers. The inset shows similar tendency on CESL-inducedGm

characteristic.

However, oxide defects, which are located at Si/SiO

2

interface

112

or bulk oxide (border), were also induced by these higher

113

tensile CESL films, and these defects will degrade the device’s

114

subthreshold swing and increase the gate-induced drain leakage

115

(GIDL) [20], as shown in Fig. 3. Because of these high-tensile

116

CESL-induced defects that are located around the interface of

117

gate oxide and Si substrate, it results in larger gate leakage in

118

nMOSFET, as shown in Fig. 3. For pMOSFET, compressive

119

CESL is useful to enhance the channel hole mobility for device

120

performance improvement. [21] Compared with conventional

121

pMOSFET with low-strain CESL, higher device driving capa-

122

bility can be found in pMOSFET, particularly with more highly

123

compressive CESL film, as shown in Fig. 4, that also increases

124

the device’s transconductance

G

_m

(inset of Fig. 4). However,

125

more highly compressive CESL has also induced oxide defect

126

in pMOSFET. These induced defects will cause slightly higher

127

device’s subthreshold swing and GIDL (Fig. 5) and larger

128

strain-induced gate leakage, as shown in Fig. 5. In order to in-

129

spect the oxide defect induced by these CESLs, a low-frequency

130

noise spectrum analysis was employed to understand the gate

131

oxide defect generation in Si/SiO

₂

interface or border [22],

132

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Fig. 5. Larger GIDL and subthreshold swing happened on SOI pMOSFET with more highly compressive CESL layers. The inset shows similar tendency on gate leakage.

Fig. 6. With low-frequency noise inspection, higher CESL-induced oxide defect andD_ithappened on nMOSFET with higher tensile CESL.

Fig. 7. With low-frequency noise inspection, higher oxide defect andDit

happened on pMOSFET with more highly compressive CESL.

[23]. Thus, these oxide defects, which will degrade the device’s

133

electrical characteristics including subthreshold swing and gate

134

leakage, can be verified using a low-frequency noise analysis.

135

Apparently, higher noise caused by oxide defects was found

136

particularly in high-tensile CESL nMOSFET and compressive

137

Fig. 8. With charge pumping analysis, higherI_CP andN_it happened on higher CESL strain devices, particularly for compressive pMOSFET.

Fig. 9. For 90-nm SOI nMOSFET, larger HC-inducedI_Ddegradation hap-pened on device with higher tensile CESL.

Fig. 10. For 90-nm SOI nMOSFET, larger HC-induced G_m degradation happened on device with higher tensile CESL.

CESL pMOSFET, as shown in Figs. 6 and 7, respectively. In ad-

138

dition, a charge pumping measurement was considered a useful

139

method to inspect defects at the interface of gate oxide and Si

140

substrate [24], [25] which can be used to confirm this CESL-

141

induced device degradation after voltage stressing. Compared

142

with a conventional device with low-strain CESL, higher

N

it143

occurred in higher strain device particularly with higher tensile

144

CESL and compressive CESL, as shown in Fig. 8. Thus, higher

145

(10)

Fig. 11. For 90-nm SOI nMOSFET, larger HC-induced subthreshold swing and GIDL happened on higher tensile CESL.

Fig. 12. For 90-nm SOI nMOSFET, larger HC-induced gate leakage hap-pened on device with higher tensile CESL.

Fig. 13. Larger NBI-inducedI_Ddegradation happened on 90-nm pMOSFET with more highly compressive CESL.

strain CESL will cause higher charge pumping current

(I

_cp

) in

146

the devices, as shown in Fig. 8. These CESL-induced defects

147

will also affect the reliability of MOSFET. Because of the

148

discrepancy of channel mobility between electrons and holes,

149

we found that, depending on the method of voltage stressing,

150

there is a different behavior in stressing-induced device

degra-151

dation between n/pMOSFETs. In this paper, HC, PBI, and NBI

152

Fig. 14. Larger NBI-induced Gm degradation happened on 90-nm pMOSFET with more highly compressive CESL.

Fig. 15. Larger NBI-induced subthreshold swing and GIDL degradation happened on 90-nm pMOSFET with more highly compressive CESL.

Fig. 16. For 90-nm SOI pMOSFET, larger NBI-induced gate leakage hap-pened on device with higher tensile CESL.

stressing were used to inspect the voltage-stressing-induced

153

device degradation for nMOSFET and pMOSFET. Because of

154

higher strain-induced gate oxide defect, higher HC voltage-

155

stressing-induced

I

D

degradation

(ΔI

D

= 94 µA/µm) was

156

found in nMOSFET with high-tensile CESL in comparison

157

with the conventional device

(ΔI

D

= 54 µA/µm) with lower

158

tensile CESL, as shown in Fig. 9. A voltage-stressing-induced

159

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TABLE I

SUMMARY FOR THEnMOSFETANDpMOSFET CHARACTERISTICSAFTERHC VOLTAGESTRESSING ANDPBI/NBI, RESPECTIVELY

tensile CESL, as shown in Fig. 10. Due to the strain-induced

161

oxide defect, HC voltage-stressing-induced subthreshold

162

characteristic degradation was found

(ΔSS = 9 mV/dec) in

163

high-tensile CESL nMOSFET in comparison with the

conven-164

tional device (ΔSS = 6 mV/dec) with lower tensile CESL, as

165

shown in Fig. 11. Larger HC voltage-stressing-induced

sub-166

strate leakage degradation was also generated in nMOSFET

167

with higher tensile CESL, as shown in Fig. 12. For pMOSFET,

168

HC-induced device degradation is not apparently due to lower

169

impact rate by low channel hole mobility; thus, NBI is more

ef-170

fective to inspect voltage-stressing-induced pMOSFET

degra-171

dation. Fig. 13 shows that higher NBI-induced drain current

172

degradation

(ΔI

_D

= 24 µA/µm) was found for pMOSFET

173

with highly compressive CESL, in comparison with the

con-174

ventional device

(ΔI

_D

= 20 µA/µm) with lower strain CESL.

175

It is presumable that gate oxide interface in pMOSFET is

176

very sensitive to gate bias voltage stressing. Thus, the

ap-177

parent voltage-stressing

G

_m

degradation shown in Fig. 14

178

was also found in pMOSFET with more highly compressive

179

CESL. With these compressive CESL strain-induced oxide

180

defects, it is easy to cause a deterioration of device’s

sub-181

threshold characteristic particularly after NBI voltage

stress-182

ing. Thus, for pMOSFET with highly compressive CESL,

183

NBI-induced subthreshold characteristic degradation was found

184

(ΔSS = 24 mV/dec) in comparison with the conventional

de-185

vice ((ΔSS = 13 mV/dec) with lower strain CESL, as shown

186

in Fig. 15. There is no doubt that serious NBI

voltage-stressing-187

induced gate leakage was also found particularly in pMOSFET

188

with more highly compressive CESL, as shown in Fig. 16.

189

Table I summarizes the device degradation after HC, PBI,

190

and NBI voltage stressing for n/pMOSFETs. It is interesting

191

to note that nMOSFET reliability is sensitive to HC voltage

192

stressing, but pMOSFET’s reliability is sensitive to NBI

volt-193

age stressing. In this paper, higher voltage-stressing-induced

194

device degradation was found in nMOSFET with higher

ten-195

sile CESL particularly after HC voltage stressing. In addition,

196

higher voltage-stressing-induced device degradation was found

197

in pMOSFET with more highly compressive CESL particularly

198

after NBI voltage stressing. For scaled MOSFET with short gate

199

length and thin gate oxide thickness, we found that it is more

200

efficient for device reliability inspection particularly to use HC

201

voltage stressing for nMOSFET and NBI voltage stressing for

202

pMOSFET.

203

IV. CONCLUSION

204

In this paper, we found that high mechanical strain of CESL

205

can enhance carrier mobility, particularly tensile strain for

206

electron and compressive strain for hole. Thus, tensile CESL-

207

induced strain can improve the performance of nMOSFET, and

208

compressive strain is beneficial for pMOSFET. However, we

209

found that these high-strain CESL layers will also induce more

210

oxide and junction defects particularly on device channel re-

211

gion, causing the degradation of device performance including

212

subthreshold swing, GIDL, and gate leakage. We found that

213

there is a different behavior in voltage-stressing-induced device

214

degradation between n/pMOSFETs, depending on the method

215

of voltage stressing. As a result, voltage-stressing-induced de-

216

vice degradation occurred particularly in nMOSFET by HC

217

voltage stressing and pMOSFET by NBI voltage stressing.

218

ACKNOWLEDGMENT

219

The authors would like to thank the UMC staff for their

220

helpful comments.

221

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222

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