IEEE ELECTRON DEVICE LETTERS, VOL. 32, NO. 8, AUGUST 2011 1095
Novel Dielectric-Engineered Trapping-Charge
Poly-Si-TFT Memory With a
TiN–Alumina–Nitride–Vacuum–Silicon Structure
Chun-Yu Wu, Yen-Ting Liu, Ta-Chuan Liao, Ming H. Yu, and Huang-Chung Cheng, Member, IEEE
Abstract—High-performance poly-Si-TFT-based TiN–alumina– nitride–vacuum–silicon (TANVAS) trapping-charge memory has been demonstrated utilizing high-k blocking oxide and vacuum tunneling layer for the first time. In particular, the vacuum, lowest k in nature, was introduced to replace the traditional tunnel-ing oxide. Furthermore, the alumina high-k blocktunnel-ing oxide was applied to upgrade the electric field across the tunneling layer. Based on the enlarged k-value difference between the blocking and tunneling layers, the TANVAS featured considerable field enhancement across the tunneling layer, thus much improving the program/erase efficiencies. In addition, owing to the suppression of defect creation in the tunneling layer, the TANVAS also exhibited superior retention characteristics. These excellent memory char-acteristics of TANVAS are therefore promising for the 3-D Flash and system-on-panel applications.
Index Terms—Field-enhanced nanowire (FEN), high-k, poly-Si, system-on-panel (SOP), thin-film transistors (TFTs), trapping-charge memory.
I. INTRODUCTION
T
HE silicon–oxide–nitride–oxide–silicon (SONOS)-type nonvolatile memory devices based on the poly-Si thin-film transistor (TFT) techniques have been extensively investigated for the realization of 3-D integrated circuits and system-on-panel (SOP) [1], [2]. In order to improve their inherent insuf-ficient program/erase (P/E) speed, lots of device architectures were proposed to enhance the electric field across the tunneling layer via the sharp corner features [3], [4]. However, most of them were still required larger operation voltage to achieve a reasonable memory window, which seriously restricted TFT SONOS applications.Recently, the adoption of high-k material as top blocking layer has been a practical scheme to reveal the low P/E voltage for single-crystalline-Si SONOS memory [5]. With raising the
k-value difference between blocking and tunneling layers, the
Manuscript received December 20, 2010; revised May 14, 2011; accepted May 21, 2011. Date of publication July 7, 2011; date of current version July 27, 2011. This work was supported by the National Science Council of the Republic of China under Grant NSC 99-2221-E-009-168. The review of this letter was arranged by Editor K. De Meyer.
The authors are with the Department of Electronics Engineering and the Institute of Electronics, National Chiao Tung University, Hsinchu 300, Taiwan (e-mail: [email protected]; [email protected]; tcliao. [email protected]; [email protected]; [email protected]).
Color versions of one or more of the figures in this letter are available online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/LED.2011.2158053
Fig. 1. Schematic diagrams of the key fabrication process steps of the proposed TANVAS. (a) FEN structure was formed after the removal of 100-nm-thick TEOS oxide strips by using diluted HF. (b) Cross-sectional schematic figure of fabricated TANVAS device with substituted vacuum tunneling layer [shown along the BBdirection of (a)].
electric field across the tunneling oxide could be promoted more effectively [6], [7]. Nevertheless, rare research works demonstrated such dielectric engineering on poly-Si-TFT mem-ories. In this letter, we proposed a novel poly-Si-TFT-based TiN–alumina–nitride–vacuum–silicon (TANVAS) memory de-vice with field-enhanced nanowire (FEN). In addition to the high-k blocking oxide, the lowest k vacuum in nature was intro-duced to replace traditional tunneling oxide to further enhance the k-value difference between the tunneling and blocking layers. Furthermore, due to being immune against the defect creation in the tunneling layer, TANVAS exhibited much-improved retention characteristics as well. As a result, both the P/E speed and retention reliability could be significantly improved by means of TANVAS device structure.
II. DEVICEFABRICATION
Based on our previous works, the fabrication process of poly-Si-TFT TANVAS memory device with FEN structure was schematically shown in Fig. 1 [8]–[10]. A 1.0-μm-thick thermal SiO2was first grown on a single-crystal silicon wafer as starting
substrate. Next, an etch-stop layer of Si3N4(50 nm thick) and a
sacrificial layer of TEOS SiO2(100 nm thick) were sequentially
deposited through the low-pressure chemical vapor deposition (LPCVD) system. The sacrificial SiO2 layer was then etched
as several dummy strips by reactive ion etch (RIE) process, followed by a layer of 100-nm-thick amorphous silicon film deposited at a temperature of 550 ◦C. After the source/drain (S/D)-pad lithography and its RIE process, pairs of a-Si side-wall spacers were in situ resided against the sideside-walls of SiO2
dummy strips and naturally connected to the S/D pads. The a-Si film was then transferred into the poly-Si by solid phase
1096 IEEE ELECTRON DEVICE LETTERS, VOL. 32, NO. 8, AUGUST 2011
Fig. 2. SEM image of poly-Si-TFT TANVAS memory device after the re-moval of tunneling oxide. The inset plot shows the XTEM image of fabricated TANVAS device with substituted vacuum tunneling layer along the BB direction.
crystallization at 600◦C for 24 h in N2ambient. Next, the FEN
structure was formed after etching the 100-nm-thick TEOS SiO2 strips by using diluted HF, as shown in Fig. 1(a).
After-ward, a 3-nm-thick TEOS SiO2film and an 11-nm-thick Si3N4
film were deposited sequentially by LPCVD as the tunnel-ing and charge-trapptunnel-ing layers, respectively. Then, an 11-nm-thick Al2O3 film was deposited by metal–organic chemical
vapor deposition system at 500◦C as the blocking layer. Be-hind the deposition of stacked gate dielectrics, a 300-nm-thick TiN metal gate was deposited by physical vapor deposition. Following the gate patterning, it should be noted that only the TiN gate, Al2O3 blocking layer, and Si3N4 trapping layer
were etched by RIE, while the 3-nm-thick TEOS SiO2 film
still remained on the poly-Si nanowires. After the phosphorous ion implantation (at 40 keV to a dose of 5× 1015 cm−2) and the S/D activation, a 300-nm-thick Si3N4layer was deposited
and then etched back by RIE to form Si3N4 spacers. Because
the Si3N4 spacers wrapped around the Al2O3 blocking layer,
they were capable of preventing the Al2O3 from damage by
the following wet etching. Next, the tunneling oxide was side etched off with diluted buffered oxide etch (BOE), and then, 400-nm-thick passivation oxide was deposited by SiH4-based
PECVD system to form a vacuum tunneling layer. The cross-sectional schematic figure of TANVAS device with substituted vacuum tunneling layer is shown in Fig. 1(b). Fig. 2 shows the scanning electron microscopy (SEM) image of poly-Si-TFT TANVAS memory device after the removal of tunneling oxide. The TANVAS with sawtooth-patterned gate was particularly designed to ensure that the gate would not collapse as the TEOS tunneling oxide was etched. By controlling the BOE immersion time, only the tunneling oxide above the nanowire channel region was side etched off, while most tunneling oxide below the broader area of the pattern gate could be remained to support the gate without collapsing. Finally, the contact hole opening and metallization completed the device fabrication.
For comparison, the TiN–alumina–nitride–oxide–silicon (TANOS) FEN devices with traditional oxide tunneling layer were also manufactured by the same process flow. The inset plot of Fig. 2 shows the cross-sectional transmission electron mi-croscopy (XTEM) image of fabricated TANVAS device along the BB direction. The FEN structure with vacuum tunneling layer could be obviously seen after the removal of tunneling oxide and SiH4-based passivation oxide deposition.
Fig. 3. (a) Threshold voltage (Vth) shift comparison of TANVAS and TANOS devices at a program bias (P ) from 11 to 13 V. (b) Vth shift comparison of TANVAS and TANOS devices at an erase bias (E) from−11 to −13 V. (c) Endurance and (d) 85◦C retention characteristics of TANVAS and TANOS devices.
III. RESULTS ANDDISCUSSION
The memory devices with a channel length (L) of 1 μm and a channel width (W ) of 2 μm were employed in this work. The subthreshold swing (SS) extracted from IDS–VGScurves were
243 and 249 mV/dec for the TANVAS and TANOS devices, respectively. It is well known that the SS is a parameter to monitor the device interface characteristics between channel and gate dielectric. Thus, the introduction of vacuum tunneling layer would not strongly degrade the Si/vacuum interface. The P/E efficiencies for both TANVAS and TANOS memory devices were characterized by means of the Fowler–Nordheim tunneling mechanism. Fig. 3(a) shows the threshold voltage (Vth) shift comparison of TANVAS and TANOS devices with
various program times at an applied gate voltage of 11–13 V. The TANVAS exhibited a greater Vthshift of 3.78 V in 10 ms
at a gate voltage of 13 V as compared to 2.62 V for the TANOS one. Likewise, Fig. 3(b) shows the similar trend that the TANVAS device had a faster erase speed than the TANOS counterparts. This indicated that the P/E efficiencies could be markedly upgraded by the introduction of vacuum tunneling layer. Since the vacuum was a lowest k value material in nature, the use of a low-k tunneling layer and high-k blocking oxide will simultaneously result in an increased electric field across
WU et al.: DIELECTRIC-ENGINEERED TRAPPING-CHARGE POLY-Si-TFT MEMORY WITH A TANVAS STRUCTURE 1097
Fig. 4. Simulation results of electric-field distribution along the sharp corner for both TANVAS and TANOS across the stacked gate dielectrics.
the tunneling layer and an inhibitive feature at the blocking oxide. Therefore, more carriers could be injected from the poly-Si channel into the nitride layer for such field-enhancement scheme. The TANVAS memory structure enhanced the k-value difference between the blocking/tunneling layers, leading to an effective improvement of P/E speed. The endurance character-istics of TANVAS and TANOS devices are shown in Fig. 3(c). The good endurance performance of TANVAS was mainly contributed to the prevention of defect generation within the tunneling dielectric. Fig. 3(d) shows the data retention of both devices at 85 ◦C. The memory window of the TANVAS was about 1.2 V after extrapolating to retention time of ten years, whereas the TANOS one was only 0.65 V. This degradation could be ascribed to the defect creation in the relatively poor quality of low-temperature-deposited tunneling TEOS oxide. Defects in the tunneling oxide would create the leakage path so that the stored charges in the nitride could flow across the tunneling layer simply. In contrast, due to the empty property of vacuum tunneling layer, TANVAS could immunize against the defect creation and thereby well kept the data storage. Fig. 4 shows the simulated electric-field distribution along the sharp corner for both TANVAS and TANOS devices. The tunneling layer materials put a great influence on the electric-field distribution across the stacked gate dielectrics. As expected, the local electric field of tunneling layer could be further promoted via TANVAS structure at the same gate bias of 12 V. It was noticed that the maximum electric field was increased from 3.94× 107to 6.58× 107V/cm as the k-ratio of blocking/tunneling layers was increased from 2.3 (TANOS) to 9 (TANVAS). Consequently, the TANVAS device could acquire a better charge-trapping efficiency in the nitride layer, which is consistent with the experimental results.
IV. CONCLUSION
In this letter, a novel trapping-charge poly-Si-TFT memory with TANVAS FEN device structure has been proposed for the first time. By replacing the low-temperature tunneling oxide as the vacuum, the TANVAS devices exhibited a larger Vth
shift of 3.78 V in 10 ms as compared to 2.62 V for the corresponding TANOS ones at an applied gate voltage of 13 V. These remarkable improvements could be attributed to the local electric-field enhancement of tunneling layer as raising the k-value ratio of the blocking/tunneling layers. Moreover, the better retention reliability for the TANVAS was ascribed to the empty feature of vacuum tunneling layer. Therefore, such a TANVAS memory is very promising for the 3-D Flash memory and SOP applications.
REFERENCES
[1] P. Xuan, M. She, B. Harteneck, A. Liddle, J. Bokor, and T.-J. King, “FinFET SONOS Flash memory for embedded applications,” in IEDM
Tech. Dig., 2003, pp. 609–612.
[2] A. J. Walker, S. Nallamothu, E.-H. Chen, M. Mahajani, S. B. Hemer, M. Clark, J. M. Cleeves, S. V. Dunton, V. L. Eckert, J. Gu, S. Hu, J. Knall, M. Konevecki, C. Petti, S. Radigan, U. Raghuram, J. Vienna, and M. A. Vyvoda, “3D TFT-SONOS memory cell for ultra-high density file storage applications,” in VLSI Symp. Tech. Dig., 2003, pp. 29–30.
[3] S.-C. Chen, T.-C. Chang, P.-T. Liu, Y.-C. Wu, P.-H. Yeh, C.-F. Weng, S. M. Sze, C.-Y. Chang, and C.-H. Lien, “Nonvolatile polycrystalline silicon thin-film-transistor memory with oxide/nitride/oxide stack gate dielectrics and nanowire channels,” Appl. Phys. Lett., vol. 90, no. 12, pp. 122 111-1–122 111-3, Mar. 2007.
[4] S.-I. Hsieh, H.-T. Chen, Y.-C. Chen, C.-L. Chen, and Y.-C. King, “MONOS memory in sequential laterally solidified low-temperature poly-Si TFTs,” IEEE Electron Device Lett., vol. 27, no. 4, pp. 272–274, Apr. 2006.
[5] C. H. Lee, K. I. Choi, M. K. Cho, Y. H. Song, K. C. Park, and K. Kim, “A novel SONOS structure of SiO2/SiN/Al2O3with TaN metal gate for multi-giga bit Flash memories,” in IEDM Tech. Dig., 2003, pp. 613–616.
[6] C.-H. Lee, S.-H. Hur, Y.-C. Shin, J.-H. Choi, D.-G. Park, and K. Kim, “Charge-trapping device structure of SiO2/SiN/high-k dielectric Al2O3 for high-density Flash memory,” Appl. Phys. Lett., vol. 86, no. 15, pp. 152 908-1–152 908-3, Apr. 2005.
[7] Y. N. Tan, W. K. Chim, W. K. Choi, M. S. Joo, and B. J. Cho, “Hafnium aluminum oxide as charge storage and blocking-oxide layers in SONOS-type nonvolatile memory for high-speed operation,” IEEE Trans. Electron
Devices, vol. 53, no. 4, pp. 654–662, Apr. 2006.
[8] T.-C. Liao, S.-W. Tu, M. H. Yu, W.-K. Lin, C.-C. Liu, K.-J. Chang, Y.-H. Tai, and H.-C. Cheng, “Novel gate-all-around poly-Si TFTs with multiple nanowire channels,” IEEE Electron Device Lett., vol. 29, no. 8, pp. 889–891, Aug. 2008.
[9] T.-C. Liao, S.-K. Chen, M. H. Yu, C.-Y. Wu, T.-K. Kang, F.-T. Chien, Y.-T. Liu, C.-M. Lin, and H.-C. Cheng, “A novel LTPS-TFT-based charge-trapping memory device with field-enhanced nanowire structure,” in
IEDM Tech. Dig., 2009, pp. 207–210.
[10] C.-Y. Wu, T.-C. Liao, M. H. Yu, S.-K. Chen, C.-M. Tsai, and H.-C. Cheng, “Field enhancement of omega-shaped-gated poly-Si TFT SONOS memory fabricated by a simple sidewall spacer formation,”
