Abstract—A new on-chip transient detection circuit for
system-level electrostatic discharge (ESD) protection is proposed. The cir-cuit performance to detect different positive and negative fast elec-trical transients has been investigated by the HSPICE simulator and verified in a silicon chip. The experimental results in a 0.13-µm CMOS integrated circuit (IC) have confirmed that the proposed on-chip transient detection circuit can be used to detect fast elec-trical transients during the system-level ESD events. The proposed transient detection circuit can be further combined with the power-on reset circuit to improve the immunity of the CMOS IC products against system-level ESD stress.
Index Terms—Electrical transient detection, electrostatic
dis-charge (ESD), system-level ESD test, transient noise.
I. INTRODUCTION
T
HE ELECTROSTATIC discharge (ESD) event has become an important reliability issue to integrated circuits (ICs). To meet the component-level ESD reliability, on-chip ESD pro-tection circuits have been added to the input/output (I/O) cells and power (VDDand VSS) cells of CMOS ICs [1], [2]. Besidesthe component-level ESD stress, system-level ESD is an in-creasingly significant reliability issue in CMOS IC products. This tendency results from the strict requirements of reliabil-ity test standards, such as the system-level ESD test for electro magnetic compatibility (EMC) regulation. In the system-level ESD test standard of IEC 61000-4-2 [3], the electrical/electronic product must sustain the ESD level of +8 kV (+15 kV) under contact discharge (air discharge) test mode to meet the immu-nity requirement of “level 4.” Such high-energy ESD-induced noises often cause damage or malfunction of CMOS ICs in-side the equipment under test (EUT). It has been reported that some CMOS ICs are very susceptible to system-level ESD
Manuscript received November 16, 2006; revised April 16, 2007, July 25, 2007, and September 14, 2007. This work was supported in part by the National Science Council, Taipei, Taiwan, R.O.C., under Contract NSC 96-2221-E-009-182, and in part by Himax Technologies Inc., Tainan, Taiwan, R.O.C.
M.-D. Ker and C.-C. Yen are with the Nanoelectronics and Gigascale Systems Laboratory, Department of Electronics Engineering and Institute of Electron-ics, National Chiao-Tung University, Hsinchu, Taiwan 300, R.O.C. (e-mail: [email protected]).
P.-C. Shih was with the Nanoelectronics and Gigascale Systems Laboratory, Department of Electronics Engineering and Institute of Electronics, National Chiao-Tung University, Hsinchu, Taiwan 300, R.O.C. He is now with Taiwan Semiconductor Manufacturing Corporation, Hsinchu 30077, Taiwan.
Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TEMC.2007.911911
Fig. 1. Measured VDDand VSSwaveforms of the microcontroller ICs inside
the keyboard with an ESD voltage of +1000 V zapping on the HCP under system-level ESD test.
stress [4]–[6], even though they have passed the component-level ESD specifications, such as a human body model (HBM) of±2 kV [7], machine model (MM) of ±200 V [8], and charged-device model (CDM) of±1 kV [9].
The inset in Fig. 1 shows an EUT (keyboard), which was stressed by an ESD gun with a charged voltage of +1000 V zapping on the horizontal coupling plane (HCP). During the system-level ESD test, the power and ground lines of the mi-crocontroller IC in the keyboard no longer maintain their nor-mal voltage levels, but an underdamped sinusoidal voltage with the amplitude of several hundred volts occurred, as shown in Fig. 1. This ESD-generated transient is quite large and fast, which can randomly couple to the power, ground, or I/O pins of the microelectronics system. Such a high-voltage-level fast transient causes the keyboard to be upset or frozen after the system-level ESD zapping [4]. Such fast transients also cause transient-induced latchup events in CMOS ICs [10].
To meet the system-level ESD specifications, two useful methods have been reported and investigated [11]–[13]. One effective method is to add some discrete noise-decoupling com-ponents or board-level noise filters into the CMOS IC products to decouple, bypass, or absorb the electrical transient voltage (energy) under system-level ESD test [11], [12]. Different types of noise filter networks can be used to improve the system-level
Fig. 2. Measurement setup for system-level ESD test with indirect contact-discharge test mode [3].
ESD immunity, including capacitor filter, ferrite bead, transient voltage suppressor (TVS), and several high-order noise filters such as LC-like (second-order) and π-section (third-order) fil-ters. It has been proved that the system-level ESD immunity of CMOS ICs under system-level ESD test can be greatly improved by choosing proper components in noise filter networks [13]. The other method to improve the system-level ESD immunity of CMOS ICs is to regularly check the system abnormal conditions by using an external hardware timer, such as a retriggerable monostable multivibrator [11]. The additional discrete noise-bypassing components substantially increase the total cost of a microelectronic product with CMOS ICs. Therefore, an on-chip solution integrated into the CMOS ICs, but without adding the additional discrete noise-decoupling components on the printed circuit board (PCB), is strongly requested by the IC industry.
In this paper, an on-chip transient detection circuit is proposed to detect the fast electrical transient under the system-level ESD test [14]. The new proposed transient detection circuit can be combined with the power-on reset circuit to provide a hard-ware/firmware codesign solution for system-level ESD stress. The circuit operation to detect different positive and negative fast electrical transients has been investigated by the HSPICE sim-ulation. The experimental results verified in a 0.13-µm CMOS IC have confirmed that the proposed on-chip transient detec-tion circuit can successfully detect the fast electrical transients during system-level ESD zapping.
II. SYSTEM-LEVELESD TEST
In the test standard of IEC 61000-4-2 [3], two test modes have been specified: air-discharge test mode and contact-discharge test mode. Fig. 2 shows the measurement setup of the system-level ESD test with indirect contact-discharge test mode. The system-level ESD measurement setup consists of a wooden table on the grounded reference plane (GRP). In addition, an isolation plane is used to separate the EUT from the horizontal coupling plane (HCP). The HCP are connected to the GRP with two 470-kΩ resistors in series.
Fig. 3. Proposed on-chip transient detection circuits realized with (a) NMOS-reset, and (b) PMOS-reset functions.
With the measurement setup in Fig. 2, the immunity of CMOS IC products against the system-level ESD stress can be evalu-ated. When the ESD gun zaps to the HCP, all CMOS ICs inside the EUT could be disturbed due to the high ESD-coupled en-ergy, as the waveforms show in Fig. 1. By using the digital oscilloscope, the transient responses on power lines of CMOS IC products can be recorded and further analyzed. Thus, the circuit performance of the proposed transient detection circuit can be evaluated through this measurement setup.
III. TRANSIENTDETECTIONCIRCUIT
A new on-chip transient detection circuit is proposed to detect the fast electrical transient under the system-level ESD zapping. By adding two coupling capacitors into a latch with two cas-caded CMOS inverters, the proposed transient detection circuit can be designed to memorize the occurrence of system-level ESD events.
A. Circuit Structure
The proposed transient detection circuits realized with NMOS-reset and PMOS-reset functions are shown in Fig. 3(a) and (b), respectively. The detection circuits, comprised of one latch and two coupling capacitors, are designed to memorize the
PMOS (Mp2) in the inverter2 (inv2) is designed with a larger
W/L ratio than that of the NMOS (Mn2). The sensitivity of
the transient detection circuit can be increased by adjusting the device W/L ratios in the latch.
In order to enhance the sensitivity of the detection circuit to the electrical transient, two coupling capacitors (Cp1 and Cp2)
are added between the input nodes (A, B) and the power lines (VDDand VSS). The capacitor Cp1 is placed between the VDD
and the input node of inv1 in order to sense the fast electrical transient from VDD. The capacitor Cp2is placed between the VSS
and the input node of inv2 in order to sense the fast electrical transient from VSS. The NMOS (Mnr) in Fig. 3(a) and the PMOS
(Mpr) in Fig. 3(b) are used to provide the initial reset function in
order to avoid the metastable operation of the latch circuit. With the reset signal of 3.3 V (0 V) applied to the gate of Mnr(Mpr),
the node A (B) of the detection circuit, shown in Fig. 3(a) and (b) can be initially set at 0 V (3.3 V). In normal circuit operations, the output nodes (VOUT1and VOUT2) of the proposed transient
detection circuits will be kept at logic 0. When a system-level ESD event occurs, the fast transient noises injecting into the power lines (VDD/VSS) will change the output state from logic
0 to logic 1. Therefore, the system-level ESD event can be detected by the proposed detection circuits. The sensitivity of the proposed transient detection circuit can be further enhanced by adjusting the device W/L ratios in the latch or changing the value of coupling capacitors (Cp1and Cp2).
B. Simulation
From the measured fast electrical transient waveforms, shown in Fig. 1, the underdamped sinusoidal waveforms on VDD/VSS
during the system-level ESD stress have been observed. Thus, a specific time-dependent voltage source given by
V (t) = V0+ Vasin(2πf (t− td)) exp(−(t − td)Da) (1)
is used to generate an underdamped sinusoidal voltage on the power lines of the proposed transient detection circuits in the simulation. With the proper parameters, such as the applied voltage amplitude Va, initial dc voltage Vo, damping factor Da,
damping frequency f , and time-delay td, the intended
under-damped sinusoidal voltage can be constructed for simulation. In the following HSPICE simulation with positive or nega-tive underdamped sinusoidal waveforms, the same parameters of Da = 2× 107s−1, f = 50 MHz, and td = 500 ns are used
(which is corresponding to the measured transient waveform in
Fig. 4. Simulated VD D, VS S, VOUT1, and VOUT2waveforms of the proposed
transient detection circuits under system-level ESD test with larger overshooting voltage coupled on (a) VD Dand (b) VS S.
Fig. 1), whereas the only difference is positive Va for
positive-going underdamped sinusoidal waveform and negative Va for
negative-going underdamped sinusoidal waveform. In addition,
Voof 3.3 and 0 V are used for fast electrical transient waveforms
on the VDDand VSS, respectively.
Under the positive system-level ESD zapping condition, the simulated VDD, VSS, VOUT1, and VOUT2 waveforms of the
pro-posed transient detection circuit with a positive-going under-damped sinusoidal voltage on VDDand VSSare shown in Fig. 4(a)
and (b). Due to different coupling paths or filter networks from the ESD source to the VDD and VSS pins of the chip, there
could be different ESD levels on VDDand VSS. Thus, two
differ-ent simulations are taken into consideration. The positive-going underdamped sinusoidal voltages with Vaof +20 V on VDDand
with Vaof +12 V on VSS are used to simulate the larger
over-shooting voltage coupled on VDD under the system-level ESD
test, as shown in Fig. 4(a). The positive-going underdamped sinusoidal voltages with Va of +12 V on VDD and with Va of
Fig. 5. Different coupling paths from ESD stress source to VDDand VSSpins
of the IC on the PCB.
+20 V on VSSare used to simulate the larger overshooting
volt-age coupled on VSS under the system-level ESD test, as shown
in Fig. 4(b). For both simulations, the VDD voltage is initially
kept at 3.3 V with a VSS of 0 V. During the fast transient of the
ESD stress, VDD begins to increase rapidly from 3.3 V. VOUT1
and VOUT2are disturbed simultaneously during the VDD/VSS
dis-turbance. At the same time, the transient detection circuit can detect the occurrence of the disturbance on VDD/VSS. As a
re-sult, when VDDfinally returns to its normal stable voltage level
of 3.3 V, VOUT1 and VOUT2 will be changed from 0 to 3.3 V
to memorize the occurrence of transient events, as shown in Fig. 4(a) and (b). The circuit operation can be analyzed from the voltage derivative on the coupling capacitors. Under the positive system-level ESD zapping condition, a current can be coupled through coupling capacitors, which can be expressed as
I1 = CP1
dV1
dt (2)
where V1 is the voltage across the coupling capacitor Cp1 and
I1 is the induced coupling current through Cp1. The voltage
derivative between VDD and VSS can introduce the coupling
current. The final logic state of the transient detection circuit will depend on the coupled voltage potential. The logic state of the transient detection circuit can be changed when the voltage potential on node A is charged up to the logic threshold voltage of inv1. The related equation can be expressed as
CP1
dV1
dt × R1 ≥ VT H 1 (3)
where R1 is the equivalent resistance on node A and VT H 1 is
the logic threshold voltage of inv1.
On the PCB design with CMOS IC products, the trace routing placements may be different for power (VDD) lines and ground
(VSS) lines. This will cause different coupling paths from the
ESD source to the VDD and VSS pins of the chip, as shown
in Fig. 5. The different coupling paths may result in different delays between the VDDand VSSwaveforms. Thus, the proposed
transient detection circuit should be evaluated in the circuit simulation under different delays in the transient waveforms
Fig. 6. Measured VDDand VSStransient responses with an ESD voltage of
+500 V zapping on the HCP under system-level ESD test. There is a delay of 5 ns between the VDDand VSSwaveforms in the first ringing period during the
fast transient stress.
Fig. 7. Simulated VDD, VSS, VOUT1, and VOUT2waveforms of the proposed
transient detection circuit under positive-going underdamped sinusoidal voltage on VDD/VSSpower lines with a 5-ns delay condition.
between VDDand VSS. The measured VDD and VSS waveforms
of the proposed transient detection circuit with an ESD voltage of +500 V zapping on the HCP under system-level ESD test are shown in Fig. 6. A delay of 5 ns between the VDDand VSS in
the first ringing period during the fast transient stress has been observed, as shown in Fig. 6.
The simulated VDD, VSS, VOUT1, and VOUT2 waveforms of
the proposed transient detection circuit with a delay of 5 ns between the VDDand VSS waveforms are shown in Fig. 7. The
positive Va on VDDand VSS waveforms is used to simulate the
positive ESD stress under the system-level ESD test, as shown in Fig. 6. During the period with a fast transient, VOUT1and VOUT2
are influenced by the VDD/VSS disturbance. Finally, VOUT1and
VOUT2are pulled up to the voltage level of 3.3 V. With a delay
between VDDand VSS, the proposed transient detection circuit
can still memorize the occurrence of the fast transient of the ESD stress.
the system-level ESD events. Therefore, the proposed tran-sient detection can memorize the occurrence of the system-level ESD and sense the fast electrical transient on the power lines (VDD/VSS).
C. Design Considerations
By using the HSPICE, the circuit operation of the proposed transient detection circuit to sense fast electrical transients can be analyzed in detail. The sensitivity of the transient detection circuit can be analyzed by changing the coupling capacitors or adjusting the device W/L ratios in the latch.
Table I shows the device dimensions and element values in the proposed transient detection circuit, as shown in Fig. 3(a). The purpose of adding the coupling capacitors (Cp1and Cp2) in the
proposed transient detection circuit is to enhance the sensitivity to fast electrical transients between power lines (VDD/VSS) and
latch logic gates (node A and node B). Under the delay of 5 ns between VDDand VSS, coupling capacitors ranging from 150 to
400 fF are used to investigate their sensitivity improvements on the transient detection circuit with device ratios listed in Table I. With higher coupling capacitors, the minimum positive ampli-tude to cause output (VOUT1and VOUT2) logic state transition of
transient detection circuits can be greatly reduced. For example, the minimum positive amplitude of the transient on VDDto cause
transition at the output (VOUT1/VOUT2) of the detection circuits
can be significantly reduced from +84 V (with a coupling capac-itor of 150 fF) to +2.1 V (with a coupling capaccapac-itor of 400 fF), as shown in Fig. 8(a). Thus, by choosing the coupling capacitors with a proper value, the sensitivity to fast electrical transients under system-level ESD test can be improved, regardless of the positive or negative transient levels.
By changing the device W/L ratios in the latch, the switching threshold voltage of the inverters (inv1 and in2) can be adjusted, and the driving capabilities of the PMOS and NMOS transistors can be modified. Under the delay of 5 ns between the VDDand
VSS, the device widths of Mn1ranging from 1.75 to 2.8 µm are
used to investigate the sensitivity improvement on the transient detection circuit with Cp1 = Cp2 = 200 fF and device ratios
listed in Table I. With a larger device W/L ratio of NMOS (Mn1)
in inverter1, the transient detection circuit can pull down the voltage at node B more efficiently. For example, the minimum positive amplitude of the transient on VDD to cause transition
at the output (VOUT1/VOUT2) of detection circuits can be
signifi-cantly reduced from +82 to +17 V by adding the device width of Mn1from 1.75 to 2.8 µm, as shown in Fig. 8(b). From these
Fig. 8. Minimum positive amplitude to change the output logic state of the transient detection circuit under (a) different coupling capacitors (CP 1and CP 2) with channel width of Mn 1= 2.5 µm, and (b) different
chan-nel widths of Mn 1with CP 1= CP 2= 200 fF. The channel length of Mn 1is
kept at 0.35 µm.
design considerations, the HSPICE simulation can be used to fine-tune the device sizes in the proposed transient detection circuits to detect different transient electrical levels.
From the measured fast electrical transient waveforms in Fig. 1, the underdamped sinusoidal waveforms on VDDand VSS
during the system-level ESD stress have been observed. The frequency of the underdamped sinusoidal waveforms on VDD
and VSS is about several tens of megahertz. The detection
fre-quency of the proposed transient detection circuit should cover such a range in order to detect fast electrical transients during the system-level ESD test. With a delay of 5 ns, the relationship between the damping frequency and minimum positive voltage to change the output logic state of the transient detection circuit is shown in Fig. 9. The relationship between the frequency factor and the underdamped sinusoidal waveforms has been analyzed in [15]. The frequency determines how fast the underdamped sinusoidal waveform will be attenuated within its first duration (cycle). The underdamped sinusoidal voltage waveform will be-come a unipolar overdamped voltage waveform if the damping
Fig. 9. Relationship between damping frequency and minimum positive volt-age to change the output logic state of the transient detection circuit.
frequency is too low [15]. From the simulated results in Fig. 9, the transient detection circuit can detect fast electrical transients with the frequency of several tens of megahertz, which will be typically generated during the system-level ESD test.
D. Discussion
In order to improve the system-level ESD immunity of CMOS ICs, the watchdog timer is often designed with a microelectronic system to regularly check the system abnormal conditions. A watchdog timer is a computer hardware timing device to reset the operation system if the main program is locked or frozen due to some fault conditions. The intention is to recover the system from the frozen state to normal operation. Under normal operation conditions, a watchdog timer maintains itself in the counting state. The firmware periodically sends a reset signal to the watchdog timer. The watchdog timer can be implemented with a counter working with a clock signal. Most watchdog timers are used in embedded systems, where this specialized timer is often a built-in unit of the microcontroller. If the main program is locked or frozen in an infinite state, the watchdog will not receive the reset signal. Then, the watchdog timer will send a signal into firmware to reset the main program. However, the logic states of a watchdog timer are stored in the registers or flip flops. It has been investigated that the logic states stored in the registers or flip flops can be destroyed or changed during system-level ESD tests to cause malfunction or frozen state on the main operation program [4].
The microcontroller with the watchdog timer can avoid the continued frozen state due to some fault conditions. How-ever, the circuit implementation of a watchdog timer is more complicated than the proposed transient detection circuit. The watchdog timer should be implemented with registers or flip flops to store logic states and combined with counter or other embedded systems to provide the reset function. Moreover, complicated circuit implementation will result in more current consumption.
Fig. 10. Measurement setup to verify the detection function of the transient detection circuit under system-level ESD test.
IV. EXPERIMENTALRESULTS
The proposed on-chip transient detection circuits in Fig. 3(a) and (b) had been fabricated in a 0.13-µm 1.2/3.3-V 1P8M CMOS process. The system-level ESD test with indirect contact-discharge test mode is used to verify the performance of the pro-posed transient detection circuit. Both positive and negative fast electrical transient waveforms are recorded by the oscilloscope to clearly indicate whether the detection circuit works correctly during the system-level test.
To verify the function of the transient detection circuit under the system-level ESD test, the measurement setup is shown in Fig. 10. The voltage waveforms on both the VDD and output
pins of the transient detection circuit are simultaneously moni-tored by a digital oscilloscope. The power supply provides the dc voltage and the regulator on the EUT provides the voltage of 3.3 V to the test chip. After the system-level ESD test with indi-rect contact-discharge mode, the output voltage of the transient detection circuit is observed to see whether it changed from 0 to 3.3 V.
The measured VDD, VOUT1, and VOUT2waveforms of the
pro-posed transient detection circuit under the system-level ESD test with an ESD voltage of +1500 V zapping on the HCP are shown in Fig. 11. VDDbegins to increase rapidly from the
nor-mal voltage (+3.3 V). Meanwhile, VOUT1and VOUT2show great
increase under such high-energy ESD stress. During the period with disturbance on VDD, VOUT1and VOUT2are disturbed
simul-taneously. Finally, the output voltage of the transient detection circuit has been changed from 0 to 3.3 V. The measured VDD,
VOUT1, and VOUT2transient waveforms of the proposed transient
detection circuits under the system-level ESD test with an ESD voltage of−1500 V zapping on the HCP are shown in Fig. 12. During VDDdisturbance, VOUT1and VOUT2are disturbed
simul-taneously. Obviously, VOUT1and VOUT2are finally pulled up to
the 3.3 V after the fast electrical transient. The experimental results are consistent with the HSPICE simulation results under positive and negative system-level ESD zapping conditions. The first nanoseconds of the data shown in Figs. 11 and 12 might be influenced by direct coupling into the probing system. However,
Fig. 11. Measured VDD, VOUT1, and VOUT2transient responses under
system-level ESD test with ESD voltage of +1500 V zapping on the HCP.
Fig. 12. Measured VDD, VOUT1, and VOUT2transient responses under
system-level ESD test with an ESD voltage of−1500 V zapping on the HCP.
the functionality of the detection circuit can be clearly seen from the change of the output level as a result of the ESD.
The circuit performance of the transient detection circuit un-der the system-level ESD test had been proven by both the experimental results and the HSPICE-simulated results. From the experimental results, the proposed transient detection circuit can indeed memorize the occurrence of the system-level ESD stress under both positive and negative fast electrical transient zapping conditions.
V. APPLICATIONS INCMOS ICs
The proposed transient detection circuit can be codesigned with firmware to provide a system solution to solve the system-level ESD issue of microelectronic products realized with CMOS ICs. It has been proven that the hardware/firmware can be codesigned and can be used effectively to improve the system-level ESD robustness of the CMOS IC products [4].
As shown in the flowchart in Fig. 13, the detection results (VOUT) from the on-chip transient detection circuits can be
tem-porarily stored as an ESD flag for firmware check. The states in the transient detection circuit and the ESD flag are initially cleared to logic 0 by the power-on reset. The reset procedure is executed through the normal firmware reset procedure when the ESD flag has a state of logic 0. When the fast electrical transient
Fig. 13. Firmware flowchart to reset or recover the system if the on-chip ESD transient detecting circuit detects the electrical transient during the system-level ESD stress.
happens, the on-chip transient detection circuit can detect the fast electrical transient to change the output states VOUTto logic
1. At the same time, the ESD flag is restored at logic 1, and the firmware executes the recover procedure to recover all system functions to a stable state as soon as possible. After the reset and recover procedures, the states in the transient detection circuit and the ESD flag are reset to logic 0 again for detecting the next ESD events.
To realize system-level ESD protection function, a hard-ware/firmware codesign solution combined with the transient detection circuit and the power-on reset circuit have been ana-lyzed. Under the normal power-on condition, the VDDpower-on
voltage waveform has a rise time of the order of milliseconds (ms). As there is no input signal except the VDDpower-on
volt-age waveform, the power-on reset circuit should be designed with the same internal delay as the order of milliseconds. Thus, the output signal of the power-on reset circuit can set the ESD flag to logic 0, as shown in Fig. 14(a). However, there are some mistriggered conditions in the power-on reset circuit. For exam-ple, the fast power-up time (in the range of microseconds) may create difficult situations for the power-on reset circuit to work properly. Therefore, a transient detection circuit is designed to sense fast electrical transients on power lines and combined with the power-on reset circuit so as to provide hardware/firmware codesign solutions for system-level ESD issues.
Due to the difference in the rise times between the ESD voltage and the VDD power-on voltage, the on-chip transient
detection circuit is designed to sense fast electrical transients and set the flag signal to logic 1, as shown in Fig. 14(b). Then, the firmware can execute the recover procedure to recover all the electrical functions to a stable state as soon as possible. After the reset and recover procedures, the ESD flag is reset to logic 0, again, for detecting the transient ESD events.
By including the on-chip transient detection circuit and an ad-ditional ESD flag into the chip, the firmware flowchart, shown in Fig. 13, can be used to improve the system-level ESD robust-ness of microelectronic products. Such an hardware/firmware codesign method can provide an effective system solution to solve the system-level ESD issues in a microelectronics system realized with CMOS ICs.
Fig. 14. Hardware/firmware operation during (a) power-on reset condition and (b) system-level ESD stress.
VI. CONCLUSION
A new transient detection circuit for system-level ESD pro-tection has been fabricated in a 0.13-µm CMOS process. By using one latch logic gate and two coupling capacitors, the on-chip transient detection circuit can be designed to detect the fast electrical transients during the system-level ESD zapping. The circuit performance under different positive and negative fast electrical transients had been also investigated by the HSPICE. The experimental results on silicon chip have confirmed that the proposed on-chip transient detection circuit can be used to detect fast electrical transients during system-level ESD zap-ping. The proposed transient detection circuit can be further combined with firmware design and power-on reset circuit to provide an effective solution to the system-level ESD issue in microelectronics systems realized with CMOS ICs.
ACKNOWLEDGMENT
The authors would like to thank Mr. C.-C. Tsai, Dr. T.-Y. Chen, and Mr. W.-Y. Lo of Himax Technologies Inc., Taiwan, for their valuable technical discussions.
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Ming-Dou Ker (S’92–M’94–SM’97–F’08) received
the B.S. degree from the Department of Electronics Engineering, the M.S., and Ph.D. degrees from the Institute of Electronics, National Chiao-Tung Uni-versity, Hsinchu, Taiwan, R.O.C., in 1986, 1988, and 1993, respectively.
In 1998, he was a Department Manager in the very large-scale integration (VLSI) Design Divi-sion, Computer and Communication Research Lab-oratories, Industrial Technology Research Institute, Hsinchu. Currently, he is a Full Professor in the Na-noelectronics and Gigascale Systems Laboratory, Department of Electronics En-gineering and Institute of Electronics, National Chiao-Tung University, where he also serves as the Director of the Master’s Degree Program in the College of Electrical Engineering and Computer Science. He is also an Associate Executive Director of the National Science and Technology Program on System-on-Chip, Taiwan. He has been invited to teach or consult reliability and quality design for integrated circuits by hundreds of design houses and semiconductor compa-nies in the worldwide integrated circuit industry. He is the author or coauthor of more than 300 papers published in international journals and conferences, especially in the field of reliability and quality design for circuits and systems in CMOS technology. He is the inventor of 128 U.S. patents and 136 R.O.C. (Taiwan) patents, especially in the field of reliability and quality of integrated circuits. His current research interests include the reliability and quality design for nanoelectronics and gigascale systems, the high-speed and mixed-voltage input–output interface circuits, and the on-glass circuits for system-on-panel applications in thin-film transistor liquid crystal displays.
Prof. Ker has served as a member of the Technical Program Committee and Session Chair of numerous international conferences. He organized the special session on Electrostatic Discharge (ESD) Protection Design for Nanoelectronics and Gigascale Systems in the IEEE International Symposium on Circuits and Systems (ISCAS) 2005. He conducted the tutorial course on ESD Protection Design for Nanoelectronics in CMOS Technology in the ISCAS 2006. He has been the President of the Foundation in the Taiwan ESD Association. He was a Distinguished Lecturer in the IEEE Circuits and Systems Society for the year 2006–2007. He also served as an Associate Editor of the IEEE TRANSACTIONS ONVLSI SYSTEMS. In 2003, he was selected as one of the Ten Outstanding Young Persons in Taiwan by the Junior Chamber International. He was the re-cipient of the National Invention Award in Taiwan in 2005 for one of his patents on ESD protection design. He has been praised by IEEE for contributions to electrostatic protection in integrated circuits, and performance optimization of VLSI micro-systems.
