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Investigation of an anomalous hump in gate current after negative-bias temperature-instability in HfO2/metal gate p-channel metal-oxide-semiconductor field-effect transistors

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Investigation of an anomalous hump in gate current after negative-bias

temperature-instability in HfO2/metal gate p-channel metal-oxide-semiconductor field-effect

transistors

Szu-Han Ho, Ting-Chang Chang, Chi-Wei Wu, Wen-Hung Lo, Ching-En Chen, Jyun-Yu Tsai, Guan-Ru Liu, Hua-Mao Chen, Ying-Shin Lu, Bin-Wei Wang, Tseung-Yuen Tseng, Osbert Cheng, Cheng-Tung Huang, and Simon M. Sze

Citation: Applied Physics Letters 102, 012103 (2013); doi: 10.1063/1.4773479

View online: http://dx.doi.org/10.1063/1.4773479

View Table of Contents: http://scitation.aip.org/content/aip/journal/apl/102/1?ver=pdfcov

Published by the AIP Publishing

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Investigation of an anomalous hump in gate current after negative-bias

temperature-instability in HfO

2

/metal gate p-channel

metal-oxide-semiconductor field-effect transistors

Szu-Han Ho,1Ting-Chang Chang,2,a)Chi-Wei Wu,1Wen-Hung Lo,2Ching-En Chen,1 Jyun-Yu Tsai,2Guan-Ru Liu,2Hua-Mao Chen,3Ying-Shin Lu,2Bin-Wei Wang,4 Tseung-Yuen Tseng,1Osbert Cheng,5Cheng-Tung Huang,5and Simon M. Sze1,2,6

1

Department of Electronics Engineering, National Chiao Tung University, Hsinchu 300, Taiwan

2

Department of Physics, National Sun Yat-Sen University, Kaohsiung 804, Taiwan

3

Department of Photonics & Institute of Electro-Optical Engineering, National Chiao Tung University, Hsinchu, Taiwan

4

Department of Electronics Engineering, Peking University, Beijing 100871, China

5

Device Department, United Microelectronics Corporation, Tainan Science Park, Taiwan

6

Department of Electronics Engineering, Stanford University, Stanford, California 94305, USA

(Received 9 November 2012; accepted 13 December 2012; published online 3 January 2013) This Letter investigates a hump in gate current after negative-bias temperature-instability (NBTI) in HfO2/metal gate p-channel metal-oxide-semiconductor field-effect transistors. Measuring gate

current at initial through body floating and source/drain floating shows that hole current flows from source/drain. The fitting of gate current (Ig)-gate voltage (Vg) characteristic curves demonstrates

that the Frenkel-Poole mechanism dominates the conduction. Next, by fitting the gate current after NBTI, in the order of Frenkel-Poole then tunneling, the Frenkel-Poole mechanism can be confirmed. These phenomena can be attributed to hole trapping in high-k bulk and the electric field formula Ehigh-kehigh-k¼ Q þ Esio2esio2.VC 2013 American Institute of Physics.

[http://dx.doi.org/10.1063/1.4773479]

With the scaling down of metal-oxide semiconductor field-effect transistors (MOSFETs), conventional SiO2

-based dielectric is only a few atomic layers thick, causing gate current to rise, power dissipation to increase, and per-formance to degrade. Besides, conventional SiO2-based

dielectrics have approached their physical limits. Hence, replacing SiO2-based dielectrics with high-k based

dielec-trics is a valid solution to these problems. In addition, high-k/metal gates can be integrated with techniques, such as silicon on insulator (SOI),1–3 strained-silicon,4,5 and multi-gate to improve device characteristics. As recom-mended in the International Technology Roadmap for Semi-conductors, Hf-based dielectrics have been heavily studied to replace SiO2-based dielectrics in recent years.

6–9

In reli-ability, negative-bias temperature-instability (NBTI) is still a significant concern for digital and analog circuits in cur-rent generation CMOS technology. In the past, NBTI degra-dation was dominated by an increase in the SiO2/Si

interface traps, which released hydrogen.10–12 However, bulk traps have dominated NBTI degradation in sub-1 nm-EOT devices in recent years due to hole trapping.13 In this paper, this phenomenon is also observed. Nevertheless, IgVg simultaneously generates an unusual hump with

NBTI. Thus, this study focuses mainly on an analysis of gate current for HfO2 dielectric p-MOSFETs undergoing

NBTI. The causes of the hump are explained in this Letter. The HfO2/metal gate p-MOSFETs used in this study

were fabricated through the gate-last process. First, high quality thermal oxide of 1 nm thickness was grown as an interfacial layer. Second, HfO2dielectrics were deposited in

that order by atomic layer deposition (ALD). Then, after annealing, HfO2 with thickness of 2 nm was formed. This

process may be crystallized into monoclinic crystal struc-ture.14,15 Finally, TixN1x was deposited by physical vapor

deposition (PVD) due to the ability of metal gates to elimi-nate gate depletion and resist remote phonon scattering.16,17 The p-MOSFETs were stressed in Vt¼ 1.8 V at 30C and

125C. IdVgtransfer curves were measured with Vdgiven

by 50 mV and Vggiven from 0 V to1.3 V during NBTI

at 30C and 125C. Then, IgVgtransfer curves were

meas-ured at 30C only with Vggiven from 0 V to 1 V before

and after NBTI (30C or 125C). Then, through the body floating (BF) and source/drain floating (SDF) process, the current path and carrier polarity can be confirmed. Next, the IgVgcurve is fitted by Frenkel-Poole mechanism and

tun-neling mechanism at 0 s and 1000s NBTI, respectively. All experimental curves were measured using an Agilent B1500 semiconductor parameter analyzer.

Figures1(a)and1(c)show the IdVgtransfer

character-istic curves with 50 mV drain voltage under NBTI for 1000s at 30C and 125C. Clearly, on-current are both degraded and Vt shifts 87 mV and 204 mV in the negative

direction at 1000s NBTI at 30C and 125C, respectively. Furthermore, subthreshold swing degradation is slight. Thus, Vt shift can be attributed mainly to hole trapping in the

high-k bulk. Figures 1(b) and 1(d) shows IgVg transfer

characteristic curves at 30C before and after NBTI at 30C and 125C, respectively. Obviously, the slight gate current hump appears after NBTI in 30C due to a smaller degrada-tion in Vt (87 mV), as shown in the inset of Fig. 1(b). Con-versely, the gate current hump is clearer after NBTI in 125C owing to a larger degradation in Vt (204 mV), as

a)

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shown in inset of Fig.1(d). Therefore, the clearer the hump generated, the more hole trapping, which occurs in high-k bulk.

To further understand the causes of the hump, fitting and distinguishing gate current are necessary. Figure2(a)shows IgVgcharacteristics with BF, SDF, and source/drain/body

all grounded (SDB). Obviously, the IgVgcharacteristic in

BF is similar to that in SDB, and the IgVgcharacteristic in

SDF is much smaller than those in either SDB or BF. These results indicate that holes transfer from source/drain to the gate, rather than electrons transferring from gate to body. Moreover, gate current is fitted under initial, shown in Fig.2(b), where it can be observed that gate current is con-firmed as Frenkel-Poole mechanism, from Vg¼ 0.98 to

Vg¼ 1.3. These results show that holes transfer from

source/drain to gate with the Frenkel-Poole mechanism at initial.

After confirming Frenkel-Poole mechanism at initial, the IgVgcharacteristic is fitted after 1000s NBTI at 125C,

as shown in Fig. 3(a). Clearly, section A indicates the Frenkel-Poole mechanism in Fig.3(b), from Vg¼ 0.50 to

Vg¼ 0.62, while section B is the tunneling mechanism in

Fig.3(c), from Vg¼ 0.68 to Vg¼ 0.78, and section C is

again Frenkel-Poole mechanism in Fig.3(d), from Vg¼ 1.2

to Vg¼ 1.3. In addition, in the Vg< Vt¼ 0.83 V

situa-tion, Frenkel-Poole mechanism transfers to tunneling mecha-nism with Vg increasing. On the contrary, tunneling

mechanism transfers to Frenkel-Poole mechanism when Vg> Vt. Frenkel-Poole current and tunneling current are a

series; whichever current is smaller dominates the current path. Therefore, Frenkel-Poole mechanism dominates cur-rent path because JFrenkel-Poole  JTunneling while tunneling

mechanism dominates current path when JFrenkel-Poole

 JTunneling. Therefore, the conditions under which a hump

is generated are JFrenkel-Poole JTunneling.

Figures 4(a) and 4(b) shows energy diagrams for Vg¼ 0 V without hole trapping and with hole trapping due to

NBTI, respectively. Note that Ehigh-kbecomes large, and ESiO2

reduces with hole trapping. An increase in Ehigh-kproduces a

larger Frenkel-Poole current, and a reduction in ESiO2

pro-duces a larger DEtrap, causing tunneling current to decrease.

DEtrapindicates the energy from the valance band in the

sur-face to trap level. Therefore, with hole trapping increasing, JFrenkel-Poole is larger than JTunneling. In addition, since the

hump generation condition is JFrenkel-Poole  JTunneling, hole

trapping leads to a more significant hump. In Figs. 1(b)and FIG. 1. (a) IdVgand (c) IdVgtransfer

characteristic curves with50 mV drain voltage as function of stress time under NBTI at 30C and 125C. (b) Ig–Vgand

(d) Ig–Vg transfer characteristic curves

at 30C before and after NBTI in 30C

and 125C.

FIG. 2. (a) Ig–Vgcharacteristic curves in

the SDB, BF, and SDF conditions. (b) Ig–Vg transfer characteristic curves of

high-k/metal gate MOSFETs under ini-tial and after NBTI at 125C. Inset

shows gate current is fitted by Frenkel-Poole mechanism at initial.

012103-2 Ho et al. Appl. Phys. Lett. 102, 012103 (2013)

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1(d), it can be observed that the more hole trapping that is captured in high-k bulk, the clearer the gate current hump we can observe. Figure 4(c) shows energy diagrams in the Vg< Vt situation with hole trapping. The electric field must

follow the formula Ehigh-kehigh-k¼ Q þ Esio2esio2¼ (Q/Esio2

þ esio2) Esio2¼ e0Esio2, where Q indicates the quantity of hole

trapping (Q > 0), Esio2 indicates an electric field in the SiO2,

and Ehigh-kis an electric field in the high-k bulk. The voltage

across gate oxide is small when Vg< Vt. Hence, Q/Esio2

can-not be ignored (Q Esio2). This result makes ehigh-k<e0and

Ehigh-k> Esio2. When Vgis swept from 0 V to Vton the device

with a large amount of hole trapping in high-k bulk, most of

the applied gate voltage occurs across in the HfO2layer. This

is the reason why JFrenkel-Pooleafter NBTI appears earlier than

JFrenkel-Poole under initial. Nevertheless, a relatively smaller

voltage occurs across in the SiO2layer, leading to a slight rise

in JTunnelingdue to a small variation in DEtrap. With an increase

in Vg, JFrenkel-Poole increases significantly while JTunneling

changes only slightly. This causes JFrenkel-Poole to change to

JTunneling. At the beginning stages, JFrenkel-Pooleappears in

sec-tion A (Fig.3(a)) owing to the supply of holes exceeding the demand (JTunneling JFrenkel-Poole). Next, JTunnelingappears in

section B (Fig. 3(a)) because the supply of holes is unable to meet the demand (JTunneling JFrenkel-Poole). Figure4(d)shows

energy diagrams in the Vg> Vtcondition with hole trapping.

The electric field should also obey the formula Ehigh-kehigh-k

¼ Q þ Esio2esio2¼ (Q/Esio2þ esio2) Esio2. On the contrary, Vg

applied to SiO2and HfO2in the Vg> Vt condition is large,

causing Q/Esio2to be ignored (Q Esio2). This result leads to

ehigh-k>esio2 and Ehigh-k< Esio2. Therefore, with Vg

increas-ing, DEtrap decreases, and JTunneling increases sharply due to

the exponential dependence on DEtrap. This is the reason why

JTunnelingchanges to JFrenkel-Poole. Finally, JFrenkel-Pooleappears

in section C (Fig.3(a)), since the supply of holes exceeds the demand (JTunneling JFrenkel-Poole).

In summary, the Vtshifts 204 mV and 87 mV in the

neg-ative direction, and a hump is generated in the IgVgtransfer

characteristic curves after NBTI in 30C and 125C, respec-tively. These are results of hole trapping in high-k bulk. Through fitting and distinguishing gate current under initial, holes are determined to transfer through the Frenkel-Poole mechanism from the source and drain. Gate current fitting af-ter NBTI at 125C indicates that JFrenkel-Poole changes to

JTunneling when Vg< Vt owing to the influence of Ehigh-k

> Esio2, while JTunnelingchanges to JFrenkel-Poolewhile Vg> Vt

due to the influence of E < E . These phenomena can FIG. 3. (a) Ig–Vg transfer characteristic

curves at initial and after NBTI in 125C. (b) Gate current in section A is fitted by Frenkel-Poole mechanism after NBTI at 125C. (c) Gate current in

sec-tion B is fitted by tunneling mechanism after NBTI at 125C. (d) Gate current in section C is fitted by Frenkel-Poole mechanism after NBTI at 125C.

FIG. 4. The energy band diagram of high-k/metal gate MOSFETs in the Vg¼ 0 V condition (a) without hole trapping before NBTI and (b) with hole

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Part of this work was performed at United Microelectronics Corporation. The work was supported by the National Science Council under Contract No. NSC 101-2120-M-110-002.

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數據

FIG. 2. (a) I g –V g characteristic curves in
FIG. 4. The energy band diagram of high-k/metal gate MOSFETs in the V g ¼ 0 V condition (a) without hole trapping before NBTI and (b) with hole

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