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The Impact of Uni-axial Strain on Low Frequency Noise in Nanoscale p-Channel
Metal–Oxide–Semiconductor Field Effect Transistors under Dynamic Body Biases
View the table of contents for this issue, or go to the journal homepage for more 2010 Jpn. J. Appl. Phys. 49 084201
(http://iopscience.iop.org/1347-4065/49/8R/084201)
The Impact of Uni-axial Strain on Low Frequency Noise in Nanoscale p-Channel
Metal–Oxide–Semiconductor Field Effect Transistors under Dynamic Body Biases
Kuo-Liang Yeh, Chih-You Ku, and Jyh-Chyurn GuoDepartment of Electronics Engineering and Institute of Electronics, National Chiao-Tung University, Hsinchu 300, Taiwan, R.O.C. Received February 8, 2010; accepted May 26, 2010; published online August 20, 2010
The impact of local strain on low frequency noise (LFN) in p-channel metal–oxide–semiconductor field effect transistor (pMOSFET) is investigated under dynamic body biases. For 60 nm pMOSFET, the uni-axial compressive strain from embedded SiGe (e-SiGe) in source/drain can contribute 75% effective mobility (eff) enhancement and the proportional improvement in current (IDS) as well as transconductance (Gm). However, the
strained pMOSFET suffer more than 80% higher LFN (SID=ID2) compared with the control pMOSFET free from strain engineering. The measured
LFN can be consistently explained by mobility fluctuation model and the increase of Hooge parameter (H) appears as a key factor responsible for
the higher LFN in strained pMOSFET. Forward body biases (FBB) is proposed as an effective method adapted to nanoscale devices for improving effand suppressing LFN, without resort to strain engineering. #2010 The Japan Society of Applied Physics
DOI: 10.1143/JJAP.49.084201
1. Introduction
Strain engineering has been introduced as an indispensable technology for increasing the mobility and driving current, especially useful for nanoscale devices.1–3) The fast gate speed driven by the mobility and current indeed contributes superior fT and fmax, the key performance parameters for RF/analog circuits.4,5) Since strain engineering has the potential impact on noise, particularly the low frequency noise (LFN) or flicker noise, it attracts increasing research effort in recent years. There exist a lot of controversies in the experimental results and proposed mechanisms on this topic.6–9)Maeda et al. reported flicker noise increases in p-channel metal–oxide–semiconductor field effect semicon-ductors (pMOSFET) under both compressive and tensile stress, namely bi-directional noise degradation.7) Stress induced excess traps and dipoles were assumed responsible for flicker noise degradation. Guisi et al. also concluded that SiGe recess source/drain (S/D) regions give rise to a significant enhancement of the trap density in the SiO2/ HfO2 gate stack.8)However, Ueno et al. claimed improved 1=f noise in pMOSFET with embedded-SiGe (e-SiGe) for local compressive stress,9)and controverted Maeda’s results as inclusive owing to side effects other than stress. In fact, there remain many open questions deserving an extensive investigation, e.g., the abnormally large LFN revealed in pMOSFET compared to nMOSFET with stress free liner and number fluctuation model assumed for pMOSFET.
Dynamic body biases method is proposed as an alternative solution aside from strain engineering, to achieving mobility and current enhancement. In fact, dynamic body biases have been extensively adopted in modern circuit design and proven as the most promising method to facilitate low power design in nanoscale complementary metal–oxide–semicon-ductor (CMOS) platform, known as dynamic threshold voltage CMOS (DTMOS).10,11)
In this paper, novel and interesting results of uni-axial compressive strain effect on LFN in pMOSFETs under dynamic body biases are presented. The pMOSFET adopting e-SiGe S/D for uni-axial compressive strain were fabricated for mobility enhancement. A comprehensive characteriza-tion was carried out to investigate the local strain effect on
mobility, current, short channel integrity, and most impor-tantly LFN. Dynamic body biases scheme consisting of forward body bias (FBB), zero body bias (ZBB), and reverse body bias (RBB) was employed to explore the influence on LFN. Mobility fluctuation model can explain the strain and dynamic body biases effect in nanoscale pMOS and Hooge parameter manifests itself a critical dependence on both effects.
2. Device Fabrication and Characterization
The strained pMOSFET with e-SiGe in S/D for uni-axial compressive strain were fabricated in 65 nm high perform-ance CMOS process and the standard pMOS free from strain engineering act as the control devices. Four-terminal device layout was implemented with four individual pads for four electrodes (G/D/S/B) to enable a freedom of body biases. The gate width (W) was fixed at 10 mm while the gate lengths drawn on layout (Ldrawn) varied in a wide range from 10 to 0.08 mm. An etching bias of 0.02 mm leads to physical gate length Lg¼Ldrawn0:02 mm, i.e., the minimal Lg down to 0.06 mm (60 nm). Interface trap density Nit was extracted by using the incremental frequency charge pump-ing (IFCP) method.12)
The power spectral density (PSD) of drain current noise, namely SID was measured by LFN measurement system, consisting of Agilent dynamic signal analyzer (DSA 35670) and low noise amplifier (LNA SR570). The LFN measure-ment generally covers a wide frequency range of 10 Hz to 100 kHz.
3. Local Strain Engineering Effect on pMOSFET Performance
3.1 Effective mobilityeff enhancement from uni-axial
strain
The uni-axial compressive strain can realize around 80% boost in linear IDS and maximum Gm for 60 nm pMOSFET due to the uni-axial compressive strain.3) Note that the gate overdrive VGT¼VGSVT was used to replace VGS as the expression in this work to eliminate the VT offset due to strain engineering. In this way, a fair comparison of electrical performance between the strained and control pMOSFET can be approached.
Figure 1 presents the effective mobility eff extracted from linear drain current–gate voltage (ID–VGS)
character-
E-mail address: jcguo@mail.nctu.edu.tw
istics. The dependence of effon gate length Lgfor strained and control pMOSFET is in an opposite direction. Strained pMOSFET gets higher eff for shorter Lg but the control one suffers a dramatic degradation in eff. As a result, the eff enhancement due to this local strain can attain 75% for 60 nm devices, which contributes near 80% increase of IDS and Gm in linear region.3) Furthermore, the eff enhancement in linear region contributes around 65% higher IDS and Gm in saturation region (not shown). The eff enhancement realized in strained pMOSFET with sufficient-ly short Lg manifests the local compressive strain effect from e-SiGe S/D. On the other hand, the dramatic eff degradation with Lg reduction revealed in control pMOS suggests an aggravated impurity scattering due to halo implantation located near the channel region in sufficiently short devices.
3.2 Interface traps and gate current: Uni-axial strain effect
Strain effect on interface traps is one of major concerns for the deployment of strain engineering in the state-of-the-art process. Figure 2 indicates the interface trap density Nit extracted by incremental frequency charge pumping (IFCP) method12) for control and strained devices with various Lg. It is found that the control pMOSFET revealed somewhat higher Nit. The difference of Nit between the control and strained pMOSFET, namely Nit(s,c) and
normalized to that of control pMOS, denoted as Nit(s,c)= Nit(c) is around 10 –20% over various Lg. However, the Nit(s,c)=Nit(c) decreases with decreasing channel length Lg. This result suggests that uni-axial compressive stress does not introduce additional interface traps. Meanwhile, the Nit in channel region increases with downscaling Lg for both control and strained pMOSFET. Gate edge damage or longitudinal shallow trench isolation (STI) stress along the direction of channel length are proposed as the potential mechanisms responsible for the increase of Nit in shorter devices.
The strain effect on gate leakage currents is one more critical concern for nanoscale devices under low power applications. The comparison between the strained and control pMOSFET, shown in Fig. 3 indicates that the uni-axial compressive strain can help reduce gate leakage current density Jg, attributed to larger out-of-plane effective mass.13)For L
gat 60 nm, the strained pMOSFET can achieve 15 – 20% lower Jg over VGT (0:4 to 1:8 V), shown in Fig. 3(b). The effective Jgreduction is a great benefit offered by the compressive strain to pMOS. Note that the Jg tends to increase with gate length scaling for both strained and control pMOS (not shown for brevity). The result suggests that the edge component of Jg is larger than that of area component and can be explained by the increasing impact from longitudinal STI stress or gate edge damage along the channel length. 0.1 1 10 35 40 45 50 55 60 65 70 75 80 W=10 μm, VBS=0 VGT= -0.4V, VDS= -50mV Gate length, Lg(μm) μeff ( cm 2 /V-s ) Control PMOS Strain PMOS
Fig. 1. (Color online) Effective mobilityeff extracted from linear I–V
characteristics for strained and control pMOSFETs over various gate lengths, Lg¼0:98 { 0:06mm. 0.1 1 0 5 10 15 20 Δ N it(s,c) / N it(c)
(
%)
Control Strain ΔNit(s,c) / Nit(c) N it(
10 10*
cm -2)
0 20 40 60 Gate length, Lg(μm)ΔNit(S,C)=Nit(control)-Nit(strain)
Fig. 2. (Color online) Interface trap density Nitvs Lg(0.07, 0.14, 0.48,
and 0.98mm), measured at VD¼VS¼VB¼0 V and VG¼Vamp¼1:4 V for
control and strained pMOSs.
0.0 0.5 1.0 1.5 5 10 15 20 25 (b) Δ J g /J g,strain (%) ΔJg=Jg,control- Jg,strain - V GT (V) 0.0 0.5 1.0 1.5 0.0 1.0 2.0 3.0 4.0 5.0 6.0 pMOS W10L006 Tox(inv)=23.35A (a) Strained Control J g ( nA/ μ m ) - V GT (V)
Fig. 3. (Color online) (a) Gate current density Jgvs VGT. (b) Gate current density difference:Jg(c,s)=Jg,svs VGT,Jg(c,s)¼Jg,cJg,s, measured at
VD¼VS¼VB¼0 V and varying VGT(VGT¼VGSVT) in 0:4 to 0:8 V, for control and strained pMOSFETs with Lg¼60 nm.
Jpn. J. Appl. Phys. 49 (2010) 084201 K.-L. Yeh et al.
3.3 Threshold voltage VT and body bias sensitivity
Figure 4(a) presents the threshold voltage VTversus Lgwith a dramatic difference between the strained and control pMOSFET, due to the uni-axial compressive strain. The control pMOSFET show an apparent reverse short channel effect (RSCE) but the strained pMOSFET reveal a VT roll-off for Lg scaling to 60 nm. Halo implantation introduced lateral non-uniform profile is the major cause responsible for RSCE. For strained pMOSFET, uni-axial strain induced bandgap narrowing (or valence band offset for holes) and S/D recess in e-SiGe are two potential reasons for the worse SCE and VTroll-off.14)Figure 4(b) indicates VT shift due to FBB (VBS¼ 0:6 V) and RBB (VBS¼0:6 V) and normal-ized to that under ZBB (VBS¼0), namely VTðVBSÞ= VTðVBS¼0 VÞ over various Lg. For pMOSFET, the FBB enables a positive VT shift toward lower jVTjwhereas RBB leads to a negative VTshift toward higher jVTj. Note that the strained pMOSFET have a smaller VT shift under both FBB and RBB, particularly for 60 nm device due to SCE featured by a remarkable VT roll off, shown in Fig. 4(a). This feature will influence dynamic body bias effect on effand LFN as discussed later. The degraded VT tunability and sensitivity under dynamic body biases emerges as a potential impact. 3.4 Local strain and body biases effect on effective
mobilityeff
For pMOSFETs, the Eeff can be calculated by eq. (1) in which VT dependence on body biases (VBS) makes a major contribution. Under the dynamic body biases, eff of both control and strained pMOSFET decreases with increasing Eeff and can be fitted by a simple model in eq. (2), in which keeps near 0.3 for various Lg (0.06 – 0.98 mm). The Eeff dependence of eff suggests phonon scattering as the dominant mechanism15)under an operation at room temper-ature, and the mechanism is applied to both strained and control pMOSFET: Eeff¼ VGTþ3VT 9TOX ; ð1Þ eff¼0 Eeff E0 : ð2Þ
Figure 5 presents the normalized eff shift [effðVBSÞ= effðVBS¼0Þ] under FBB and RBB, over various Lg. The FBB enables a positive eff shift whereas RBB leads to a negative eff shift. The magnitude of effðVBSÞ increases
with decreasing Lg no matter whether it is a positive or a negative shift. The strained pMOSFET indicate a smaller value in effðVBSÞ=effðVBS¼0Þ under both FBB and RBB, particularly for 60 nm device. It can be understood that the smaller body bias effect on VT in strained pMOSFET, shown in Fig. 4(a) leads to smaller Eeff variation and then the smaller effðVBSÞaccording to eqs. (1) and (2). 4. Local Strain Engineering Effect on LFN in
pMOSFETs
4.1 Uni-axial strain and dynamic body bias effect on SID=IDS2
The LFN measured from 60 nm pMOSFET and expressed in terms of SID=IDS2 under varying frequencies is shown in Fig. 6. Unfortunately, the strained pMOSFET suffers much higher SID=IDS2than control pMOSFET over a wide range of frequencies in 10 Hz–100 kHz. Therefore, the impact of uni-axial strain on LFN in nanoscale pMOSFETs appears as a critical concern, particularly for analog and RF circuit design. Figure 7(a) shows SID=IDS2 under a specified VGT¼ 0:4 V for strained and control pMOSFET with various Lg. For long channel devices, e.g., Lg¼0:98 mm, strained and control pMOSFET demonstrate similar LFN character-istics in SID=IDS2. However, for shorter Lg going down to 0.13 mm and below, the strained pMOSFET suffer obviously higher SID=IDS2. Figure 7(b) presents SID=IDS2 multiplied with device gate width and length (W Lg). Interestingly,
0.1 1 10 -0.28 -0.30 -0.32 -0.34 -0.36 -0.38 -0.40 Control Strained (a) W=10 μm VDS=- 50mV, VBS=0 Gate Length, Lg (μm) V T (V) 0.1 1 -50 -25 0 25 50 RBB: V BS= 0.6V Strained Control Control Strained (b) Δ V T ( V BS ) / |V T ( V BS =0 ) | (%) ΔVT(VBS)=VT(VBS)-VT(VBS=0) FBB: V BS= -0.6V Gate Length, Lg (μm)
Fig. 4. (Color online) (a) Linear VTmeasured at VDS¼ 50 mV, VBS¼0 for strained and control pMOSFET (b) VTshift due to VBS, normalized to
VTðVBS¼0Þ:VTðVBSÞ=VTðVBS¼0Þ,VTðVBSÞ ¼VTðVBSÞ VTðVBS¼0Þ measured under FBB (VBS¼ 0:6 V) and RBB (VBS¼0:6 V) for strained and
control pMOSFET with Lg¼0:06, 0.13, and 0.98mm.
0.1 1 -5 0 5 10 15 Δ μeff ( VBS ) / | μeff ( VBS =0 ) | (%) RBB FBB W=10 μm, VDS= -50mV
Δμeff(VBS)=μeff(VBS)-μeff(VBS=0)
Control V BS=0.6V Strain V BS=0.6V Control V BS= -0.6V Strain V BS= -0.6V Gate Length, L g (μm)
Fig. 5. (Color online) The eff shift due to VBS and normalized
to effðVBS¼0Þ: effðVBSÞ=effðVBS¼0Þ, effðVBSÞ ¼effðVBSÞ
effðVBS¼0Þ measured under FBB (VBS¼ 0:6 V) and RBB (VBS¼
0:6 V) for strained and control pMOSFETs with Lg¼0:06, 0.13, and
0.98mm.
opposite trends are demonstrated for the strained and control devices in SID=IDS2WLg against Lg scaling. The control pMOSFET indicate a decreasing function whereas the strained pMOSFET reveal an increasing trend versus Lg scaling. Therefore, Fig. 7(a) indicates a remarkably faster increase of SID=ID2 with Lg scaling for strained pMOSFET and more than 80% higher SID=ID2 in 60 nm devices compared with the long channel device (Lg¼0:98 mm). This result actually is in contradiction with what was published for nMOSFET and cannot be explained by the well-known number fluctuation model.16) Referring to Fig. 4(a), the dramatic RSCE revealed in control pMOSFET indicates a highly non-uniform channel doping profile due to halo implantation and potentially worse LFN based on the number fluctuation model.16)However, the experimental for pMOSFET exhibits an opposite trend that is the control pMOSFET with apparently worse RSCE have much lower LFN.
Regarding other potential reasons responsible for the worse LFN in strained pMOSFET, like stress induced excess traps or dipoles proposed by Maeda et al.,7)they cannot be justified due to a contraction with the measured gate leakage currents Jgin which the strain pMOSFET presents a lower Jg than control pMOSFET, shown in Fig. 3. In addition, a remarkably different trend in strain engineering effect on LFN in terms of ðSID(s,c)=ID2Þ=ðSID(c)=ID2Þ as shown in
Fig. 7 and interface traps density denoted as Nit(s,c)=Nit(c) shown in Fig. 2 under Lgscaling suggests that carrier number fluctuation is no longer an appropriate model to explain our observation. Note that SID(s,c)=ID2 means the difference between SID(s)=ID2 (strained) and SID(c)=ID2 (control). With the downscaling of Lg, the Nit(s,c)=Nit(c)decreases whereas ðSID(s,c)=ID2Þ=ðSID(c)=ID2Þincreases significantly. The meas-ured results are exactly in contradiction with the number fluctuation model, according to which the LFN (SID=ID2) is proportional to the interface trap density Nit.17)
The aforementioned arguments motivate our interest in exploring a truly appropriate model for an accurate prediction of LFN in pMOSFET. Figure 8 exhibits SID=IDS2versus IDS under various VGT, VBS, and Lgfor both strained and control pMOS. Herein, the SID=IDS2follows a function proportional to 1=IDSover the whole range of bias conditions. The results indicate that mobility fluctuation model derived according to Hooge empirical formulas, given by eq. (3) or (4) is the dominant mechanism governing pMOSFETs’ LFN:18)
SID IDS2 ¼1 f qVDS IDS Heff Leff2 ; ð3Þ SID IDS2 ¼q f 1 WLeffCox H VGT ; VGT¼ ðVGSVTÞ; ð4Þ where H is the Hooge parameter and Leff is the effective channel length. 101 102 103 104 105 10-14 10-13 10-12 10-11 10-10 10-9 Control Strained pMOS W10L006 VDS=-50 mV VGT=-0.4V, VBS=0 SID /IDS 2 (1/Hz) Frequency (Hz)
Fig. 6. (Color online) LFN measured for 60 nm pMOSFET under VGT¼
0:4 V and VBS¼0. The LFN is represented as SID=IDS2 for a fair
comparison between strained and control devices with different IDS.
SID=IDS2is the normalized PSD of drain current noise.
WL*S ID /IDS 2 (10 -10 /Hz* μ m 2 ) W=10 μm 1 W=10 μm VDS=-50mV, VBS=0 VGT = -0.4V S ID /I DS 2 (10 -11 * 1/HZ) 0.1 1 0.5 1.0 1.5 VDS=-50mV, VBS=0 (b) g (μm) 0.1 5 10 15 20 25 Strained (a) Gate length, L g (μm) Gate length, L Control Strained Control Eeff = 0.65MV/cm
Fig. 7. SID=IDS2measured under a specified Eeffof 0.65 MV/cm for strained and control pMOSFET with Lg¼0:06, 0.13, and 0.98mm: (a) SID=IDS2;
(b) SID=IDS2W Lg. 10-6 10-5 10-4 10-3 10-12 10-11 10-10 10-9 L=0.06,0.13μm L=0.98μm VDS= -50mV, VGT= -0.2~-0.6V VBS= -0.6 ~0.6V Strain pMOS L098 L013 L006 Control pMOS L098 L013 L006 S ID /I DS 2 (1/Hz)
Drain Current I DS (A) 1/IDS
Fig. 8. (Color online) SID=IDS2versus IDS, measured under varying VGT
(VGT¼ 0:2 to 0:6 V) and body biases (VBS¼ 0:6, 0, 0.6 V) for
strained and control pMOSFET with various Lg¼0:06, 0.13, and 0.98mm.
Jpn. J. Appl. Phys. 49 (2010) 084201 K.-L. Yeh et al.
Note that SID=IDS2 exhibits a dramatic increase with Lg scaling in both strained and control devices, and strained pMOSFET suffer much higher LFN in terms of SID=IDS2for aggressively scaled dimensions at 0.13 mm and 60 nm. The mobility fluctuation model with an expression of eq. (3) for varying IDS or eq. (4) for varying VGT can predict the dependence of the dramatic increase of SID=IDS2 on device parameters (W, Leff, Cox, eff, H, IDS, VGT) and more importantly help explore the origins responsible for the worse LFN in strained pMOSFET. The increase of effective mobility (eff) or Hooge parameter (H) and the decrease of effective channel length (Leff) will lead to higher LFN in terms of SID=IDS2 under the specified IDS. For the strained pMOSFET, the implantation profile difference reflected by Fig. 4 may also contribute to shorter effective channel length and lead to higher LFN. It explains why the strained pMOSFET with short Lg(0.13 and 0.06 mm) indeed gain the benefit of higher eff but suffer worse LFN, as shown in Figs. 7 and 8. According to eq. (4), the effective ways to suppressing LFN can be the increase of device dimensions (W, Leff), the increase of jVGTj, and the reduction of H. The local strain cooperating with body biases effect on the Hooge parameter Hemerges as an interesting topic.
As it is well known that dynamic body biases method has been proven in DTMOS platform for low power design, we propose that this method may become a potential solution for low noise design. Figure 9 presents the dynamic body biases effect on LFN in terms of SIDðVBSÞ=SIDðVBS¼ 0Þ where SIDðVBSÞ ¼SIDðVBSÞ SIDðVBS¼0Þ under FBB (VBS¼ 0:6 V) and RBB (VBS¼0:6 V). For both strained and control pMOSFETs, FBB can reduce SID[SIDðVBSÞ< 0] attributed to reduced normal effective field Eeff. On the other hand, RBB makes LFN worse with SIDðVBSÞ> 0. However, the dynamic body bias effect on LFN is degraded in strained pMOSFET with a smaller amount of SIDðVBSÞ= SIDðVBS¼0Þ, particularly worse for the shortest devices with Lg¼60 nm. The significant VT lowering and degraded body bias effect shown in Fig. 4 for strained pMOSFET explains the diminishing benefit from FBB on LFN.
Table I presents the strain effect on LFN and effin terms of normalized amount such as [SID(s,c)=ID2ðVBSÞ=½SID(c)=
ID2ðVBSÞ] and eff(s,c)ðVBSÞ=eff(c) at VGT¼ 0:4 V and under dynamic body biases (FBB, ZBB, RBB). Note that SID(s,c)=ID2ðVBSÞ is defined as SID(s)=ID2SID(c)=ID2 and eff(s,c)ðVBSÞ is equal to eff(s)eff(c) under a specified VBS. The results summarized in Table I reveal interesting effects from dynamic body biases. For FBB, the increase of LFN in strained pMOSFETs [SID(s)=ID2ðVBSÞ] compared to control pMOSFET [SID(c)=ID2ðVBSÞ] becomes larger whereas the effenhancement in strained pMOSFET over the control ones becomes smaller. As for RBB, an opposite trend was demonstrated for LFN and eff, i.e., the increase of LFN due to strain gets smaller but the eff enhancement over control ones becomes larger. It can be explained that the control pMOSFET benefit from FBB in the suppression of SID(c)= ID2ðVBSÞand enhancement of eff(c), attributed to lower Eeff from FBB. In this way, the control pMOSFET has much less LFN than strained pMOSFET and it is demonstrated with larger difference in SID=ID2ðVBSÞ given by SID(s,c)= ID2ðVBSÞ. Also, the larger FBB effect in control pMOSFET facilitates more Eeff reduction and eff enhancement, and then the smaller difference from that of strain pMOSFET denoted as eff(s,c)ðVBSÞ.
4.2 Strain and body biases effect on Hooge parameterH
Referring to Table I, mobility fluctuation model given by eq. (3) or (4) is the most relevant mechanism to explain the uni-axial compressive strain effect on LFN of pMOSFET, and Hooge parameter H appears as the most key factor determining LFN in terms of SID=ID2. Figure 10 makes a comparison of H between the strained and control pMOSFETs over various Lg, and exhibits a remarkable
0.1 1 -50 -25 0 25 50 75 FBB RBB W=10 μm,VGT= -0.4~-0.6V ΔSId(VBS)=SId(VBS)-SId(VBS=0) Δ SID ( VBS ) /S ID ( VBS =0 ) (%) Strained VBS=0.6V VBS=-0.6V Control VBS=0.6V VBS=-0.6V Gate length, Lg (μm)
Fig. 9. (Color online) Change of SIDunder FBB (VBS¼ 0:6 V) as well
as RBB (VBS¼0:6 V) and normalized to the reference SID at ZBB
(VBS¼0), denoted asSIDðVBSÞ=SIDðVBS¼0Þ measured for strained and
control pMOSFET with various Lg¼0:06, 0.13, and 0.98mm.
Table I. The strain effect on LFN and eff in terms of ½SID(s,c)=
ID2ðVBSÞ=½SID(c)=ID2ðVBSÞandeff(s,c)ðVBSÞ=eff(c)under dynamic body
biases ZBB (VBS¼0), FBB (VBS¼ 0:6 V), and RBB (VBS¼0:6 V), and
VGT¼ 0:4 V. Data were measured from control and strained pMOSFETs
with Lg¼0:06, 0.13, and 0.98mm.
Lg(mm)
½SID(s,c)=ID2ðVBSÞ=½SID(c)=ID2ðVBSÞ eff(s,c)ðVBSÞ=eff(c)
0.98 0.13 0.06 0.98 0.13 0.06 FBB (%) 1 156 209 5 37 64 ZBB (%) 0 55 128 7 44 75 RBB (%) 29 41 10 7 48 85 0.1 1 2.0x10-4 4.0x10-4 6.0x10-4 8.0x10-4 1.0x10-3 Strained Control W=10 μm VDS=-50mV VGT= -0.4V, VBS=0 Hooge Parameter, αH Gate length, Lg (μm)
Fig. 10. Hooge parameterHextracted from SID=IDS2measured under
VGT¼ 0:4 V and VBS¼0 for strained and control pMOSFET with various
Lg(0.98, 0.13, 0.06mm).
increase of H with Lg scaling in strained devices but a decrease in control devices. It suggests the local strain will increase H and makes LFN worse. The larger H in the strained pMOSFET, assuming negligible difference in Leff from e-SiGe suggests that mobility fluctuation becomes worse potentially from accelerated phonon scattering in the strained lattice.19)
Figure 11 indicates that Hand effof control pMOSFET are very sensitive to VBS but those of strained pMOSFET show a weak dependence. Note that FBB can effectively increase eff and reduce H for control pMOSFET and contribute much lower SID=ID2. The critical dependence of Hon eff shown in Fig. 12 can facilitate an understanding of the mechanism responsible for dynamic body biases effect on LFN. FBB can help increase eff under a specified VGT due to smaller normal field (Eeff) resulted from reduced body depletion charge. The increase of eff in this way can achieve lower Hand then realize lower LFN. On the other hand, the eff enhancement from the uni-axial strain is accompanied with larger H and leads to the penalty of worse LFN.
According to eq. (3), the effective ways to suppressing LFN (flicker noise) can be classified as the increase of device dimensions (W, Leff), the increase of VGT, and the reduction of H. Figure 13 illustrates H versus Eeff for strained and control pMOSFET (Lg¼60 nm) in which Eeff is varied by changing VGTfrom 0:2 to 0:5 V, under FBB,
ZBB, and RBB. For control pMOSFET, the H increases with Eeff under all biasing conditions. As for strained pMOSFET, the His higher than that of control pMOS and shows a weak dependence on Eeffunder various body biases (FBB, ZBB, and RBB). Note that the Hooge parameter H responsible for LFN is determined by mobility fluctuation instead of mobility itself. The statement can be understood by eqs. (5)–(8).20) The remarkable difference in the E
eff dependence of H between the strained and control pMOSFET suggests different mechanisms dominant in mobility fluctuation. For control pMOSFET, the strong Eeff dependence of H suggests that the mobility fluctuation is dominated by the component of surface roughness scatter-ing, i.e., the third term of eq. (8). It can be understood that the larger Eefftends to drive the inversion carriers closer to the gate oxide/channel interface and make surface rough-ness worse. This increase of surface roughrough-ness can enhance mobility fluctuation and reflect its effect on H.20)However, for strained pMOSFET, the weak Eeff dependence of H suggests that the mobility fluctuation is dominated by the component of phonon scattering, i.e., the first term of eq. (8). The mechanism proposed for control pMOSFET cannot be applied to strained pMOS:
1 eff ¼ 1 ph þ 1 i þ 1 sr ; ð5Þ 1 eff ¼ 1 ph þ 1 i þ 1 sr ; ð6Þ where 1 eff ¼ 1 2 eff eff; 1 ph þ 1 i þ 1 sr ¼ph 2 ph þi 2 i þsr 2 sr )eff 2 eff ¼ph 2 ph þi 2 i þsr 2 sr : ð7Þ According to the original definition, H, H,ph, H,i, and H,sr are proportional to eff, ph, i and eff, respec-tively, as H¼ eff ph 2 H,phþ eff i 2 H,iþ eff sr 2 H,sr: ð8Þ -0.6 0.0 0.6 10-5 10-4 10-3 50 100 150 200 Control Strain Strain Control Body Bias, V BS(V) Hooge Parameter, α H μeff ( cm 2 /V-s )
Fig. 11. (Color online) Hooge parameter H extracted from SID=IDS2
and Effective mobilityeffvs VBSextracted from I–V for 60 nm strained
and control pMOS, at VGT¼ 0:4 V, VBS¼ 0:6, 0, 0.6 V.
RBB : VBS=0.3, 0.6V FBB : V BS= -0.3,-0.6V H μeff(cm2/V-s) 20 40 60 80 100 10-5 10-4 10-3 V GT= -0.2~-0.6V Strain W10 L098 L013 L006 Control W10 L098 L013 L006 Hooge parameter, α
Fig. 12. (Color online) Hooge parameterHvseffunder FBB (VBS¼
0:3, 0:6 V) and RBB (VBS¼0:3, 0.6 V). FBB can increaseeff and
reduceH. 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 10-4 10-3 10-2 W=10μm L=0.06μm Control pMOS RBB ZBB FBB Strained pMOS RBB VBS=0.6V ZBB VBS=0V FBB VBS=-0.6V VDS= -50mV, VGT= -0.2~-0.5V, Hooge parameter, α H E eff (MV/cm)
Fig. 13. (Color online) TheHvs Eefffor strained and control devices
with Lg¼0:06mm, under dynamic body biases FBB (VBS¼ 0:6 V), ZBB,
and RBB (VBS¼0:6 V).
Jpn. J. Appl. Phys. 49 (2010) 084201 K.-L. Yeh et al.
The different body biases dependence of H between strained and control pMOSFET leads to apparently smaller H(S,C) (¼ H(Strain)H(Control)), when operating under ZBB and RBB. This interesting result is consistently reflected by the smaller SID(S,C)=ID2 under RBB shown in Table I. Considering that mobility fluctuation is the domi-nant mechanism responsible for LFN in pMOSFET, the body biases dependence of SID(S,C)=ID2 and H(S,C) can be explained as follows. For strained pMOSFET, the mobility fluctuation is dominated by accelerated phonon scattering, which is nearly independent of Eeff and leads to the weak body biases dependence of H. On the other hand, for the control pMOSFET, the mobility fluctuation is primarily governed by surface roughness scattering, which definitely increases with increasing Eeff and then results in significant body biases effect on H. The mentioned argu-ment can consistently explain the strain effect on LFN and its body bias dependence. The interesting observation suggests that the difference of interface property and scattering process near the channel surface can make the mobility fluctuation different between the strained and control pMOSFET.
5. Conclusions
The uni-axial compressive strain can realize multiple advantages in nanoscale pMOSFETs, such as 65 – 80% boost of eff, IDS, and Gm in linear and saturation regions and 15 – 20% lower Jg under strong inversion. The remarkable increase in Gm and IDS can boost gate speed and RF/analog circuit performance in terms of fT and fmax. However, this local strain leads to worse LFN with more than 80% higher SID=ID2 in 60 nm devices. The number fluctuation model widely used for nMOSFETs is no longer valid and cannot explain the local strain as well as scaling effects on LFN measured from pMOSFETs. Mobility fluctuation model can predict the novel LFN characteristics in the dependence on local strain, geometry scaling, and bias conditions. The increase of Hooge parameter H due to local strain is identified as the major factor responsible for worse LFN in strained pMOSFET. FBB can increase eff, reduce H, and improve LFN, all contributed from the reduced Eeff. Unfortunately, the dynamic body biases effect is degraded in strained pMOSFET in nanoscale and cannot make significant contribution in LFN. On the other hand, RBB degrades eff and makes LFN worse for both control and strained pMOSFET; however their difference in LFN performance becomes smaller, particularly under increasing Eeff, because the strained pMOSFET is less sensitive to body bias. The strain engineering for mobility enhancement is useful in high speed digital design but will introduce an adverse impact on analog and RF circuits. For control pMOSFET, FBB is proven as an effective
solution for improving eff and speed ( fT and fmax) as well as LFN (SID=ID2, H), without resort to strain engineering.
Acknowledgements
This work is supported in part by the National Science Council under Grant NSC 98-2221-E009-166-MY3. Besides, the authors acknowledge the support from National Device Laboratory (NDL) for noise measurement, Chip Implementation Center (CiC) and UMC R&D for devices fabrication.
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![Figure 5 presents the normalized eff shift [ eff ðV BS Þ= eff ðV BS ¼ 0Þ] under FBB and RBB, over various L g](https://thumb-ap.123doks.com/thumbv2/9libinfo/7645798.138802/4.892.175.713.96.292/figure-presents-normalized-shift-þ-fbb-rbb-various.webp)
