A 7.1 mW, 10 GHz All Digital Frequency Synthesizer With Dynamically Reconfigured Digital Loop Filter in 90 nm CMOS Technology

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578 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 45, NO. 3, MARCH 2010

A 7.1 mW, 10 GHz All Digital Frequency Synthesizer

With Dynamically Reconfigured Digital Loop Filter

in 90 nm CMOS Technology

Song-Yu Yang, Wei-Zen Chen, and Tai-You Lu

Abstract—A 10 GHz all digital frequency synthesizer (ADPLL) with dynamic digital loop filter is presented. Governed by a pro-posed locking process monitor (LPM), the digital loop filter is auto-matically reconfigured during the frequency acquisition and phase tracking process. The loop bandwidth is also self-adjusted during the locking process so as to achieve fast lock and low noise simulta-neously. A skew-compensated phase accumulator is proposed for high speed operation, which preserves the advantages of low power dissipation while eliminating the accumulated timing skew issue. With less than 7 s locking time, the measured rms jitter from a 9.92 GHz carrier is about 0.9 ps. The ADPLL core consumes 7.1 mW from a 1 V supply, and the digital I/O cells drains 2.7 mW from a 3.3 V supply for chip measurement. Implemented in a 90 nm CMOS technology, the core area is only 0.352 mm2.

Index Terms—ADPLL, phase-locked loop, phase accumulator, frequency divider, phase-frequency detector, bang-bang phase de-tector.

I. INTRODUCTION

A

LL-DIGITAL phase-locked loop (ADPLL) frequency synthesizers have drawn tremendous research efforts recently as the technology paradigm shifts into the nano-meter CMOS arena [1]–[6]. They circumvent several design is-sues that conventional charge-pump based PLLs encounter, including capacitor leakage, current mismatch, and limited dynamic range under low supply voltage. Besides, the bulky passive loop filter is replaced by more cost-effective digital filter, which can be further scaled down along with the advance-ments in IC technology. Additionally, the digital based design facilitates sophisticated scheme for performance optimization, and also the portability of silicon intellectual property (SIP) for technology migration. Thus, they are more attractive for SoC integration.

Manuscript received April 28, 2009; revised October 30, 2009. Current ver-sion published February 24, 2010. This paper was approved by Associate Editor Jafar Savoj. This work was supported in part by the National Science Council under Contract NSC-97-2220-E-009-009, MediaTek Inc., and ITRI/STC. Chip fabrication was provided by CIC.

S.-Y. Yang is with MediaTek Inc., Hsinchu, Taiwan 30078 (e-mail: xyz1029. ee94g@nctu.edu.tw).

W.-Z. Chen is with the Department of Electronics Engineering, National Chiao-Tung University, Hsinchu 300, Taiwan (e-mail: wzchen@mail.nctu.edu. tw).

T.-Y. Lu is with the Institute of Electronics, National Chiao-Tung University, Hsinchu 300, Taiwan.

Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/JSSC.2009.2039530

Major design issues of the frequency synthesizer are focused on phase purity/timing jitter, reference spur, and locking time. In frequency hopping system and some system clock scenarios where the PLL is disabled during the sleeping mode, the locking speed is of special interests. On the other hand, for the portable devices, the power dissipation is also of special concern. To avoid severe trade-off among the desired properties, some aux-iliary circuits are needed to monitor the locking process and dy-namically adjust the loop parameters accordingly. To accelerate the locking speed, typically, the frequency acquisition process is monitored by a frequency detector [7]–[9] to coarsely tune the oscillator output frequency. On the other hand, a common approach to switch loop bandwidth is by adjusting charge pump current and zero resistors in PLLs [10]. It corresponds to a gear shifting in ADPLL implementation [11]. These techniques can drastically reduce the settling time. However, as the frequency resolution of FD is usually limited, the overall locking time will be dominated by the final phase tracking process.

In this design, an all digital phase-locked loop frequency synthesizer with dynamic digital loop filter is proposed [6]. Governed by a proposed locking process monitor (LPM), the digital loop filter is automatically reconfigured and the loop bandwidth is self-adjusted during the frequency acquisition and phase tracking process. The settling time in both modes is reduced significantly. The locking speed is accelerated by order of magnitude in contrast to the prior art in [8], [11]. It features less than 7 s locking time and 0.9 ps rms jitter while manifesting operating frequency up to 10 GHz.

This paper is organized as follows. Section II describes the ADPLL architecture, its operation principles, and system anal-ysis. Section III describes the detail circuit implementation, in-cluding digital controlled oscillator (DCO), phase accumulator, and the locking process monitor (LPM). The experimental re-sults are shown in Section IV. Finally, Section V draws the con-clusion.

II. ADPLL ARCHITECTURE

The architecture of the proposed ADPLL is illustrated in Fig. 1, which is composed of a dual-mode phase frequency de-tector (DPD), a PI digital loop filter composed of programmable integral and proportional paths, a locking process mon-itor (LPM), an LC based digital controlled oscillator (DCO), a divide-by-4 prescaler, and two phase accumulators PAC1 and PAC2.

To relax the speed requirement of the phase accumulator, the PAC1 accumulates quarter of the frequency multiplication

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YANG et al.: ALL DIGITAL FREQUENCY SYNTHESIZER WITH DYNAMICALLY RECONFIGURED DIGITAL LOOP FILTER 579

Fig. 1. Dynamically reconfigured all digital phase locked loop architecture.

factor . On the other hand, PAC2 follows a divide-by-4 prescaler, accumulating the prescaler output phase. The

quan-tized phase difference between and is

re-solved by a subtractor, and then filtered by the digital loop filter to adjust DCO’s output frequency. To accelerate the locking speed and extend locking range, the DPD is operated in the linear mode during frequency acquisition (FA), and is turned into binary mode during the phase tracking (PT) process. Both modes are moderated by the LPM. The LPM will also dynam-ically adjust the loop parameters according to the phase error and the status of loop filter, which will be further discussed in the following sections.

A. Frequency Acquisition (FA) Mode

In the initial phase of the locking process, the loop is preset in the frequency acquisition mode. Fig. 2(a) illustrates a fre-quency locked loop architecture [7], [9], which is mainly com-posed of a phase accumulator, a frequency detector, and a loop filter. The DCO output frequency is detected by counting clock edges in a reference period (Fig. 2(b)), which is derived by a phase accumulator followed by a differentiator. If is the target locking frequency, is the target number of counts in a reference period, and is the counted DCO cycles, we have (1) and

(2) Then the difference between target frequency and current DCO output frequency can be derived as

(3) If the integrator of loop filter is moved to the input of the sub-tractor, the frequency locked loop becomes equivalent to the

main architecture in Fig. 1 by disabling the integral path of the loop filter. During this mode, the DPD is operated in the linear mode where the output is proportional to frequency error to ac-celerate frequency locking. The frequency detector output con-tinuously adjusts the DCO output frequency. In contrast to the prior art in [7], no reset cycle is needed for frequency detection in this design. It also accelerates the locking speed.

To investigate the locking behavior during FA mode, the system transfer function can be derived as [12]

(4) where

(5) can be adjusted by tuning DCO gain and the propor-tional path gain during frequency acquisition. The root loci analysis shown in Fig. 3(a) indicates that the must be less than 1 to maintain system stability. Fig. 3(b) shows the step response. It reveals that a larger leads to a faster locking time, but also results in larger overshooting during transition.

After variation is settled within one LSB, the frequency acquisition loop is locked and LPM will launch the phase tracking mode. Due to the quantization error of the phase accumulator, the long term frequency error is limited to one adjustable frequency step

(6) which is also proportional to . It shows a trade off between locking speed and accuracy.

B. Phase Tracking (PT) Mode

During this mode, the integral path is then activated, and the whole system is turned into a 2nd order phase-locked loop.

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Fig. 2. (a) Frequency locked loop architecture and (b) frequency counter.

Fig. 3. (a) Root loci of frequency locked loop and (b) step response.

Meanwhile, PAC1 and PAC2 are reset, while the content of the integrator in the loop filter is preset to the current DCO control code. Afterwards, the DPD is switched to the binary phase detection mode without resorting to sophisticated time to digital converter, leading the loop to become a bang-bang PLL. By employing the binary PD, the dynamic behavior of the ADPLL resembles a 2nd order modulator [13].

Fig. 4 shows the phase trace of the bang-bang PLL during locking process [14]. Here the x axis shows the un-quantized phase error , and the y axis illustrates the output of integral path of loop filter. Due to the non-linear phase detection, the bang-bang loop cannot lock onto a fix point on the phase plane. Instead, the condition of loop stability is referred to whether the phase error can settle within a bounded orbit. The constraint for stability can be derived as [14]

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Fig. 4. Phase trace of bang-bang PLL.

where is the loop delay normalized to a reference period. The phase noise performance of the bang-bang PLL is further investigated by linearizing PD gain using Markov chain approx-imation [15], as is shown in Fig. 5. For the solid and dot lines that have the same integral path gain, a larger will broaden the

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Fig. 5. (a) Phase noise performance and (b) output RMS jitter versus loop parameters.

loop bandwidth and speed up the locking process. But it may re-sult in larger steady state jitter if the bang-bang jitter becomes a dominant noise source. On the contrary, for the dot and dash lines that have the same , increasing will degrade the phase margin and lead to jitter peaking, though it can also accelerate the locking speed.

The power spectrum density of phase noise performance under different loop parameters reflects in the integral timing jitter. Fig. 5(b) summarizes the jitter contours. For a constant , it can be seen that a larger will degrade timing jitter due to jitter peaking. On the other hand, for a constant , the timing jitter can be improved by increasing the loop bandwidth to a certain extent. However, this situation will be inverted if the in-band quantization noise of the bang-bang PD dominates the overall jitter performance. Thus, a severe trade-off between locking speed and jitter optimization exits without dynamic digital loop filter. Fig. 5(b) also reveals that, for a target rms jitter of less than one pico-second, a DCO gain of less than 1-kHz per LSB is required (minimum ). It imposes another design challenge for both high frequency and low noise design.

III. CIRCUITIMPLEMENTATION

A. Locking Process Monitor (LPM)

To overcome the trade-off between locking speed and jitter performance, the and are dynamically adjusted during locking process, and is moderated by a proposed locking process monitor (LPM). According to the modulation analogy in the bang-bang PLL behavior [13], the variation

of quantized phase error will become bounded in the steady state. The mean value of , represents the locking frequency of the PLL. Thus, the proximity of frequency lock can be detected by monitoring the ripple superimposed on , which will diminish as the loop approaching the locking state. Based on this principle, the LPM is realized as shown in Fig. 6(a).

The LPM senses the quantized phase error and the in-tegral path output , so as to adjust , and the operation mode accordingly. It is composed of an operation mode con-troller, peak/bottom hold detectors, a gradient polarity detector (GPD), registers, and decision logic for adjusting and . The PLL is initialized as a frequency acquisition loop when the fre-quency switching command is issued. On the other hand, it is switched to the phase tracking mode as the variation of phase error falls within one LSB.

According to the timing diagram in Fig. 6(b), the peak and bottom values of occur when the polarity of is inverted (i.e., the slop of changes its polarity), and is detected by the GPD. Meanwhile, the GPD generates pulses to extract the peak/bottom value. The local maximum and minimum of can then be updated by the peak/bottom hold de-tector, which is toggled by . To rapidly determine its locking status, is estimated by averaging its successive peak and bottom values of

(8) and the consecutive are then stored and compared through registers and decision circuit. The criterion of approaching lock

can be expressed as

(9) where is the locking window and denotes the time interval between two adjacent peak/bottom values. As settles within consecutive samples, the loop parameters , and are then re-duced gradually towards its optimum value in the steady state under the constraint of loop stability, making the loop band-width being dynamically adjusted from a wide band mode to a narrow band mode. By adopting this control scheme, it accel-erates locking speed without cycle slip while keeping low ref-erence spur and timing jitter in the locked state.

Fig. 7 shows the simulation result of the locking behavior with and without the aid of LPM. For the same steady state loop bandwidth, the simulated locking time with the proposed scheme is about 5 s, while that without LPM is about 50 s. In other words, it improves the locking speed by about 10 times.

B. Phase Accumulator

In the ADPLL, the phase accumulator PAC2 is typically implemented as a synchronous counter and thus consumes significant power. Contrarily, an asynchronous accumulator can reduce power though. The accumulated timing skew due to flip-flop clock to data output delay can exceed one input clock period. Thus, the achievable multiplication factor is severely limited especially with high input frequency. To over-come this problem, a novel skew-compensated asynchronous

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Fig. 6. (a) Locking process monitor architecture and (b) timing diagram.

Fig. 7. Comparison of locking behaviors with and without the aid of LPM.

phase accumulator is proposed. It preserves the advantages of low power dissipation while eliminating the accumulated timing skew issue.

Fig. 8(a) shows the detailed block diagram, which is con-structed by an asynchronous counter, resampling registers – , and sampling phase generator. When comes in to fetch the contents in PAC2, the sampling phase for the 1st stage of the asynchronous counter is generated by resampling through 2 D flip-flops to avoid metastability. To circumvent the skew problem caused by clock to data output

delay, instead of sampling all outputs of the counter at the same time, a series of sampling phases are generated to capture the contents of the counter.

Fig. 8(b) illustrates the timing diagram of the critical case when the contents of the asynchronous counter change from to . In this case the overflow signal propagates from the first stage to the last stage, leading to a maximum timing skew. In the sampling phase generator, is then postponed by D-latches – that are toggled by the falling edge of the 1st–3rd stage divider outputs – , to generate the sampling phases – . Thus, a minimum setup

time of can be guaranteed when

retrieving the contents of the ripple counter. The stages 4 to 8 are all resampled by since a setup time of

is sufficient for flip-flop operating at and below. The

PAC2 output is then stored in as . By

com-pensating for accumulated timing skew, the uncertainty in phase detection by band-bang detector is limited to one clock cycle. It also prevents the detectable frequency resolution bounded by (6) from getting worse.

C. Digitally Controlled Oscillator (DCO)

Fig. 9 illustrates the DCO schematic, which is based on LC-tank oscillator architecture. The output frequency is varied by digitally tuning the varactor bank. A differential planar inductor of 1.2 nH is adopted. The quality factor of the inductor is about 9 at 10 GHz. The varactor is based on N-channel inversion mode device, and its simulated Q at 10 GHz is about

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Fig. 8. (a) Skew compensated phase accumulator and (b) timing diagram.

Fig. 9. DCO architecture.

25. The DCO core circuit is biased by a pMOS current source with on-chip regulator to minimize flicker noise and improve PSRR.

As are discussed in the previous sections, to achieve sub-pico second RMS jitter, the DCO resolution must be better than 1-kHz per LSB. To reduce chip area of the varactor bank, the fre-quency tuning is accomplished by a 7 bits coarse tuning bank, followed by a 10 bits fine tuning bank to ensure linearity. The frequency resolution is further enhanced to 250 Hz per LSB by

employing high speed dithering through an 8-bit second order modulator.

IV. EXPERIMENTALRESULTS

The experimental prototype has been fabricated in a 90 nm CMOS process. Fig. 10 shows the chip micrograph. The chip size is 0.902 mm , which is mainly occupied by the LC res-onator and the digital IO cells. The core area is only 0.352 mm . The ADPLL core consumes 7.1 mW from a 1 V supply, among

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Fig. 10. ADPLL chip micrograph.

which the phase accumulator consumes 0.97 mW, the prescaler consumes 1.33 mW, the DCO consumes 3.9 mW, and logic circuitries dissipate 0.9 mW. Additionally, the digital I/O cells drain 2.7 mW from a 3.3 V supply for chip measurement.

The phase noise and PLL output spectrum are both measured using Agilent E4448A spectrum analyzer. With 40 MHz refer-ence frequency and a multiplication factor of 248 , the measured phase noise form the 9.92 GHz carrier is shown in Fig. 11. The phase noise at 1 MHz offset is about dBc/Hz. By frequency domain measurement, the integrated timing jitter from 50 kHz to 80 MHz is about 1.1 ps, and is about 1.13 ps when the integrated bandwidth is extended to 1 GHz. The timing jitter is mainly dominated by the in-band noise.

For a bang-bang PLL loop with a loop delay of clock cycle, and the ratio between integral and proportional path gain

be , the limit cycle oscillation frequency can be derived as [14]

(10) where is the integer number that satisfies the following con-straint:

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In this design, , and in the steady

state. By substituting the design parameters into (10) and (11), the DCO output frequency is modulated in a rectangular

wave-form at MHz due to bang-bang operation, whose

peak to peak frequency deviation is about .

By Fourier series expansion, cyclic tones at can be seen around the DCO output frequency .

Fig. 12 shows the measured output spectrum from a 9.92 GHz carrier. Spurious tones at 10 MHz and 30 MHz offset are respec-tively dB and dB below the main carrier. The reference spur at 40 MHz offset is about dB below the main carrier. For wireless communication applications, spurious tones should

Fig. 11. Phase noise performance.

Fig. 12. Output spectrum.

Fig. 13. Measured time domain waveform.

be suppressed to avoid reciprocal mixing issues, which can be achieved by adjusting to decrease .

The time domain performance is characterized using Tek-tronix DPO71254 oscilloscope. Fig. 13 shows the time domain waveform. The measured rms jitter is about 0.9 ps, including random jitter, periodic jitter, and the trigger jitter of the instru-ment for about 100 fs (rms). The jitter measured in time domain is quite close to that characterized in the frequency domain, and

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TABLE I PERFORMANCEBENCHMARK

Fig. 14. (a) Measured locking time and (b) the zoomed-in locking behavior.

the timing jitter deteriorated by the spurious tones is negligible compared to its random jitter.

For locking behavior characterization, the divide-by-8 output is measured to comply with the input bandwidth of the modu-lation domain analyzer (Agilent 53310A). When the output fre-quency hops form 9.92 GHz to 10.08 GHz, the measured settling time within 20 ppm accuracy is about 6.89 s, as is shown in Fig. 14(a). Fig. 14(b) shows the zoom-in version of the locking characteristic.

Table I summarizes the ADPLL performance and benchmark with the state of the art in the literature. The proposed architec-ture manifests the highest output frequency, fastest locking time,

highest multiplication factor, and also highest power efficiency in terms of GHz/mW.

V. CONCLUSION

This paper presents a 10 GHz all-digital frequency synthe-sizer with less than 1 ps rms jitter and less than 7 s locking time. The ADPLL manifests fast locking speed as well as low jitter performance by the dual mode phase and frequency de-tection scheme and dynamically reconfiguring the digital loop filter, which is governed by the proposed LPM engine. Also, the output jitter is comparable to most analog PLLs without resort

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to sophisticated TDC. Finally, a novel skew-compensated chronous phase accumulator is proposed. Operating as an asyn-chronous counter, it preserves the advantages of power scaling while capable of high speed operation and providing high divi-sion ratio.

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Song-Yu Yang was born in Chiayi, Taiwan, in 1983.

He received the B.S. and M.S. degrees in electronics engineering from National Chiao-Tung University, Hsinchu, Taiwan, in 2005 and 2008, respectively.

He is currently with MediaTek Inc., Hsinchu, Taiwan. His research interests focus on integrated circuit designs for high-speed communication sys-tems.

Mr. Yang is a member of Phi Tau Phi honorary scholar society.

Wei-Zen Chen received the B.S., M.S., and Ph.D.

degrees in electronics engineering from National Chiao-Tung University, Hsinchu, Taiwan, in 1992, 1994, and 1999, respectively.

From 1999 to 2002, he was with the Department of Electrical Engineering, National Central Univer-sity, Chung-Li, Taiwan. Since 2002, he joined the Department of Electronics Engineering, National Chiao-Tung University, where he is now a Full Professor. He is the Deputy Executive Director of the National SoC Program in Taiwan, and also serves as IEEE Solid-State Circuit Society Taipei Chapter Chair starting from 2008.

Dr. Chen’s research focuses on mixed-signal integrated circuit for wireless and wireline communication systems. He is a member of Phi Tau Phi honorary scholar society and technical program committee member of the IEEE Custom Integrated Circuits Conference (CICC) and IEEE Asian Solid-State Circuits Conference (A-SSCC).

Tai-You Lu was born in Taipei, Taiwan, in 1980.

He received the B.S. degree in electrical engineering from National Cheng-Kung University, Taiwan, in 2003. He is currently pursuing the Ph.D. degree in the Institute of Electronics, National Chiao-Tung University, Hsinchu, Taiwan.

His research focuses on the design of radio frequency integrated circuits for wireless commu-nications. He is a member of Phi-Tau-Phi honorary scholar society.