Effects of Minority-Carrier Response Behavior on
Ge MOS Capacitor Characteristics: Experimental
Measurements and Theoretical Simulations
Chao-Ching Cheng, Chao-Hsin Chien, Associate Member, IEEE, Guang-Li Luo, Yu-Ting Ling,
Ruey-Dar Chang, Member, IEEE, Chi-Chung Kei, Chien-Nan Hsiao, Jun-Cheng Liu, and
Chun-Yen Chang, Life Fellow, IEEE
Abstract—In this paper, we present MEDICI simulations of
the admittance-voltage properties of Ge and Si MOS devices, including analyses of substrate conductance Gsub and high–low
transition frequency ftran, to explore the differences in the
minority-carrier response. The Arrhenius-dependent Gsub
char-acteristics revealed that a larger energy loss—by at least four orders of magnitude—occurs in Ge than in Si, reflecting the fast minority-carrier response rate, i.e., a higher value of ftran. We
confirmed that the higher intrinsic carrier concentration in Ge, through the generation/recombination of midgap trap levels as well as the diffusion mechanism, resulted in the onset of low-frequency C –V curves in the kilohertz regime, accompanying the gate-independent inversion conductance. The experimental data obtained from Al2O3/Ge MOS capacitors were consistent with
the values of Gsub and ftran obtained from MEDICI
predic-tions and theoretical calculapredic-tions. In addition, upon increasing the inversion biases, we observed shifts in the Gsub/f
con-ductance peaks to low frequencies that mainly arose from the transition of minority carriers with bulk traps in the depletion layer. Meanwhile, we estimated that the bulky defects of ca. (2−4) × 1015cm−3exist in present-day low-doped Ge wafers.
Index Terms—Bulk trap, germanium (Ge), MEDICI simulation,
minority-carrier response, MOS capacitor, substrate conductance. I. INTRODUCTION
V
ARIOUS high-k gate dielectrics, substrate materials, and device structures have been proposed to relieve the enor-mous scaling burden required to improve transistorperfor-Manuscript received August 26, 2008; revised December 4, 2008. First published March 16, 2009; current version published April 22, 2009. This work was supported by the National Science Council of the Republic of China (Contract NSC94-2215-E009-066). The review of this paper was arranged by Editor H. S. Momose.
C.-C. Cheng, J.-C. Liu, and C.-Y. Chang are with the Institute of Electronics, National Chiao-Tung University, Hsinchu 300, Taiwan.
C.-H. Chien is with the Department of Electronics Engineering, Institute of Electronics, National Chiao-Tung University, Hsinchu 300, Taiwan, and also with the National Nano Device Laboratory, Hsinchu 300, Taiwan.
G.-L. Luo is with the National Nano Device Laboratory, Hsinchu 300, Taiwan.
Y.-T. Ling and R.-D. Chang are with the Department and Graduate Institute of Electronic Engineering, Chang Gung University, Tao-Yuan 300, Taiwan.
C.-C. Kei is with the Instrument Technology Research Center, National Ap-plied Research Laboratories, Hsinchu 300, Taiwan, and also with the National Tsing Hua University, Hsinchu 30013, Taiwan.
C.-N. Hsiao is with the Vacuum Technology Division, Instrument Technol-ogy Research Center, National Applied Research Laboratories, Hsinchu 300, Taiwan.
Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TED.2009.2016020
mance. High-k/Ge structure-based devices are considered new potential candidates to replace conventional Si MOSFETs for high-performance logic devices because of their high intrinsic carrier mobility. Much effort has been devoted to improve the high-k/Ge interface and junction leakage characteristics through both surface passivation [1]–[3] and process modifi-cation [4], [5]; several promising results have recently been demonstrated [6]–[8]. Interestingly, an uncommon electrical characteristic—the fast minority-carrier response—has been manifested during electrical measurements of Ge MOS capac-itors; its variation with respect to the interface state response is also a noteworthy issue that requires clarification. In fact, many years ago, Nicollian and Brews [9] foresaw that it would be possible to observe an LF C–V curve for a narrow-gap material, such as Ge, at the standard HF used for traditional Si because of the higher intrinsic carrier concentration ni.
Such minority-carrier characteristics for capacitors deposited on Si substrates have been established and correlated to the effects of the temperature, doping concentration, and impurity contamination; however, similar studies using Ge substrates remain rare [10]–[12]. The influences of the doping concen-tration and the substrate type on this anomalous C–V behavior have been discovered in high-k/Ge MOS capacitors [13], [14]; the fundamental mechanisms were clarified through fitting of MOS-equivalent circuit models [10], [11] and measurements of Arrhenius-dependent conductance properties [12], respec-tively. In this paper, we utilized a 2-D MEDICI numerical simulator, accompanied by theoretical calculations, to compre-hensively investigate the minority-carrier response—as func-tions of the doping concentration, measured frequency, and temperature—in terms of the electrical properties of Ge and Si MOS capacitors. We have also examined the underlying mechanistic differences through practical admittance measure-ments of atomic-layer-deposited (ALD) Al2O3 thin films on both types of Ge substrates.
II. MEDICI SIMULATION AND
EXPERIMENTALPROCEDURES
A. MEDICI Simulation Program
The computer simulation program MEDICI has been em-ployed to predict the semiconductor device properties of several electronic structures, including HEMTs [15], MOSFETs [16],
CHENG et al.: EFFECTS OF CARRIER RESPONSE BEHAVIOR ON Ge MOS CAPACITOR CHARACTERISTICS 1119
silicon oxide high-k oxide silicon [17], photodetectors [18], and junction diodes [19]. By self-consistently solving the Poisson equation and the continuity equations in MEDICI, we can sim-ulate the admittance properties of MOS structures containing SiO2 (30 Å) and Al gates to examine the minority-carrier characteristics in Si and Ge. In addition, MEDICI makes it possible to perform simulations at relatively high frequencies and low temperatures by providing the appropriate physical models and parameters. Most importantly, the contributions of the interface states to both the capacitance and conductance loss at depletion can be omitted, which is beneficial to the analysis of admittance-voltage data in the inversion region. Apart from a large difference in the value of the energy bandgap for these two substrates, both carrier lifetime and mobility, which are dependent on the carrier concentration and the temperature, are critical in determining the minority-carrier generation behavior. Moreover, the bulk trap level at midgap was assumed for both substrates.
B. Fabrication of the MIS Capacitor
We prepared p- and n-type Ge wafers that were doped with Ga and Sb dopants at levels of ca. 2× 1015 and ca. 1× 1014cm−3, respectively. The Si wafer, having a standard doping concentration of ca. 1× 1016 cm−3, was also studied for comparison. All wafers were precleaned through a cyclic rinse with dilute hydrofluoric acid and deionized water. The Al2O3 high-k layer was deposited using the ALD system at a substrate temperature of 100◦C; the physical thickness was ca. 64(±2) Å according to the established growth rate of ca. 1.06 Å/cycle. Trimethylaluminum [Al(CH3)3] and H2O were chosen as the metal source and oxidant, respectively; they were alternatively pulsed into the reactor for 1 s per pulse separated by a N2purge of 10 s to remove the redundant reactants. The top capacitor electrode was formed via a shadow mask by de-positing electron-beam Pt at a film thickness of ca. 700 Å(area, ca. 4× 10−4 cm2), whereas the backside contact was made through the thermal evaporation of Al. Finally, the entire MOS structure underwent forming gas annealing (N2/H2, 90:10) at 300◦C for 30 min. The admittance-voltage characteristics were measured in the parallel mode using HP4284, and then they were corrected by excluding the series resistance and parasitic components. The temperature- and frequency-dependent elec-trical curves in depletion and weak inversion were investigated to explore the latent minority-carrier mechanism.
III. RESULTS ANDDISCUSSION
Figs. 1 and 2 present the simulated C–V and G–V charac-teristics of Al/SiO2 gate stacks on p-Si and p-Ge substrates at various temperatures, respectively. It was observed that the dielectric on Si [Fig. 1(a)] obviously presented the LF C–V curves only when raising the temperature up to 400 K and reducing the frequency to as low as 100 Hz. In contrast, such LF curves readily occurred at 300 K for Ge systems in which the doping concentrations were 1016and 1014cm−3[Fig. 1(b) and (c), respectively]. We observed the minority-carrier behavior even at higher frequencies, e.g., 1 MHz, in the low-doped Ge.
On the contrary, the complete HF C–V curves appeared only in the high-doped Ge at temperatures as low as 250 K. By examining the simulated conductance Gmea in the Si case [Fig. 2(a)], the inversion conductance Ginvrevealed frequency independence up to 100 kHz; the values increased by about two orders of magnitude as we increased the temperature from 300 to 400 K. From Fig. 2(b) and (c), the Ge counterpart reveals two distinct features: The Ginvcharacteristics measured at low temperature (250 K) were identical to those in Si at high temperature (400 K); upon increasing the temperature to 350 K, the value of Ginv became proportional to the square of the angular frequency ω, which is similar to the curves observed in accumulation. The resultant w2 dependence of
G–V curves implied similar equivalent operation circuits in
both accumulation and inversion for Ge MOS capacitors at higher temperatures, e.g., > 300 K. In general, the electrical differences in inversion between Ge and Si are dependent on the dominance of either the Ginv or wCinv term, which are further correlated to the measured temperature, frequency, and properties of the substrate material. We will understand the minority-carrier conductance loss through the theoretical cal-culations of these two components, together with the following experimental findings. Note that the absence of interface states was assumed in simulation; hence, they did not contribute to the energy loss, thereby causing the onset of a deeper “dip” in depletion.
Figs. 3 and 4 display the measured C–V and G–V character-istics of Pt/ALD-Al2O3gate stacks deposited on p-Ge and n-Ge substrates, respectively. First, as illustrated in Figs. 3(a)–(c) and 4(a)–(c), the minority-carrier response occurred in C–V inversion for both types of Ge. The low-doped (1014 cm−3) n-Ge exhibited a relatively faster rate with respect to p-Ge (2× 1015 cm−3), which we attribute to the resultant high-minority-carrier concentration. Moreover, Figs. 3(d)–(f) and 4(d)–(f) display the gate-bias-independent values of Ginv in Ge with more severe frequency dispersion upon increasing the measured temperature, unlike the exponential decline of the conductance curves in inversion for Si MOS capacitors (not shown here).
From the equivalent circuit model [20], the simulated values of Gsub in inversion, i.e., Ginv, are the parallel combination of generation/recombination conductance Ggr and diffusion conductance Gdiff, where Ggr is due to the finite g–r within the depletion layer through the bulk traps, and Gdiff is due to the diffusion current of the minority carriers from the bulk to the edge of the depletion region. At lower temperatures, Ggr is more significant [9], [20] and can be expressed using the equation Ggr A = q φS ni 1 w τT (1)
where φS and w are the surface potential and
deple-tion layer width in inversion, respectively, and τT is the
Shockley–Read–Hall lifetime determined by the density of g–r centers and the capture coefficients for electrons and holes, re-spectively. As the temperature further increases, Gdiff becomes
Fig. 1. MEDICI-simulated C–V curves of Al/SiO2gate stacks on Si and Ge substrates under measured temperatures ranging from 250 to 400 K. (a) p-Si,
1016cm−3. (b) p-Ge, 1016cm−3. (c) p-Ge, 1014cm−3. Note that the measured frequencies are labeled by solid symbols: square (1 MHz), circle (100 kHz),
up-triangle (10 kHz), down-triangle (1 kHz), and star (100 Hz).
dominant because of the increasing function of n2
i [9], [20], as
revealed by the following equation:
Gdiff A = q2 kT n2 i Nmaj Lmir τmir = qNmirμmir Lmir (2) where Nmaj is the substrate doping concentration, and
Lmaj(τmir) and μmir are the diffusion length (lifetime) and mobility of minority carriers in the bulk material, respec-tively. To correctly observe the temperature dependence of the minority-carrier response behavior, all of the parameters are a function of the temperature in the calculations, except for τT
because of the weakly temperature dependence. In Fig. 5(a), we provide the simulated result of Arrhenius-dependent substrate conductance Gsubin Si and Ge at various dopant concentrations (1014and 1016cm−3), plotted with experimental data obtained from this and previous studies. Note that these values of Gsub in inversion, i.e., Ginv, can be extracted by directly subtracting the reactance of the insulator capacitor Cinsfrom the commonly used parallel equivalent circuit. As seen for both Si and Ge cases, the simulated Gsubcurves can be divided into two stages: one dominated by Gdiff at high temperatures and the other by
Ggrat low temperatures. Most importantly, the values of Ginv of the dielectric on Ge were larger than those on Si by at least
four orders of magnitude, which is indicative of a larger energy loss occurring in Ge. Both our data of Al2O3/p-Ge and the reported HfO2/n-Ge structure [12] are in agreement with the simulation results for the SiO2/p-Ge structure.
Using (1) and (2), we evaluated the respective components of
Ggrand Gdiffin Ginvfor these two substrates. A high bulk trap volume density NT of 1015 cm−3 was assumed in Ge, which
is relative to a value of 1014 cm−3 in Si, because Ge wafer quality has not yet developed to a satisfactory level. Fig. 5(b) reveals that the crossover temperature TCat which the transition is made from the g–r mechanism dominating to the diffusion-controlled process was ca. 330 K for p-Ge, which is close to the value of ca. 318 K characterized for high-k/n-Ge(ND=
ca. 7× 1014 cm−3) [12]. Relative to the value of TC of ca.
442 K for its Si counterpart, we ascribe the lower value for Ge to its higher value of ni. Here, the deviations in the values of Ginvevaluated via the MEDICI simulations and the theoretical calculation arose from the adopted material parameters, e.g., the
NT value. We also calculated the magnitude of the wCinvterm for comparison with the values of Ginvin these two substrates, where Cinvis defined using the following [9]:
Cinv= εsεo √ 2LD ni Nmaj exp −qφS 2kT (3)
CHENG et al.: EFFECTS OF CARRIER RESPONSE BEHAVIOR ON Ge MOS CAPACITOR CHARACTERISTICS 1121
Fig. 2. MEDICI-simulated G–V curves of Al/SiO2gate stacks on Si and Ge substrates under measured temperatures ranging from 250 to 400 K. (a) p-Si,
1016cm−3. (b) p-Ge, 1016cm−3. (c) p-Ge, 1014cm−3. Note that the measured frequencies are labeled by solid symbols: square (1 MHz), circle (100 kHz),
up-triangle (10 kHz), down-triangle (1 kHz), and star (100 Hz).
where εsis the substrate dielectric constant, LD is the Debye
length, and φS is equal to 2φB at the threshold inversion
point (φB is the bulk potential). The calculations revealed
that wCinv Ginv for the Si case at temperatures up to ca. 400 K; thus, the equivalent substrate circuit in inversion is often simplified further so that the depletion capacitance Cdep changes in parallel only with the Ginvterm. This conclusion is only suitable for the Ge counterpart when the temperatures de-crease below ca. 250 K; meanwhile, the opposite behavior, i.e.,
wCinv Ginv, occurs at temperatures above ca. 350 K. That is, at intermediate temperatures (250–350 K), the minority-carrier response in Ge MOS capacitors is strongly dependent on the measured temperature and frequency.
Here, we define the effective transition frequency ftran—at which the capacitance in inversion is midway between Cins and the HF capacitance Chf—as marking the onset of the LF
C–V behavior. Our experimental data for ftran observed in Al2O3/p-Ge (Fig. 3) are within the MEDICI-simulated predic-tions in Fig. 6(a). The fast response rates in the Ge capacitors corresponded to the higher values of ftran, i.e., ca. 5 and 200 kHz at RT for Ge doped at 1016 and 1014cm−3, respec-tively. Higher degrees of substrate doping and lower measured temperatures accordingly lowered the order of ftrandue to the abatement of minority-carrier disturbance. From these studies,
we conclude that the two energy loss mechanisms, i.e., Ggr and Gdiff, are responsible for the supply of minority carriers to the inversion layer, providing LF-like C–V properties in the kilohertz regime. Previously, Bai et al.[14] reported an interesting phenomenon in HfO2/p-Ge: An increase in the degree of substrate doping from 1015to 4× 1017cm−3reduced the value of ftranfrom greater than 100 kHz to less than 10 kHz. Upon increasing the Ge concentration to 3× 1018cm−3, how-ever, the value of ftranincreased again to greater than 1 MHz, which is opposite to the trend that we expected. To explain this anomalous behavior, we correlated the value of ftranto the changes in Ginvusing the following equation [9]:
ftran= Ginv 2πCins 1− Chf Cins (4) using a value of Cinsof 1.11 μF/cm2as in our Al2O3/Ge cases, i.e., corresponding to the capacitance-equivalent thickness of 30 Å, and with the assumption that the number of bulk traps was proportional to the dopant concentration. We observe in Fig. 6(b) that Ge doped at 1018cm−3exhibited a relatively high value of ftranwith respect to that of the low-doped Ge. Consid-ering that the values of NTranging from ca. 1014to 1016cm−3
Fig. 3. (a)–(c) C–V and (d)–(f) G–V curves of Pt/ALD-Al2O3/p-Ge MOS capacitors measured at temperatures of 20◦C, 40◦C, and 60◦C, respectively.
CHENG et al.: EFFECTS OF CARRIER RESPONSE BEHAVIOR ON Ge MOS CAPACITOR CHARACTERISTICS 1123
Fig. 5. (a) Simulated Arrhenius-dependent substrate conductances Gsubin Si
and Ge at two dopant concentrations (1014and 1016cm−3), plotted with the
experimental data obtained in this and previous studies [9], [12]. The simulated
Gsub data can be fitted by the (solid lines) diffusion conductances Gdiff
and (dashed lines) g–r conductances Ggr. (b) Calculations of
temperature-dependent Gdiffand Ggrin Si and Ge substrates having dopant concentrations
of 2× 1015cm−3. The values of NTwere 1014and 1015cm−3in Si and Ge,
respectively. The values of the wCinvterm were also calculated in terms of the
frequency range 1 kHz–1 MHz.
and low-doped Ge substrates [21], [22], together with a max-imum solid solubility of ca. 1019 cm−3 for p-type dopants, we suspect that the highly doped p-Ge wafer might contain a large number of midgap traps (e.g., 1017−1019 cm−3) inside the depletion layer [14], possibly arising from high degrees of Fe and Ni metal impurities [22], dopant precipitation, and/or metal–dopant combined defects. In reality, the density of bulky defects is governed not only by the wafer type and contami-nation by impurities but also by the device’s fabrication [23], [24], in particular, the dielectric–Ge interface, which, in turn, influences the degree of the minority-carrier response on the measured frequency. In other words, the magnitude of Ggr is probably comparable with that of Gdiff—possibly even exceed-ing it at higher temperatures—but Gdiff still immediately rules the inversion conductance Ginv as the temperature increases further.
On the other hand, because the device equivalent circuit in inversion is similar to that in depletion, it is essential to
Fig. 6. (a) Simulated temperature-dependent transition frequencies ftranin Si
and Ge at two dopant concentrations (1014and 1016cm−3), plotted along with
our experimental data from Figs. 5 and 7. (b) Calculated temperature-dependent transition frequencies ftranin Si and Ge substrates, determined according to
the material parameters in Fig. 8. Different values of NT(1017− 1019cm−3)
were assumed for our highly doped Ge system.
explore the differences between the minority-carrier-induced loss and the interface-state loss with respect to the measured frequency. Thus, we calculated the temperature dependence of the interface-state response frequency fit as a function of the surface potential using the following equation [9]:
fit= vthσcapni π exp −qφS kT (5) where vthis the thermal velocity, and σcapis the capture cross section. Supposing that the standard measured frequency is in the range 103–106Hz, as depicted in Fig. 7(a), we can detect
Ditclose to the midgap in Ge only at values of fitgreater than 105Hz, which is quite different from the Ditresponse observed as low as 103 Hz in Si. Indeed, we observed depletion bumps at frequencies of 50–1000 kHz for the Al2O3/p-Ge capacitors (Fig. 3) and at 1–100 kHz for the Al2O3/p-Si capacitors (not shown here). In contrast, we did not observe any such bump for the corresponding n-Ge case (Fig. 4) because of the intense minority-carrier loss. The calculated results in Fig. 7(b) and (c) suggest that continuously decreasing the temperature from 300
Fig. 7. (a) Calculated response frequency fitof interface states plotted as a function of the surface potential φSfor Si and Ge capacitors at RT. (b) Temperature
dependence of the plots of fitversus φSfor the Ge capacitor. The shadow region represents the standard frequency range 1 kHz–1 MHz used for the measurements.
(c) Plot of the φSdependence of observable Ditin the Ge bandgap at various measured temperatures (within the standard frequency range). For comparison, the
temperature dependence of the Ge bandgap is presented on the right-hand y-axis.
to 100 K is a practical means of extracting the overall dis-tribution of Dit within the Ge bandgap. Such a temperature-dependent conductance method is discussed in detail in a recent literature review by Martens et al.[10].
Fig. 8(a)–(f) displays the Gsub/f versus log f characteristics for both types of Ge under gate biases ranging from the midgap to the inversion. We employed the statistical conductance model to estimate the values of the midgap Ditfor p-Ge and n-Ge of ca. 7(±1) × 1011 and 1.5(±0.5) × 1012 cm−2 eV−1, respec-tively. An interesting trend appeared for the devices biased into the inversion conditions: The Gsub/f peak gradually moved to lower frequency, accompanied by an increased intensity, and upon raising the temperature; as a consequence, the overall conductance spectra shifted to higher frequency. Because of the presence of a high minority-carrier density, this phenomenon reveals that we must consider the communication of interface traps not only with majority carriers but also with minority carriers in Ge MOS capacitors. Even so, we still believe that such a shift in the frequency-dependent conductance peaks is mainly correlated to the Ginv loss within the substrate itself, overwhelming the Dit-induced energy loss in inversion. We rationalize this behavior by considering the following obser-vations. First, from the viewpoint of the fit calculation, the
Gsub/f peaks appear far below 105 Hz, which is irrational
for the Ditresponse in Ge devices that are close to RT. Next, assuming that the transition of the surface minority carriers with
Ditdominates the conductance peaks in inversion, the resultant shorter lifetime in the charging/discharging of Ditshould shift them to higher frequency, rather than lower frequency, upon increasing the inversion biases. In fact, a Λ-shaped distribution in the trap time constant across the overall Ge bandgap was ob-served under a quite low temperature of 80 K when employing a full conductance measurement [10], in which the Gsub/f peaks shifted initially to lower frequency and subsequently to higher frequency with respect to the gate bias. In addition, according to the classical bulk trap model proposed by Nicollian and Brews [9], the resultant frequency of the Gsub/f maximum should coincide with the value of ftran observed in the C–V curves. Indeed, we observed that the conductance peaks (and values of
ftran) for p-Ge capacitors were located at ca. 4 (3), 20 (15), and 100 kHz (130 kHz) at 20◦C, 40◦C, and 60 ◦C, respectively, when Vgwas equal to 1 V. The trends were also consistent for
the n-Ge cases. In addition, we estimated the effective values of NT simply from the corresponding magnitudes of Gsub/f by evaluating the depletion width swept out by 2-kT band bending; the resulting values of NT for p-Ge and n-Ge were ca.
3.9× 1015 and 2.5× 1015 cm−3, respectively, reflecting high levels of bulky defects existing in these particular Ge wafers.
CHENG et al.: EFFECTS OF CARRIER RESPONSE BEHAVIOR ON Ge MOS CAPACITOR CHARACTERISTICS 1125
Fig. 8. Measured values of Gsub/w plotted with respect to the log frequency for Pt/ALD-Al2O3gate stacks on (a)–(c) p-Ge and (d)–(f) n-Ge substrates at
temperatures of 20◦C, 40◦C, and 60◦C, respectively.
IV. CONCLUSION
We have characterized the substrate conductance and tran-sition frequency characteristics through MEDICI simulations and device experiments on Ge and Si substrates to under-stand their minority-carrier response behavior. The plot of the Arrhenius-dependent Gsub indicated a larger energy loss occurring in Ge than in Si by at least four orders of magnitude, corresponding to the fast minority-carrier response rate. Our Al2O3/Ge MOS capacitors exhibited values of Gsuband ftran that were both close to those of the MEDICI prediction. We have also validated that a high value of ni in Ge, via the
bulk-trap generation/recombination as well as the diffusion from the bulk substrate, caused the onset of the LF C–V curves in the kilohertz regime and the gate-independent inversion conductance. In addition, we have suggested that the shift in the
Gsub/f conductance peaks to low frequency upon increasing the inversion bias is mainly due to the transition of minority carriers with bulk traps in the depletion layer, in which the value of NT reached as high as ca. (2−4) × 1015 cm−3 in the
low-doped Ge.
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Chao-Ching Cheng received the B.S. degree in
electronic engineering in 2003 from Chang-Gung University, Tao-Yuan, Taiwan, and the M.S. degree in electronic engineering in 2005 from the National Chiao-Tung University (NCTU), Hsinchu, Taiwan, where he is currently working toward the Ph.D. degree related to Ge and III–V MOSFETs in the Institute of Electronics.
His main research interests include the study of the interface and device properties of Ge and III–V sub-strates integrating with high-k materials, heteroepi-taxial technology, and electrical characteristics of SiGe film in various III–V materials.
Chao-Hsin Chien (M’04–A’05) was born in 1968.
He received the B.S., M.S., and Ph.D. degrees in electronics engineering from the National Chiao-Tung University (NCTU), Hsinchu, Taiwan, in 1990, 1992, and 1997, respectively. His Ph.D. dissertation research focused on plasma-induced charging dam-age on deep-submicrometer devices with ultrathin gate oxides.
In 1999, he was with the National Nano Device Laboratory, Hsinchu, as an Associate Researcher. He is currently an Associate Professor with the Depart-ment of Electronics Engineering, Institute of Electronics, NCTU. His research interests and activities include high-κ dielectric, novel nonvolatile memory devices, organic devices, and nanowires.
Guang-Li Luo received the Ph.D. degree in
solid-state physics from the Chinese Academy of Sciences, Beijing, China, in 1997.
From 1997 to 2001, he was a Faculty Member with the Institute of Microelectronics, Tsinghua Univer-sity, Beijing. In 2002, he was with the Microelec-tronics and Information Systems Research Center, National Chiao Tung University, Hsinchu, Taiwan, as an Assistant Researcher and then as an Associate Researcher. Since July 2005, he has been an As-sociate Researcher with the National Nano Device Laboratory, Hsinchu. His research interests include SiGe epitaxy and related devices.
Yu-Ting Ling, photograph and biography not available at the time of
publication.
Ruey-Dar Chang (S’89–M’90–S’96–M’98) was
born in Taichung, Taiwan, in 1966. He received the B.S. degree in materials engineering from the National Cheng Kung University, Tainan, Taiwan, in 1988, the M.S. degree from the National Chiao Tung University, Hsinchu, Taiwan, in 1990, and the Ph.D. degree in electrical engineering from the University of Texas, Austin, in 1998.
From 1990 to 1994, he was with the Electronics Research and Service Organization/Industrial Tech-nology Research Institute, Hsinchu, where he was engaged in the development of process simulation and DRAM devices under the Submicron Project. In 1994, he joined the Vanguard International Semi-conductor Corporation, Hsinchu, where he was responsible for the DRAM device design and TCAD. Since 1998, he has been with the Department and Graduate Institute of Electronic Engineering, Chang Gung University, Tao-Yuan, Taiwan, where he is an Assistant Professor. He currently works on CMOS process modeling, doping profile characterization, TFT technology modeling, and power devices.
Chi-Chung Kei was born in Taiwan. He received
the B.S. and M.S. degrees in materials science en-gineering in 2000 and 2002, respectively, from the National Tsing Hua University (NTHU), Hsinchu, Taiwan, where he is currently working toward the Ph.D. degree in materials science engineering.
He is currently an Associate Researcher with the Instrument Technology Research Center, National Applied Research Laboratories, Hsinchu. His re-search interests include the developments of atomic layer deposition and UHV metal-organic chemical vapor deposition systems, and the fabrication and characterization of III–V compound semiconductors, high-k dielectrics, and nanostructured materials.
Chien-Nan Hsiao received the Ph.D. degree in
ma-terials science and engineering from Taiwan Univer-sity, Taipei, Taiwan, in 2000.
He is currently a Researcher and the Director of the Vacuum Technology Division, Instrument Tech-nology Researcher Center, National Applied Science Laboratories, Hsinchu, Taiwan. His research inter-ests include synthesis and characterization thin-film materials and vacuum technology.
CHENG et al.: EFFECTS OF CARRIER RESPONSE BEHAVIOR ON Ge MOS CAPACITOR CHARACTERISTICS 1127
Jun-Cheng Liu was born in Kaohsiung, Taiwan. He
received the M.S. degree in electronics engineering from the National Chiao Tung University (NCTU), Hsinchu, Taiwan, in 2007.
He is currently with the Institute of Electron-ics, NCTU. His research interests focus on material analysis, device fabrication, and electrical measure-ments of the ALD high-k/Ge MOSFETs.
Chun-Yen Chang (S’69–M’70–SM’81–F’88– LF’05) was born in Feng-Shan, Taiwan. He received the B.S. degree in electrical engineering from the National Cheng Kung University (NCKU), Tainan, Taiwan, in 1960 and the M.S. and Ph.D. degrees from the National Chiao Tung University (NCTU), Hsinchu, Taiwan, in 1962 and 1969, respectively.
He has profoundly contributed to the areas of mi-croelectronics, microwave, and optoelectronics, in-cluding the invention of the method of low-pressure MOCVD using triethylgallium to fabricate LED, laser, and microwave devices. He pioneered works on Zn incorporation (1968), nitridation (1984), and fluorine incorporation (1984) in SiO2 for ULSIs, as
well as in the charge transfer in semiconductor–oxide–semiconductor system (1968), carrier transport across metal–semiconductor barriers (1970), and the theory of metal–semiconductor contact resistivity (1971). In 1963, he joined the NCTU to serve as an Instructor, establishing a high vacuum laboratory. In 1964, he and his colleagues established the nation’s first and state-of-the-art Semiconductor Research Center, NCTU, with a facility for silicon planar device processing, where they made the nation’s first Si planar transistor in April 1965 and, subsequently, the first IC and MOSFET in August 1966, which strongly forms the foundation of Taiwan’s hi-tech development. From 1977 to 1987, he single-handedly established a strong electrical engineering and computer science program at the NCKU, where GaAs, α-Si, and poly-Si research was established in Taiwan for the first time. He consecutively served as the Dean of Research (1987–1990), the Dean of Engineering (1990–1994), and the Dean of Electrical Engineering and Computer Science (1994–1995). Simultaneously, from 1990 to 1997, he served as the Founding President of the National Nano Device Laboratories, Hsinchu. Since August 1, 1998, he has been the President with the Institute of Electronics, NCTU. In 2002, to establish a strong system design capability, he initiated the “National program of system on chip,” which is based on a strong Taiwanese semiconductor foundry.
Dr. Chang is a Member of Academia Sinica (1996) and a Foreign Associate of the National Academy of Engineering, U.S. (2000). He was a recipient of the 1987 IEEE Fellow Award, the 2000 Third Millennium Medal, and the 2007 Nikkei Asia Prize for Science category in Japan and regarded as “the father of Taiwan semiconductor industries.”
