IEEE ELECTRON DEVICE LETTERS, VOL. 24, NO. 4, APRIL 2003 Silicon Devices 269
Substrate Bias Dependence of Breakdown
Progression in Ultrathin Oxide pMOSFETs
C. W. Tsai, Student Member, IEEE, M. C. Chen, Student Member, IEEE, S. H. Gu, Student Member, IEEE, and
Tahui Wang, Senior Member, IEEE
Abstract—Negative substrate bias-enhanced oxide breakdown (BD) progression in ultrathin oxide (1.4 nm) pMOS is observed. The enhanced progression is attributed to the increase of hole-stress current resulting from BD-induced, channel-carrier heating. The carrier temperature extracted from the spectral distribution of hot-carrier luminescence is around 1300 K. The substrate bias dependence of post-BD hole-tunneling current is confirmed from measurement and calculation. The observed phenomenon is par-ticularly significant to ultrathin gate oxide reliability in floating substrate (SOI) and forward-biased substrate devices.
Index Terms—Breakdown (BD) progression, carrier tempera-ture, substrate bias, ultrathin oxide pMOS.
I. INTRODUCTION
G
ATE-oxide breakdown (BD) has been considered as one of the most critical reliability issues for aggressive scaling of oxide thickness. In ultrathin oxide devices, oxide BD is evolved in a progressive way and the oxide leakage current increases slowly with stress time [1]–[3]. Previous study has shown that a small increase in gate leakage due to oxide BD is considered to be nondestructive for circuit operation [4]. The oxide failure time is thus determined by BD hardness involved in a progressive process, or in other words, by BD evolution rate.A forward-substrate bias ( ) is sometimes employed in cer-tain analog and digital MOS circuits to achieve improved device characteristics [5]. In addition, the floating body configuration of partially depleted floating substrate (SOI) CMOS will result in a nonzero body voltage due to various body-charging mecha-nisms [6], [7]. Although the dependence of oxide BD on has been widely explored [8], [9], a forward effect on the evolu-tion of oxide BD is rarely investigated.
In this work, we observe for the first time that oxide BD pro-gression in a 1.4-nm oxide pMOS exhibits distinct depen-dence. The devices were stressed at a high gate voltage (
V) until the onset of BD ( ), and then the devices were subjected to a lower gate voltage stress ( V) with dif-ferent substrate bias to study the evolution of oxide BD. The Weibull distribution of oxide failure time ( ) for different stress is shown in Fig. 1 by assuming that oxide failure is defined as ten times increase in gate current. Apparently, a
for-Manuscript received January 10, 2003. This work was supported by yhe Na-tiona Council of Taiwan, R.O.C., under Grant NSC 90-2215-E009-069 and from UMC, Taiwan (89C189). The review of this letter was arranged by Editor B. Yu. The authors are with the Department of Electronics Engineering, National Chiao-Tung University, Hsinchu, Taiwan, R.O.C. (e-mail:twang@cc.nctu.edu. tw).
Digital Object Identifier 10.1109/LED.2003.810890
Fig. 1. Weibull plot of oxide failure time (t ) for a 1.4-nm oxide pMOS. StressV is 03 V and V is 00.5, 0, and 0.5 V. The t is defined as an increase of gate current by ten times. The device area is 22 2 m.
Fig. 2. Charge separation measurement result of electron current (I ) and hole current (I ) versus substrate bias. The inset shows the electron and hole current flows at a negative gate bias. In measurement, source, drain, and substrate are grounded, and the gate voltage is01.5 V. The hole-tunneling current is measured at the source, and the drain and the electron current is measured at the substrate.
ward aggravates BD evolution, and the responsible mecha-nism will be discussed.
II. MECHANISM FORENHANCEDBD PROGRESSION
To investigate the role of in BD evolution, we analyze the polarity of stress-gate current first by using charge-separation measurement. The gate current in an ultrathin oxide (1.4 nm) pMOS is found to have comparable electron ( ) and hole ( ) components at a negative gate bias. Fig. 2 shows that the domi-nant component after is the hole current. Unlike and in a fresh device, the post- hole current increases signifi-cantly with a negative . By comparing the dependence of
270 IEEE ELECTRON DEVICE LETTERS, VOL. 24, NO. 4, APRIL 2003 Silicon Devices
Fig. 3. Measured spectral distribution of light emission (I ) after oxide breakdown. The dashed line represents the Boltzmann tail with a carrier temperature of 1300 K.V = 02:5 V.
post- and , we exclude the possibility that the de-pendence of the post- hole current is caused by the change of effective gate-to-channel bias in the BD spot [2] resulting from modulated channel resistance. Otherwise, the post- elec-tron tunneling current ( ) should exhibit the same depen-dence. Furthermore, substrate impact ionization [9] and neg-ative bias temperature instability (NBTI) effects are also ex-cluded, since the trend of the dependence is opposite.
Fig. 3 shows the measured spectral distribution of hot carrier light emission after . The measurement is performed with a Hamamatsu C3230 single photon counting system. The photon number at different wavelengths is counted individually. The measurement result is then corrected for the wavelength depen-dence of the filter transmittance. The pre- light emission is negligible and is not shown here. The extracted carrier tempera-ture from the high-energy tail of the spectrum is around 1300 K. There are two theories to explain the rise of carrier temperature after BD [10], [11]. First, based on the model proposed in [10], the gate voltage will penetrate into the substrate after BD and cause lateral field heating of channel carriers. This mechanism is unlikely here because the post- does not exhibit de-pendence, as pointed out earlier. The second explanation is that high-dissipated energy, released by valence electrons ( ) from the gate through the BD path, will locally produce a temperature rise of holes in the channel [11].
III. SIMULATION OFHOLE-TUNNELINGCURRENT
To show that the rise of hole temperature may account for the dependence of post- , we calculate the hole-tun-neling current from to 1300 K. In our calculation, we solved the coupled Poisson and Schrodinger equation to obtain the valence band diagram. A single band effective mass approx-imation is used. The hole direct-tunneling current can be calcu-lated through the Tsu Esaki equation [12]. See (1), shown at the bottom of the page, where is the hole effective mass in Si, ( ) denotes the Fermi energy in the channel ( -poly), stands for the th subband energy, and is the hole tun-neling probability. Other variables have their usual definitions.
Fig. 4. (a) Simulated substrate bias effect on hole-tunneling current for different hole temperatures. The hole current is normalized to its value atV =
0:5 V. (b) Distribution of channel holes in the lowest three subbands. The gate
bias in simulation is01.5 V. The parameters used in simulation is m (Si) =
0:67m , m (SiO ) = 0:55m , (hole barrier height at SiO interface) = 4:25 eV, t = 1:4 nm, and N (substrate doping) = 1 2 10 cm . The
density of states massm (Si) is treated as a fitting parameter.
It should be emphasized that it is not our intention here to calcu-late detailed charge transport in the BD path since the effective oxide thickness after is not known. Instead, our purpose is to investigate the influence of hole temperature on hole distribution in subbands and corresponding effect on hole-tunneling cur-rent. Therefore, the simple Wentzel–Kramers–Brillouin (WKB) formula for direct tunneling is employed. Our result in Fig. 4(a) clearly shows that the hole-tunneling current exhibits larger dependence at a higher temperature. The simulation can well in-terpret the measured dependence of post- by simply using an elevated hole temperature. To further explain the tem-perature effect on the dependence, the distribution of channel holes in the lowest three subbands is given in Fig. 4(b). Be-fore , hole temperature is 300 K. Most of inversion holes reside in the first subband, regardless of , for example, 99.9% at V versus 98% at V. In other words, the effect on hole-tunneling current is small at 300 K. After , the hole temperature is increased. For V, since the substrate confinement field is large, a large part of holes (81%) still stay in the first subband, although the hole temperature is rather high (1300 K), but for V, the confinement substrate field is small, and a large portion of holes are thermally excited to higher sub-bands, where the oxide tunneling probability is large.
TSAI et al.: SUBSTRATE BIAS DEPENDENCE OF BREAKDOWN PROGRESSION IN ULTRATHIN OXIDE pMOSFETs 271
A larger hole-tunneling current is obtained. Thus, the substrate bias effect on hole-tunneling current becomes more significant at a higher hole temperature.
IV. CONCLUSION
BD evolution in ultrathin oxide pMOS is aggravated by a forward-substrate bias. Numerical analysis shows that the en-hanced BD evolution can be explained by a rise of substrate hole temperature and thus increased hole stress current. The ac-celerated BD evolution has large impact on circuit lifetime in forward-biased substrate or SOI devices.
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